CN204314873U - A kind of I2C buffer circuit and I2C bus system - Google Patents
A kind of I2C buffer circuit and I2C bus system Download PDFInfo
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- CN204314873U CN204314873U CN201420836961.1U CN201420836961U CN204314873U CN 204314873 U CN204314873 U CN 204314873U CN 201420836961 U CN201420836961 U CN 201420836961U CN 204314873 U CN204314873 U CN 204314873U
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Abstract
This application discloses a kind of I2C buffer circuit and bus system.Described circuit: go out inbound port at the data-signal of host node device and go out between inbound port to access a pair metal-oxide-semiconductor from the data-signal of node device, described two metal-oxide-semiconductors drain electrode short circuit, its grid together connects the switch controlling signal output port of host node device; Access a pair metal-oxide-semiconductor between clock signal output terminal mouth at host node device and the clock signal receiving port from node device, described two metal-oxide-semiconductors drain electrode short circuit, its grid together connects the switch controlling signal output port of host node device.The embodiment of the present application, adopt metal-oxide-semiconductor design, its circuit structure is simple and cost is lower, makes this circuit be easy to realize, and can solve the complicated problem not easily realized of the circuit existed in prior art.
Description
Technical field
The application relates to communication technical field, particularly relates to a kind of I2C buffer circuit and I2C bus system.
Background technology
In communication power supply, often use I2C (Inter-Integrated Circuit) bus.I2C bus is twin wire universal serial bus, for connecting microcontroller and peripherals, is a kind of bus standard that the microelectronics communications field extensively adopts.
With reference to Fig. 1, it is the structural drawing of the I2C bus system of prior art.As shown in Figure 1, in I2C bus system, each host node device 10 can mount multiple from node device 11.
In actual applications, when host node device 10 is in running order, if directly will be articulated to host node device 10 from node device 11, and realize host node device 10 and the data communication from node device 11, then be easy to make the normal work of host node device 10 to be affected, and cause damage to host node device 10 with from the serviceable life of node device 11.
For this reason, need to design suitable buffer circuit 12, when host node device 10 is in running order, realize isolating from the circuit of node device 11 and host node device 10; When host node device 10 is in idle condition, then realize the level conversion from node device 11 and host node device 10, complete and access from the communication of node device 11.
The I2C buffer circuit that prior art adopts, all has circuit complexity, realizes the higher defect of cost.Therefore, how designing that to obtain structure simple and be easy to the I2C buffer circuit that realizes, is the technical matters that those skilled in the art are badly in need of solving.
Utility model content
The application provides a kind of I2C buffer circuit and I2C bus system, complicated with the circuit that the I2C buffer circuit solving prior art exists, realize the higher problem of cost.
According to the first aspect of the embodiment of the present application, provide a kind of I2C buffer circuit, described circuit is for being linked into host node device from node device in I2C system;
Described circuit comprises: the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance;
Wherein, described in the source electrode of described first metal-oxide-semiconductor and a termination of the first resistance, the data-signal of host node device goes out inbound port; The bus level of another termination I2C control end of described first resistance;
The drain electrode of described first metal-oxide-semiconductor connects the drain electrode of described second metal-oxide-semiconductor; After the grid of described first metal-oxide-semiconductor and the grid short circuit of described second metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
Inbound port is gone out from the data-signal of node device described in the source electrode of described second metal-oxide-semiconductor and a termination of described 3rd resistance; The bus level of another termination I2C equipment end of described 3rd resistance;
The clock signal output terminal mouth of host node device described in the source electrode of described 3rd metal-oxide-semiconductor and a termination of described second resistance; The bus level of I2C control end described in another termination of described second resistance;
The drain electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 4th metal-oxide-semiconductor; After the grid of described 3rd metal-oxide-semiconductor and the grid short circuit of described 4th metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
From the clock signal receiving port of node device described in the source electrode of described 4th metal-oxide-semiconductor and a termination of described 4th resistance; The bus level of I2C equipment end described in another termination of described 4th resistance;
Wherein, described circuit meets:
V
I2C_EN-VCCA≤V
GS_th
V
I2C_EN-VCCB≤V
GS_th
V
I2C_EN≥V
GS_th
Described V
i2C_ENfor the level magnitudes of the control signal that the switch controlling signal output port of described host node device exports; Described VCCA is the bus level of I2C control end; Described VCCB is the bus level of I2C equipment end; Described V
gS_thfor the minimum cut-in voltage threshold value of metal-oxide-semiconductor each in described circuit;
When described host node device is in acquiescence or duty, described V
i2C_ENfor low level; When described host node device is in idle condition, described V
i2C_ENfor high level.
Preferably, the value of described first resistance, the second resistance, the 3rd resistance and the 4th resistance is between 2.2K Ω to 4.7K Ω.
The embodiment of the present application also provides a kind of I2C bus system, in described I2C bus system, is respectively articulated in host node device from node device respectively by an I2C buffer circuit;
Described I2C buffer circuit comprises: the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance;
Wherein, described in the source electrode of described first metal-oxide-semiconductor and a termination of the first resistance, the data-signal of host node device goes out inbound port; The bus level of another termination I2C control end of described first resistance;
The drain electrode of described first metal-oxide-semiconductor connects the drain electrode of described second metal-oxide-semiconductor; After the grid of described first metal-oxide-semiconductor and the grid short circuit of described second metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
Inbound port is gone out from the data-signal of node device described in the source electrode of described second metal-oxide-semiconductor and a termination of described 3rd resistance; The bus level of another termination I2C equipment end of described 3rd resistance;
The clock signal output terminal mouth of host node device described in the source electrode of described 3rd metal-oxide-semiconductor and a termination of described second resistance; The bus level of I2C control end described in another termination of described second resistance;
The drain electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 4th metal-oxide-semiconductor; After the grid of described 3rd metal-oxide-semiconductor and the grid short circuit of described 4th metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
From the clock signal receiving port of node device described in the source electrode of described 4th metal-oxide-semiconductor and a termination of described 4th resistance; The bus level of I2C equipment end described in another termination of described 4th resistance;
Wherein, described circuit meets:
V
I2C_EN-VCCA≤V
GS_th
V
I2C_EN-VCCB≤V
GS_th
V
I2C_EN≥V
GS_th
Described V
i2C_ENfor the level magnitudes of the control signal that the switch controlling signal output port of described host node device exports; Described VCCA is the bus level of I2C control end; Described VCCB is the bus level of I2C equipment end; Described V
gS_thfor the minimum cut-in voltage threshold value of metal-oxide-semiconductor each in described circuit.
Preferably, the value of described first resistance, the second resistance, the 3rd resistance and the 4th resistance is between 2.2K Ω to 4.7K Ω.
The I2C buffer circuit of the embodiment of the present application, can realize in I2C bus system, to host node device with from the controllable circuit isolation features between node device.By default or host node device in running order under, realize host node device and isolate from the circuit between node device, even if now will be articulated in host node device from node device, also can not realize host node device and from the data communication between node device, realize the hot plug of equipment room safety; Under host node device is in idle condition, realize host node device and from the level conversion between node device, thus realize in I2C bus system, host node device and from the normal data transfer between node device.
I2C buffer circuit described in the embodiment of the present application, adopt metal-oxide-semiconductor design, its circuit structure is simple and cost is lower, makes this circuit be easy to realize, and can solve the complicated problem not easily realized of the circuit existed in prior art.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the I2C bus system of prior art;
Fig. 2 is the structural drawing of the I2C bus system of the embodiment of the present application.
Embodiment
Here will be described exemplary embodiment in detail, its sample table shows in the accompanying drawings.When description below relates to accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawing represents same or analogous key element.Embodiment described in following exemplary embodiment does not represent all embodiments consistent with the application.On the contrary, they only with as in appended claims describe in detail, the example of apparatus and method that some aspects of the application are consistent.
Only for describing the object of specific embodiment at term used in this application, and not intended to be limiting the application." one ", " described " and " being somebody's turn to do " of the singulative used in the application and appended claims is also intended to comprise most form, unless context clearly represents other implications.It is also understood that term "and/or" used herein refer to and comprise one or more project of listing be associated any or all may combine.
Term first, second, third, etc. may be adopted although should be appreciated that to describe various information in the application, these information should not be limited to these terms.These terms are only used for the information of same type to be distinguished from each other out.Such as, when not departing from the application's scope, the first information also can be called as the second information, and similarly, the second information also can be called as the first information.Depend on linguistic context, word as used in this " if " can be construed as into " ... time " or " when ... time " or " in response to determining ".
The object of the application is to provide a kind of I2C buffer circuit and I2C bus system, can realize in I2C system from the level conversion between node device and host node device and circuit isolation, thus the voltage matches of equipment and I2C bus can be realized, and the hot plug between support equipment; And circuit structure described in the embodiment of the present application is simple, cost is lower, is easy to realize.
With reference to Fig. 2, it is the structural drawing of the I2C bus system of the embodiment of the present application.
As shown in Figure 2, host node device 20 and at least one is from node device 21.Wherein, to be eachly articulated in described host node device 20 from node device 21 respectively by an I2C buffer circuit 22.By described I2C buffer circuit 22, host node device 20 can be realized and isolate from the level conversion between node device 21 and circuit.
It should be noted that, comprise two bus lines in I2C bus system: serial data line SDA and serial time clock line SCL.
As shown in Figure 2, the clock signal in I2C system is one way signal, is sent by the clock signal output terminal mouth SCL_S of host node device 20, is received by the clock signal receiving port SCL_C from node device 21.
Data-signal in I2C system is two-way signaling.Wherein, data-signal can go out inbound port SDA_S by the data-signal of host node device 20 and send, and goes out inbound port SDA_C receive by the data-signal from node device 21.Data-signal also can be gone out inbound port SDA_C and send by the data-signal from node device 21, go out inbound port SDA_S receive by the data-signal of host node device 20.
In actual applications, when host node device 20 is in Access status, can not directly be linked into from node device 21 on host node device 20.Now to realize the hot plug of equipment room, just need realize host node device 20 by I2C buffer circuit 22 and isolate from the circuit between node device 21.
On the other hand, when host node device 20 enters idle condition, host node device 20 can be linked into by from node device 21, now, need this I2C buffer circuit 22 can realize host node device 20 and from the level conversion between node device 21, thus ensure the normal work of I2C bus system.
In the I2C buffer circuit 22 that the embodiment of the present application provides, only need to adopt common MOS (Metal-Oxid-Semiconductor, Metal-oxide-semicondutor) field effect transistor can realize I2C buffer circuit 22, realize in I2C system, host node device 20 and between node device 21 circuit isolation and level conversion, its circuit structure is simple, realizes cost lower.
Shown in Fig. 2, the I2C buffer circuit 22 described in the embodiment of the present application is described in detail.
As shown in Figure 2, described I2C buffer circuit 22 comprises: the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, the 4th metal-oxide-semiconductor Q4, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4.
Wherein, the data-signal of the source electrode of described first metal-oxide-semiconductor Q1 and a termination host node device 20 of the first resistance R1 goes out inbound port SDA_S; The bus level VCCA of another termination I2C control end of described first resistance R1.
The drain electrode of described first metal-oxide-semiconductor Q1 connects the drain electrode of described second metal-oxide-semiconductor Q2; After the grid of described first metal-oxide-semiconductor Q1 and the grid short circuit of described second metal-oxide-semiconductor Q2, meet the switch controlling signal output port GPIO (General Purpose Input Output, universal input/output) of host node device 20.
The source electrode of described second metal-oxide-semiconductor Q2 and a termination of described 3rd resistance R3 go out inbound port SDA_C from the data-signal of node device 21; The bus level VCCB of another termination I2C equipment end of described 3rd resistance R3.
The clock signal output terminal mouth SCL_S of the source electrode of described 3rd metal-oxide-semiconductor Q3 and a termination host node device 20 of the second resistance R2; The bus level VCCA of another termination I2C control end of described second resistance R2.
The drain electrode of described 3rd metal-oxide-semiconductor Q3 connects the drain electrode of described 4th metal-oxide-semiconductor Q4; After the grid of described 3rd metal-oxide-semiconductor Q3 and the grid short circuit of described 4th metal-oxide-semiconductor Q4, meet the switch controlling signal output port GPIO of host node device 20.
The source electrode of described 4th metal-oxide-semiconductor Q4 and a termination of described 4th resistance R4 are from the clock signal receiving port SCL_C of node device 21; The bus level VCCB of another termination I2C equipment end of described 4th resistance R4.
It should be noted that, described in the embodiment of the present application, I2C buffer circuit must meet the following conditions:
V
I2C_EN-VCCA≤V
GS_th(1)
V
I2C_EN-VCCB≤V
GS_th(2)
V
I2C_EN≥V
GS_th(3)
Wherein, V
i2C_ENfor the level magnitudes of the control signal I2C_EN that the switch controlling signal output port of described host node device exports; VCCA is the bus level of I2C control end; VCCB is the bus level of I2C equipment end; V
gS_thfor the minimum cut-in voltage threshold value of each metal-oxide-semiconductor in this I2C buffer circuit.
In the embodiment of the present application, each in I2C bus system is articulated in host node device 20 from node device 21 respectively by an I2C buffer circuit 22.Described I2C buffer circuit 22, when detecting that host node device 20 is in running order, realizes host node device 20 and isolates from the circuit between node device 21; When detecting that host node device 20 is in idle condition, realizing host node device 20 and from the level conversion between node device 21, realizing the data transmission in I2C bus system.
Thus, in the embodiment of the present application, what utilize metal-oxide-semiconductor can turn-off characteristic, and achieving can the I2C buffer circuit of switch control rule, thus to realize in I2C system host node device 20 and from the hot plug between node device 21.I2C buffer circuit described in the embodiment of the present application, adopt metal-oxide-semiconductor design, its circuit structure is simple and cost is lower, makes this circuit be easy to realize, and can solve the complicated problem not easily realized of the circuit existed in prior art.
Below the principle of work of the I2C buffer circuit described in the embodiment of the present application is explained in detail.
As shown in Figure 2, for host node device 20, by default or host node device 20 in running order under, its switch controlling signal output port GPIO export control signal I2C_EN be low level.
For data-signal transmission channel: the grid of described first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 and voltage between source electrodes Vgs are 0 or for negative bias, parasitic diode in metal-oxide-semiconductor, because of anti-phase series connection, makes the first metal-oxide-semiconductor Q1 and the second metal-oxide-semiconductor Q2 all be in off state.Make thus, the data-signal of host node device 20 goes out inbound port SDA_S and goes out between inbound port SDA_C from the data-signal of node device 21 is not conducting, is host node device 20 and from the data-signal transmission channel not conducting between node device 21.
For clock signal transmission passage: the grid of described 3rd metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4 and voltage between source electrodes Vgs are 0 or for negative bias, parasitic diode in metal-oxide-semiconductor, because of anti-phase series connection, makes the 3rd metal-oxide-semiconductor Q3 and the 4th metal-oxide-semiconductor Q4 all be in off state.Make thus, the clock signal output terminal mouth SCL_S of host node device 20 and be not conducting between the clock signal receiving port SCL_C of node device 21, be host node device 20 and from the clock signal transmission passage not conducting between node device 21.
Can be implemented under default conditions thus and host node device 20 in running order under, host node device 20 and from the circuit isolation between node device 21.Now, even if will be articulated in host node device 20 from node device 21, also can not directly realize accessing from node device 21 to the communication of host node device 20, thus can be good at the work safety ensureing host node device 20, realize in I2C system, host node device 20 and from the hot plug between node device 21.
As shown in Figure 2, for host node device 20, under host node device 20 is in idle condition, the control signal I2C_EN that its switch controlling signal output port GPIO exports is high level.
For data-signal transmission channel:
When the data-signal of host node device 20 goes out inbound port SDA_S output low level, control signal I2C_EN is high level, because this I2C buffer circuit 22 meets V
i2C_EN>=V
gS_th, grid and the voltage between source electrodes Vgs of described first metal-oxide-semiconductor Q1 reach positive bias, make a MOD pipe Q1 conducting.Due to parasitic diode, grid and the voltage between source electrodes Vgs of the second metal-oxide-semiconductor Q2 also reach positive bias, make the second metal-oxide-semiconductor Q2 also conducting.Now, go out from the data-signal of node device 21 output signal that data-signal that data-signal that inbound port SDA_C receives follows host node device 20 goes out inbound port SDA_S, be all low level.
When going out inbound port SDA_C output low level from the data-signal of node device 21, control signal I2C_EN is high level, because this I2C buffer circuit 22 meets V
i2C_EN-VCCA≤V
gS_th, grid and the voltage between source electrodes Vgs of described second metal-oxide-semiconductor Q2 reach positive bias, make the 2nd MOD pipe Q2 conducting.Due to parasitic diode, grid and the voltage between source electrodes Vgs of the first metal-oxide-semiconductor Q1 also reach positive bias, make the first metal-oxide-semiconductor Q1 also conducting.Now, the data-signal of host node device 20 goes out the data-signal that inbound port SDA_S receives and follows the output signal going out inbound port SDA_C from the data-signal of node device 21, is all low level.
When the data-signal of host node device 20 goes out inbound port SDA_S output high level, control signal I2C_EN is high level, because this I2C buffer circuit 22 meets V
i2C_EN-VCCA≤V
gS_th, the grid of described first metal-oxide-semiconductor Q1 and voltage between source electrodes Vgs are 0 or negative bias, make the first metal-oxide-semiconductor Q1 be in off state.Meanwhile, because this I2C buffer circuit 22 also meets V
i2C_EN-VCCB≤V
gS_th, the grid of described second metal-oxide-semiconductor Q2 and voltage between source electrodes Vgs are also 0 or negative bias, make the second metal-oxide-semiconductor Q2 also be in off state.Now, going out inbound port SDA_C by the 3rd resistance R3 pull-up from the data-signal of node device 21 is high level.Make thus, go out from the data-signal of node device 21 output signal that data-signal that data-signal that inbound port SDA_C receives follows host node device 20 goes out inbound port SDA_S, be all high level.
When going out inbound port SDA_C from the data-signal of node device 21 and exporting high level, control signal I2C_EN is high level, because this I2C buffer circuit 22 meets V
i2C_EN-VCCB≤V
gS_th, the grid of described second metal-oxide-semiconductor Q2 and voltage between source electrodes Vgs are 0 or negative bias, make the second metal-oxide-semiconductor Q2 be in off state.Meanwhile, because this I2C buffer circuit 22 also meets V
i2C_EN-VCCA≤V
gS_th, the grid of described first metal-oxide-semiconductor Q1 and voltage between source electrodes Vgs are also 0 or negative bias, make the first metal-oxide-semiconductor Q1 also be in off state.Now, the data-signal of host node device 20 goes out inbound port SDA_S by the first resistance R1 pull-up is high level.Make thus, the data-signal of host node device 20 goes out the data-signal that inbound port SDA_S receives and follows the output signal going out inbound port SDA_C from the data-signal of node device 21, is all high level.
For clock signal transmission passage:
When the clock signal output terminal mouth SCL_S output low level of host node device 20, control signal I2C_EN is high level, because this I2C buffer circuit 22 meets V
i2C_EN>=V
gS_th, grid and the voltage between source electrodes Vgs of described 3rd metal-oxide-semiconductor Q3 reach positive bias, make the 3rd MOD pipe Q3 conducting.Due to parasitic diode, grid and the voltage between source electrodes Vgs of the 4th metal-oxide-semiconductor Q4 also reach positive bias, make the 4th metal-oxide-semiconductor Q4 also conducting.Now, the clock signal received from the clock signal receiving port SCL_C of node device 21 follows the output signal of the clock signal output terminal mouth SCL_S of host node device 20, is all low level.
When the clock signal output terminal mouth SCL_S of host node device 20 exports high level, control signal I2C_EN is high level, because this I2C buffer circuit 22 meets V
i2C_EN-VCCA≤V
gS_th, the grid of described 3rd metal-oxide-semiconductor Q3 and voltage between source electrodes Vgs are 0 or negative bias, make the 3rd metal-oxide-semiconductor Q3 be in off state.Meanwhile, because this I2C buffer circuit 22 also meets V
i2C_EN-VCCB≤V
gS_th, the grid of described 4th metal-oxide-semiconductor Q4 and voltage between source electrodes Vgs are also 0 or negative bias, make the 4th metal-oxide-semiconductor Q4 also be in off state.Now, be high level from the clock signal receiving port SCL_C of node device 21 by the 4th resistance R4 pull-up.Make thus, the clock signal received from the clock signal receiving port SCL_C of node device 21 follows the output signal of the clock signal output terminal mouth SCL_S of host node device 20, is all high level.
Can be implemented under host node device 20 is in idle condition thus, host node device 20 and the level conversion from the data transmission channel between node device 21.Now, can realize, from node device 21 to the communication of host node device 20 access, realizing host node device 20 and transmitting from the data between node device 21.
As seen from the above description, the I2C buffer circuit 22 of the embodiment of the present application, can realize in I2C bus system, to host node device 20 with from the controllable circuit isolation features between node device 21.Concrete, by default or host node device 20 in running order under, realize host node device 20 and isolate from the circuit between node device 21, even if now will be articulated in host node device 20 from node device 21, also can not realize host node device 20 and from the data communication between node device 21, realize the hot plug of equipment room safety; Under host node device 20 is in idle condition, realize host node device 20 and from the level conversion between node device 21, thus realize in I2C bus system, host node device 20 and from the normal data transfer between node device 21.
I2C buffer circuit described in the embodiment of the present application, adopt metal-oxide-semiconductor design, its circuit structure is simple and cost is lower, makes this circuit be easy to realize, and can solve the complicated problem not easily realized of the circuit existed in prior art.
Need to further illustrate, in the embodiment of the present application, the input capacitance that can set each metal-oxide-semiconductor is as far as possible little.Concrete, in this I2C bus system, the summation of the input capacitance of all I2C equipment (host node device and from node device) is less than the code requirement of I2C.
What needs further illustrated is, in the embodiment of the present application, in described I2C buffer circuit 22, described first resistance R1, the second resistance R2, the 3rd resistance R3 and the 4th resistance R4 are pull-up resistor, for the level of clock signal or data-signal is pulled to required voltage.
Preferably, the value of described first resistance R1, the second resistance R2, the 3rd resistance R3 and the 4th resistance R4 can be between 2.2K Ω to 4.7K Ω.
Certainly, in actual applications, each resistance value of this I2C buffer circuit 22 does not limit to and above-mentioned value.In actual applications, only need specifically to set according to the resistance of concrete value to the first resistance R1, the second resistance R2, the 3rd resistance R3 and the 4th resistance R4 of I2C control end bus level VCCA and I2C equipment end bus level VCCB.
Those skilled in the art, at consideration instructions and after putting into practice utility model disclosed herein, will easily expect other embodiment of the application.The application is intended to contain any modification of the application, purposes or adaptations, and these modification, purposes or adaptations are followed the general principle of the application and comprised the undocumented common practise in the art of the application or conventional techniques means.Instructions and embodiment are only regarded as exemplary, and true scope and the spirit of the application are pointed out by claim below.
Should be understood that, the application is not limited to precision architecture described above and illustrated in the accompanying drawings, and can carry out various amendment and change not departing from its scope.The scope of the application is only limited by appended claim.
Claims (4)
1. an I2C buffer circuit, is characterized in that, described circuit is for being linked into host node device from node device in I2C system;
Described circuit comprises: the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance;
Wherein, described in the source electrode of described first metal-oxide-semiconductor and a termination of the first resistance, the data-signal of host node device goes out inbound port; The bus level of another termination I2C control end of described first resistance;
The drain electrode of described first metal-oxide-semiconductor connects the drain electrode of described second metal-oxide-semiconductor; After the grid of described first metal-oxide-semiconductor and the grid short circuit of described second metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
Inbound port is gone out from the data-signal of node device described in the source electrode of described second metal-oxide-semiconductor and a termination of described 3rd resistance; The bus level of another termination I2C equipment end of described 3rd resistance;
The clock signal output terminal mouth of host node device described in the source electrode of described 3rd metal-oxide-semiconductor and a termination of described second resistance; The bus level of I2C control end described in another termination of described second resistance;
The drain electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 4th metal-oxide-semiconductor; After the grid of described 3rd metal-oxide-semiconductor and the grid short circuit of described 4th metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
From the clock signal receiving port of node device described in the source electrode of described 4th metal-oxide-semiconductor and a termination of described 4th resistance; The bus level of I2C equipment end described in another termination of described 4th resistance;
Wherein, described circuit meets:
V
I2C_EN-VCCA≤V
GS_th
V
I2C_EN-VCCB≤V
GS_th
V
I2C_EN≥V
GS_th
Described V
i2C_ENfor the level magnitudes of the control signal that the switch controlling signal output port of described host node device exports; Described VCCA is the bus level of I2C control end; Described VCCB is the bus level of I2C equipment end; Described V
gS_thfor the minimum cut-in voltage threshold value of metal-oxide-semiconductor each in described circuit;
When described host node device is in acquiescence or duty, described V
i2C_ENfor low level; When described host node device is in idle condition, described V
i2C_ENfor high level.
2. I2C buffer circuit according to claim 1, is characterized in that, the value of described first resistance, the second resistance, the 3rd resistance and the 4th resistance is between 2.2K Ω to 4.7K Ω.
3. an I2C bus system, is characterized in that, in described I2C bus system, is respectively articulated in host node device from node device respectively by an I2C buffer circuit;
Described I2C buffer circuit comprises: the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance;
Wherein, described in the source electrode of described first metal-oxide-semiconductor and a termination of the first resistance, the data-signal of host node device goes out inbound port; The bus level of another termination I2C control end of described first resistance;
The drain electrode of described first metal-oxide-semiconductor connects the drain electrode of described second metal-oxide-semiconductor; After the grid of described first metal-oxide-semiconductor and the grid short circuit of described second metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
Inbound port is gone out from the data-signal of node device described in the source electrode of described second metal-oxide-semiconductor and a termination of described 3rd resistance; The bus level of another termination I2C equipment end of described 3rd resistance;
The clock signal output terminal mouth of host node device described in the source electrode of described 3rd metal-oxide-semiconductor and a termination of described second resistance; The bus level of I2C control end described in another termination of described second resistance;
The drain electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 4th metal-oxide-semiconductor; After the grid of described 3rd metal-oxide-semiconductor and the grid short circuit of described 4th metal-oxide-semiconductor, connect the switch controlling signal output port of described host node device;
From the clock signal receiving port of node device described in the source electrode of described 4th metal-oxide-semiconductor and a termination of described 4th resistance; The bus level of I2C equipment end described in another termination of described 4th resistance;
Wherein, described circuit meets:
V
I2C_EN-VCCA≤V
GS_th
V
I2C_EN-VCCB≤V
GS_th
V
I2C_EN≥V
GS_th
Described V
i2C_ENfor the level magnitudes of the control signal that the switch controlling signal output port of described host node device exports; Described VCCA is the bus level of I2C control end; Described VCCB is the bus level of I2C equipment end; Described V
gS_thfor the minimum cut-in voltage threshold value of metal-oxide-semiconductor each in described circuit.
4. I2C bus system according to claim 3, is characterized in that, the value of described first resistance, the second resistance, the 3rd resistance and the 4th resistance is between 2.2K Ω to 4.7K Ω.
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| CN201420836961.1U CN204314873U (en) | 2014-12-24 | 2014-12-24 | A kind of I2C buffer circuit and I2C bus system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107678999A (en) * | 2017-10-25 | 2018-02-09 | 东莞博力威电池有限公司 | A kind of I2C isolation circuits |
| CN109243389A (en) * | 2018-10-15 | 2019-01-18 | 深圳市华星光电技术有限公司 | LCD circuit and display |
| CN109545157A (en) * | 2018-11-09 | 2019-03-29 | 深圳市华星光电技术有限公司 | A kind of universal serial bus isolating device and liquid crystal display panel |
-
2014
- 2014-12-24 CN CN201420836961.1U patent/CN204314873U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107678999A (en) * | 2017-10-25 | 2018-02-09 | 东莞博力威电池有限公司 | A kind of I2C isolation circuits |
| CN109243389A (en) * | 2018-10-15 | 2019-01-18 | 深圳市华星光电技术有限公司 | LCD circuit and display |
| WO2020077857A1 (en) * | 2018-10-15 | 2020-04-23 | 深圳市华星光电技术有限公司 | Liquid crystal display circuit and display |
| CN109545157A (en) * | 2018-11-09 | 2019-03-29 | 深圳市华星光电技术有限公司 | A kind of universal serial bus isolating device and liquid crystal display panel |
| WO2020093587A1 (en) * | 2018-11-09 | 2020-05-14 | 深圳市华星光电技术有限公司 | Serial bus disconnection device and liquid crystal display panel |
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