CN204305403U - Based on the mixed type raster data model system of power amplification circuit and energizing circuit - Google Patents
Based on the mixed type raster data model system of power amplification circuit and energizing circuit Download PDFInfo
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- CN204305403U CN204305403U CN201420717055.XU CN201420717055U CN204305403U CN 204305403 U CN204305403 U CN 204305403U CN 201420717055 U CN201420717055 U CN 201420717055U CN 204305403 U CN204305403 U CN 204305403U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The utility model discloses a kind of mixed type raster data model system based on power amplification circuit and energizing circuit, primarily of driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, and the power drive amplifying circuit be arranged between self-locking optical excitation circuit and driving chip M forms, it is characterized in that, also be provided with respectively with boostrap circuit, the beam excitation formula logic amplifying circuit that self-locking optical excitation circuit is connected with power drive amplifying circuit.The utility model can excite the correlation function of driving chip M automatically according to outside illumination condition, without the need to increasing extra starting drive, therefore its power consumption is lower.Meanwhile, be only 1/4 of conventional gate drive circuit start-up time start-up time of the present utility model, its start-up time is extremely short.
Description
Technical field
The utility model relates to a kind of LED drive circuit, specifically refers to the mixed type raster data model system based on power amplification circuit and energizing circuit.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Utility model content
The purpose of this utility model is the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit, a kind of reasonable in design is provided, can effectively reduce energy consumption and current noise, obviously shorten the mixed type raster data model system based on power amplification circuit and energizing circuit of start-up time.
The purpose of this utility model is achieved through the following technical solutions: based on the mixed type raster data model system of power amplification circuit and energizing circuit, primarily of driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, and the power drive amplifying circuit be arranged between self-locking optical excitation circuit and driving chip M forms.Meanwhile, native system is also provided with the beam excitation formula logic amplifying circuit be connected with power drive amplifying circuit with boostrap circuit, self-locking optical excitation circuit respectively, described beam excitation formula logic amplifying circuit is primarily of power amplifier P4, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C13 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C13, the resistance R17 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R17, the polar capacitor C15 of minus earth, one end is connected with the negative input of NAND gate IC4, the resistance R18 that the other end is connected with the in-phase end of power amplifier P4, be serially connected in the resistance R19 between the end of oppisite phase of power amplifier P4 and output, one end is connected with the output of NAND gate IC4, the resistance R20 that the other end is connected with the negative input of NAND gate IC6, positive pole is connected with the output of NAND gate IC5, the electric capacity C14 that negative pole is connected with the negative input of NAND gate IC6, and one end is connected with the positive pole of polar capacitor C15, the resistance R21 that the other end is connected with the negative input of NAND gate IC5 forms, the electrode input end of described NAND gate IC4 is connected with the end of oppisite phase of power amplifier P4, and its output is connected with the electrode input end of NAND gate IC5, the electrode input end of NAND gate IC6 is connected with the output of power amplifier P4, and its output is then connected with power drive amplifying circuit, the output of power amplifier P4 is then connected with self-locking optical excitation circuit, and its in-phase end is connected with boostrap circuit.
Further, described power drive amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and end of oppisite phase and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and in-phase end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that colelctor electrode is connected with the in-phase end of power amplifier P3 after resistance R11, base stage is connected with the emitter stage of triode Q2, the triode Q3 that colelctor electrode is connected with the end of oppisite phase of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q4 that colelctor electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the end of oppisite phase of power amplifier P3, and negative pole is connected with the emitter stage of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q4, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter stage of triode Q4, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the colelctor electrode of triode Q2, the diode D2 of the extremely external-4V voltage of P forms, the end of oppisite phase of described power amplifier P1 is connected with the in-phase end of power amplifier P2, and its in-phase end is connected with self-locking optical excitation circuit, the end of oppisite phase of power amplifier P2 is connected with the output of NAND gate IC6, the output of power amplifier P3 is then connected with the TD pin of driving chip M.
Described homophase AC signal amplifying circuit is by power amplifier P, the resistance R7 that one end is connected with the VCC pin of driving chip M, the other end is connected with the in-phase end of power amplifier P, the resistance R6 that one end is connected with the end of oppisite phase of power amplifier P, the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the in-phase end of power amplifier P, the polar capacitor C4 of negative pole external power supply forms, the output of described power amplifier P is connected with the INP pin of driving chip M.
Described self-locking optical excitation circuit is by nor gate IC1, nor gate IC2, nor gate IC3, the photocell CDS that one end is connected with the in-phase end of power amplifier P, the other end is connected with the output of power amplifier P4 after potentiometer R5, and the electric capacity C3 be serially connected between the electrode input end of nor gate IC3 and output forms; The electrode input end of described nor gate IC1 is connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The output of described nor gate IC2 then simultaneously the negative input of AND OR NOT gate IC3 be connected with the in-phase end of power amplifier P1, the output of the output of nor gate IC3 then power amplifier P is connected; The output of described nor gate IC2 is then connected with the end of oppisite phase of power amplifier P after resistance R6.
Described boostrap circuit is by FET MOS, the resistance R4 that one end is connected with the source electrode of FET MOS, the other end is connected with the in-phase end of power amplifier P4, the polar capacitor C1 that negative pole is connected with the grid of FET MOS, positive pole is connected with the drain electrode of FET MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, the polar capacitor C2 that positive pole is connected with the positive pole of polar capacitor C1, the negative input of negative pole AND OR NOT gate IC2 is connected, and one end is connected with the positive pole of polar capacitor C2, the resistance R3 of other end ground connection forms; The drain electrode of described FET MOS is connected with the tie point of resistance R7 with photocell CDS.
Described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C5 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R8 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, colelctor electrode in turn after electric capacity C6 and electric capacity C7 ground connection and the transistor Q1 of grounded emitter form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, ground connection after its non-same polarity is then connected with the emitter stage of transistor Q1; Meanwhile, the emitter stage of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
For guaranteeing result of use of the present utility model, described driving chip M preferentially adopts LTC4440A integrated chip to realize.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) the utility model can excite the correlation function of driving chip M automatically according to outside illumination condition, and without the need to increasing extra starting drive, therefore its power consumption is lower.
(2) be only 1/4 of conventional gate drive circuit start-up time start-up time of the present utility model, its start-up time is extremely short.
(3) the utility model adopts boostrap circuit to provide control signal for self-locking optical excitation circuit and driving chip, therefore has very high input impedance, can guarantee the stable performance of whole circuit
(4) the utility model effectively can avoid external electromagnetic interference, can reduce current noise significantly.
(5) be provided with homophase AC signal amplifying circuit in the utility model, therefore can guarantee that the intensity of pulse signal can not decay, thus guarantee stable performance.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is power drive amplification circuit structure schematic diagram of the present utility model.
Detailed description of the invention
Below in conjunction with embodiment, the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, power amplification formula mixed type raster data model system of the present utility model, primarily of driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, be serially connected in the power drive amplifying circuit between self-locking optical excitation circuit and driving chip M, and respectively with self-locking optical excitation circuit, the beam excitation formula logic amplifying circuit composition that boostrap circuit is connected with power drive amplifying circuit.
For guaranteeing result of use, the high-frequency N channel mosfet grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
The structure of described power drive amplifying circuit as shown in Figure 2, namely it is primarily of power amplifier P1, power amplifier P2, power amplifier P3, triode Q2, triode Q3, triode Q4, be serially connected in the one-level RC filter circuit between the output of power amplifier P1 and end of oppisite phase, be serially connected in the secondary RC filter circuit between the output of power amplifier P2 and in-phase end, and resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, electric capacity C10, electric capacity C11, electric capacity C12 and diode D2 form.
Wherein, described one-level RC filtered electrical routing resistance R9 and electric capacity C8 is formed in parallel, namely between resistance R9 and the electric capacity C8 end of oppisite phase that is all serially connected in power amplifier P1 and output; Described secondary RC filter circuit is then formed in parallel by resistance R10 and electric capacity C9, namely between resistance R10 and the electric capacity C9 in-phase end that is all serially connected in power amplifier P2 and output.Meanwhile, the end of oppisite phase of power amplifier P1 is also connected with the in-phase end of power amplifier P2.
The base stage of triode Q2 is connected with the output of power amplifier P1, and its colelctor electrode is connected with the in-phase end of power amplifier P3 after resistance R11, and its emitter stage is then connected with the base stage of triode Q3; The colelctor electrode of triode Q3 is connected with the end of oppisite phase of power amplifier P3 after resistance R12, meanwhile, and the colelctor electrode also external+10V voltage of this triode Q3.
The base stage of triode Q4 is connected with the output of power amplifier P2 after resistance R13, and its colelctor electrode is then connected with the base stage of triode Q3 after resistance R16.Electric capacity C11 is then in parallel with resistance R13, and for guaranteeing effect, this electric capacity C11 preferentially adopts electrochemical capacitor to realize.During connection, the negative pole of electric capacity C11 is connected with the base stage of triode Q4, and its positive pole is then connected with the output of power amplifier P2.The positive pole of electric capacity C10 is connected with the end of oppisite phase of power amplifier P3, and its negative pole is then connected with the emitter stage of triode Q3.Meanwhile, the negative pole of this electric capacity C10 and the equal ground connection of emitter stage of triode Q3.
One end of resistance R14 is connected with the base stage of triode Q4, the voltage of the external-4V of its other end; And one end of resistance R15 is connected with the emitter stage of triode Q4, the voltage of its other end then external equally-4V.Electric capacity C12 is then in parallel with resistance R15.Equally, described electric capacity C10 and electric capacity C12 also all adopts electrochemical capacitor to realize.
The N pole of described diode D2 is connected with the colelctor electrode of triode Q2, and its P pole is at the voltage of external-4V.Meanwhile, the output of this power amplifier P3 will be connected with the TD pin of driving chip M.
For guaranteeing the normal operation of power amplifier P1 and power amplifier P2, this electric capacity C8 and electric capacity C9 all preferentially adopts patch capacitor to realize.And the resistance of resistance R9, resistance R10 is 10 K Ω, the resistance of resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16 is 20 K Ω.
Described homophase AC signal amplifying circuit is by power amplifier P, and resistance R7, resistance R6 and polar capacitor C4 form.During connection, one end of resistance R7 is connected with the VCC pin of driving chip M, and its other end is connected with the in-phase end of power amplifier P; And one end of resistance R6 is connected with the end of oppisite phase of power amplifier P, its other end is connected with self-locking optical excitation circuit.The positive pole of polar capacitor C4 is connected with the in-phase end of power amplifier P, its negative pole external power supply Vin.The output of described power amplifier P is connected with the INP pin of driving chip M, and for guaranteeing that power amplifier P can normally work, the magnitude of voltage of this external power supply Vin needs to be 6 ~ 12V.
Described beam excitation formula logic amplifying circuit is primarily of power amplifier P4, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C13 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C13, the resistance R17 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R17, the polar capacitor C15 of minus earth, one end is connected with the negative input of NAND gate IC4, the resistance R18 that the other end is connected with the in-phase end of power amplifier P4, be serially connected in the resistance R19 between the end of oppisite phase of power amplifier P4 and output, one end is connected with the output of NAND gate IC4, the resistance R20 that the other end is connected with the negative input of NAND gate IC6, positive pole is connected with the output of NAND gate IC5, the electric capacity C14 that negative pole is connected with the negative input of NAND gate IC6, and one end is connected with the positive pole of polar capacitor C15, the resistance R21 that the other end is connected with the negative input of NAND gate IC5 forms.
For guaranteeing effect, during connection, the electrode input end of described NAND gate IC4 is connected with the end of oppisite phase of power amplifier P4, and its output is connected with the electrode input end of NAND gate IC5; The electrode input end of NAND gate IC6 is connected with the output of power amplifier P4, and its output is then connected with the end of oppisite phase of power amplifier P2.
Self-locking optical excitation circuit is by nor gate IC1, and nor gate IC2, nor gate IC3, photocell CDS, potentiometer R5 and electric capacity C3 form.During connection, one end of photocell CDS is connected with the in-phase end of power amplifier P, and its other end is connected with the output of power amplifier P4 after potentiometer R5.This photocell CDS is once sense outside illumination, then its limit self-excitation can produce electric energy, for driving chip M.
Between the electrode input end that described electric capacity C3 is serially connected in nor gate IC3 and output, namely the positive pole of electric capacity C3 wants the electrode input end of AND OR NOT gate IC3 to be connected, and the output of its negative pole then AND OR NOT gate IC3 is connected.
Meanwhile, the electrode input end of nor gate IC1 will be connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected.The output of described nor gate IC2 then needs the negative pole of AND OR NOT gate IC3 simultaneously to enter end to be connected with the in-phase end of power amplifier P1, and the output of the output of nor gate IC3 then power amplifier P is connected.
The output of the other end AND OR NOT gate IC2 of described resistance R6 is connected, and namely the output of nor gate IC2 is connected with the end of oppisite phase of power amplifier P after resistance R6.Meanwhile, the inverting input of this nor gate IC2 will be connected with boostrap circuit.
Described boostrap circuit is made up of FET MOS, resistance R1, resistance R2, resistance R3, resistance R4 and polar capacitor C1 and polar capacitor C2.During connection, one end of resistance R4 is connected with the source electrode of FET MOS, the other end is connected with the in-phase end of power amplifier P4; The negative pole of polar capacitor C1 is connected with the grid of FET MOS, and its positive pole is connected with the drain electrode of FET MOS after resistance R1; Resistance R2 and polar capacitor C1 is in parallel, and the positive pole of polar capacitor C2 is connected with the positive pole of polar capacitor C1, and second input of its negative pole AND OR NOT gate IC2 is connected.
One end of resistance R3 is connected with the positive pole of polar capacitor C2, its other end ground connection.Meanwhile, the drain electrode needs of this FET MOS are connected with the tie point of resistance R7 with photocell CDS, to guarantee that photocell CDS can provide operating voltage for FET MOS.
Described drive circuit is then made up of transformer T, diode D1, electric capacity C5, resistance R8, electric capacity C6, electric capacity C7 and transistor Q1.During connection, the P pole of diode D1 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C5 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.For guaranteeing the normal operation of driving chip M, its VCC holds the voltage needing external+12V.
Resistance R8 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q1 is then connected with the TG pin of driving chip M, and its colelctor electrode is ground connection after electric capacity C6 and electric capacity C7 in turn, its grounded emitter.Meanwhile, the colelctor electrode of this transistor Q1 also needs the DC voltage of external+6V, to guarantee that transistor Q1 has enough bias voltages to drive himself conducting.
Described transformer T exports to outside FET after being used for that+the 6V of outside DC voltage is carried out transformation process.The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, ground connection after its non-same polarity is then connected with the emitter stage of transistor Q1.Meanwhile, the emitter stage of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present utility model.According to the situation of reality, user can only select any one or several port of these four outputs to use.
As mentioned above, just the utility model can well be realized.
Claims (7)
1. based on the mixed type raster data model system of power amplification circuit and energizing circuit, primarily of driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, the boostrap circuit be connected with this self-locking optical excitation circuit, and the power drive amplifying circuit be arranged between self-locking optical excitation circuit and driving chip M forms, it is characterized in that, also be provided with respectively with boostrap circuit, the beam excitation formula logic amplifying circuit that self-locking optical excitation circuit is connected with power drive amplifying circuit, described beam excitation formula logic amplifying circuit is primarily of power amplifier P4, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the in-phase end of power amplifier P4, the polar capacitor C13 of positive pole ground connection after optical diode D3, one end is connected with the positive pole of polar capacitor C13, the resistance R17 of other end ground connection after diode D4, positive pole is connected with the tie point of diode D4 with resistance R17, the polar capacitor C15 of minus earth, one end is connected with the negative input of NAND gate IC4, the resistance R18 that the other end is connected with the in-phase end of power amplifier P4, be serially connected in the resistance R19 between the end of oppisite phase of power amplifier P4 and output, one end is connected with the output of NAND gate IC4, the resistance R20 that the other end is connected with the negative input of NAND gate IC6, positive pole is connected with the output of NAND gate IC5, the electric capacity C14 that negative pole is connected with the negative input of NAND gate IC6, and one end is connected with the positive pole of polar capacitor C15, the resistance R21 that the other end is connected with the negative input of NAND gate IC5 forms, the electrode input end of described NAND gate IC4 is connected with the end of oppisite phase of power amplifier P4, and its output is connected with the electrode input end of NAND gate IC5, the electrode input end of NAND gate IC6 is connected with the output of power amplifier P4, and its output is then connected with power drive amplifying circuit, the output of power amplifier P4 is then connected with self-locking optical excitation circuit, and its in-phase end is connected with boostrap circuit.
2. the mixed type raster data model system based on power amplification circuit and energizing circuit according to claim 1, it is characterized in that, described power drive amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and end of oppisite phase and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and in-phase end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that colelctor electrode is connected with the in-phase end of power amplifier P3 after resistance R11, base stage is connected with the emitter stage of triode Q2, the triode Q3 that colelctor electrode is connected with the end of oppisite phase of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q4 that colelctor electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the end of oppisite phase of power amplifier P3, and negative pole is connected with the emitter stage of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q4, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter stage of triode Q4, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the colelctor electrode of triode Q2, the diode D2 of the extremely external-4V voltage of P forms, the end of oppisite phase of described power amplifier P1 is connected with the in-phase end of power amplifier P2, and its in-phase end is connected with self-locking optical excitation circuit, the end of oppisite phase of power amplifier P2 is connected with the output of NAND gate IC6, the output of power amplifier P3 is then connected with the TD pin of driving chip M.
3. the mixed type raster data model system based on power amplification circuit and energizing circuit according to claim 2, it is characterized in that, described homophase AC signal amplifying circuit is by power amplifier P, one end is connected with the VCC pin of driving chip M, the resistance R7 that the other end is connected with the in-phase end of power amplifier P, one end is connected with the end of oppisite phase of power amplifier P, the resistance R6 that the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the in-phase end of power amplifier P, the polar capacitor C4 of negative pole external power supply forms, the output of described power amplifier P is connected with the INP pin of driving chip M.
4. the mixed type raster data model system based on power amplification circuit and energizing circuit according to claim 3, it is characterized in that, described self-locking optical excitation circuit is by nor gate IC1, nor gate IC2, nor gate IC3, the photocell CDS that one end is connected with the in-phase end of power amplifier P, the other end is connected with the output of power amplifier P4 after potentiometer R5, and the electric capacity C3 be serially connected between the electrode input end of nor gate IC3 and output forms; The electrode input end of described nor gate IC1 is connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The output of described nor gate IC2 then simultaneously the negative input of AND OR NOT gate IC3 be connected with the in-phase end of power amplifier P1, the output of the output of nor gate IC3 then power amplifier P is connected; The output of described nor gate IC2 is then connected with the end of oppisite phase of power amplifier P after resistance R6.
5. the mixed type raster data model system based on power amplification circuit and energizing circuit according to claim 4, it is characterized in that, described boostrap circuit is by FET MOS, one end is connected with the source electrode of FET MOS, the resistance R4 that the other end is connected with the in-phase end of power amplifier P4, negative pole is connected with the grid of FET MOS, the polar capacitor C1 that positive pole is connected with the drain electrode of FET MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, positive pole is connected with the positive pole of polar capacitor C1, the polar capacitor C2 that the negative input of negative pole AND OR NOT gate IC2 is connected, and one end is connected with the positive pole of polar capacitor C2, the resistance R3 of other end ground connection forms, the drain electrode of described FET MOS is connected with the tie point of resistance R7 with photocell CDS.
6. the mixed type raster data model system based on power amplification circuit and energizing circuit according to any one of Claims 1 to 5, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C5 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R8 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, colelctor electrode is ground connection after electric capacity C6 and electric capacity C7 in turn, and the transistor Q1 of grounded emitter forms, the Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, ground connection after its non-same polarity is then connected with the emitter stage of transistor Q1, meanwhile, the emitter stage of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
7. the mixed type raster data model system based on power amplification circuit and energizing circuit according to claim 6, it is characterized in that, described driving chip M is LTC4440A integrated chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420717055.XU CN204305403U (en) | 2014-11-25 | 2014-11-25 | Based on the mixed type raster data model system of power amplification circuit and energizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420717055.XU CN204305403U (en) | 2014-11-25 | 2014-11-25 | Based on the mixed type raster data model system of power amplification circuit and energizing circuit |
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| Publication Number | Publication Date |
|---|---|
| CN204305403U true CN204305403U (en) | 2015-04-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420717055.XU Expired - Fee Related CN204305403U (en) | 2014-11-25 | 2014-11-25 | Based on the mixed type raster data model system of power amplification circuit and energizing circuit |
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| Country | Link |
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| CN (1) | CN204305403U (en) |
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2014
- 2014-11-25 CN CN201420717055.XU patent/CN204305403U/en not_active Expired - Fee Related
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