CN104394629A - Novel gate drive system - Google Patents
Novel gate drive system Download PDFInfo
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- CN104394629A CN104394629A CN201410687508.3A CN201410687508A CN104394629A CN 104394629 A CN104394629 A CN 104394629A CN 201410687508 A CN201410687508 A CN 201410687508A CN 104394629 A CN104394629 A CN 104394629A
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- driving chip
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a novel gate drive system. The novel gate drive system is mainly composed of a drive chip M, a drive circuit connected with the drive chip M, and a boot-strap circuit connected with the drive chip M; the boot-strap circuit is composed of a field-effect tube MOS, a resistor R5, a polar capacitor C6 and a polar capacitor C1, wherein one end of the resistor R5 is connected with the source electrode of the field-effect tube MOS while the other end is connected with the ground, the anode of the polar capacitor C6 is connected with the source electrode of the field-effect tube MOS while the cathode is connected with the INP pin of the drive chip M, and the cathode of the polar capacitor C1 is connected with the grid electrode of the field-effect tube MOS while the anode is connected with the drain electrode of the field-effect tube MOS after passing a resistor R1. The novel gate drive system is very simple in structure and very convenient to manufacture and use. The starting time of the novel gate drive system is only 1/4 of the starting time of a traditional gate drive circuit, and the starting time is very short.
Description
Technical field
The present invention relates to a kind of LED drive circuit, specifically refer to a kind of novel grid drive system.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Summary of the invention
The object of the invention is to the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit, a kind of reasonable in design is provided, can effectively reduce energy consumption and current noise, obviously shorten the novel grid drive system of one of start-up time.
Object of the present invention is achieved through the following technical solutions: a kind of novel grid drive system, primarily of driving chip M, and the drive circuit be connected with driving chip M, and the boostrap circuit be connected with driving chip M forms, described boostrap circuit is by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R5 of other end ground connection, positive pole is connected with the source electrode of field effect transistor MOS, the polar capacitor C6 that negative pole is connected with the INP pin of driving chip M, negative pole is connected with the grid of field effect transistor MOS, the polar capacitor C1 that positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, positive pole is connected with the positive pole of polar capacitor C1, the polar capacitor C5 that negative pole is connected with the source electrode of field effect transistor MOS, and one end is connected with the positive pole of polar capacitor C5, the resistance R4 of other end ground connection forms, the drain electrode of described field effect transistor MOS is also connected with the VCC pin of driving chip M.Meanwhile, between the TD pin and drive circuit of driving chip M, beam excitation formula logic amplifying circuit is also serially connected with, described beam excitation formula logic amplifying circuit is primarily of power amplifier P1, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C7 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C7, the resistance R6 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R6, the polar capacitor C9 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R7 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R8 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC1, the resistance R9 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C8 that negative pole is connected with the negative input of NAND gate IC3, and one end is connected with the positive pole of polar capacitor C9, the resistance R10 that the other end is connected with the negative input of NAND gate IC2 forms, the electrode input end of described NAND gate IC1 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC2, the electrode input end of NAND gate IC3 is connected with the output of power amplifier P1, and its output is connected with drive circuit, the electrode input end of power amplifier P1 is connected with the TD pin of driving chip M.
Further, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C2 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R3 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode forms through electric capacity C3 ground connection and transistor Q1 that emitter is connected with the output of NAND gate IC3 after electric capacity C4 in turn; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
For guaranteeing result of use of the present invention, described driving chip M is preferentially realized by LTC4440A integrated chip.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) overall structure of the present invention is very simple, and it makes and very easy to use.
(2) be only 1/4 of conventional gate drive circuit start-up time start-up time of the present invention, its start-up time is extremely short.
(3) the present invention adopts boostrap circuit to provide control signal for driving chip, therefore has very high input impedance, can guarantee the stable performance of whole circuit.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is primarily of driving chip M, the drive circuit be connected with driving chip M, and the boostrap circuit be connected with driving chip M, and the beam excitation formula logic amplifying circuit be serially connected between the TD pin of driving chip M and drive circuit forms.
Described boostrap circuit is made up of field effect transistor MOS, polar capacitor C1, polar capacitor C5, polar capacitor C6, resistance R1, resistance R2, resistance R4 and resistance R5.During connection, one end of resistance R5 is connected with the source electrode of field effect transistor MOS, its other end ground connection; The positive pole of polar capacitor C6 is connected with the source electrode of field effect transistor MOS, and its negative pole is connected with the INP pin of driving chip M; The negative pole of polar capacitor C1 is connected with the grid of field effect transistor MOS, and its positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, and resistance R2 is then in parallel with polar capacitor C1.
The positive pole of described polar capacitor C5 is connected with the positive pole of polar capacitor C1, and its negative pole is connected with the source electrode of field effect transistor MOS.And one end of resistance R4 is connected with the positive pole of polar capacitor C5, its other end ground connection.
For guaranteeing the normal work of field effect transistor MOS and driving chip M, therefore the drain electrode of this field effect transistor MOS is also connected with the VCC pin of driving chip M, and the VCC pin of this driving chip M needs the power supply of external+12V.
For guaranteeing result of use, the high-frequency N channel mosfet grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
Described beam excitation formula logic amplifying circuit is primarily of power amplifier P1, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C7 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C7, the resistance R6 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R6, the polar capacitor C9 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R7 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R8 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC1, the resistance R9 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C8 that negative pole is connected with the negative input of NAND gate IC3, and one end is connected with the positive pole of polar capacitor C9, the resistance R10 that the other end is connected with the negative input of NAND gate IC2 forms.
Meanwhile, the electrode input end of this NAND gate IC1 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC2; The electrode input end of NAND gate IC3 is connected with the output of power amplifier P1, and its output is connected with drive circuit; The electrode input end of power amplifier P1 is connected with the TD pin of driving chip M.
Described drive circuit is then made up of transformer T, diode D1, electric capacity C2, resistance R3, electric capacity C3, electric capacity C4 and transistor Q1.During connection, the P pole of diode D1 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C2 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.For guaranteeing the normal operation of driving chip M, its VCC holds the voltage needing external+12V.
Resistance R3 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q1 is then connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C3 and electric capacity C4 in turn, and its emitter is then connected with the output of NAND gate IC3.Meanwhile, the collector electrode of this transistor Q1 also needs the direct voltage of external+6V, to guarantee that transistor Q1 has enough bias voltages to drive himself conducting.
For guaranteeing result of use, described electric capacity C2, electric capacity C3 and electric capacity C4 all adopt patch capacitor to realize.Described transformer T exports to outside field effect transistor after being used for that+the 6V of outside direct voltage is carried out transformation process.
The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1.Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present invention.According to the situation of reality, user can only select any one or several port of these four outputs to use.
As mentioned above, just the present invention can well be realized.
Claims (3)
1. a novel grid drive system, primarily of driving chip M, the drive circuit be connected with driving chip M, and the boostrap circuit be connected with driving chip M forms, described boostrap circuit is by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R5 of other end ground connection, positive pole is connected with the source electrode of field effect transistor MOS, the polar capacitor C6 that negative pole is connected with the INP pin of driving chip M, negative pole is connected with the grid of field effect transistor MOS, the polar capacitor C1 that positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, positive pole is connected with the positive pole of polar capacitor C1, the polar capacitor C5 that negative pole is connected with the source electrode of field effect transistor MOS, and one end is connected with the positive pole of polar capacitor C5, the resistance R4 of other end ground connection forms, the drain electrode of described field effect transistor MOS is also connected with the VCC pin of driving chip M, it is characterized in that, is also serially connected with beam excitation formula logic amplifying circuit between the TD pin and drive circuit of driving chip M, described beam excitation formula logic amplifying circuit is primarily of power amplifier P1, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C7 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C7, the resistance R6 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R6, the polar capacitor C9 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R7 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R8 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC1, the resistance R9 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C8 that negative pole is connected with the negative input of NAND gate IC3, and one end is connected with the positive pole of polar capacitor C9, the resistance R10 that the other end is connected with the negative input of NAND gate IC2 forms, the electrode input end of described NAND gate IC1 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC2, the electrode input end of NAND gate IC3 is connected with the output of power amplifier P1, and its output is connected with drive circuit, the electrode input end of power amplifier P1 is connected with the TD pin of driving chip M.
2. the novel grid drive system of one according to claim 1, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C2 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R3 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode forms through electric capacity C3 ground connection and transistor Q1 that emitter is connected with the output of NAND gate IC3 after electric capacity C4 in turn; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C4 with electric capacity C3, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
3. the novel grid drive system of one according to claim 2, is characterized in that, described driving chip M is LTC4440A integrated chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410687508.3A CN104394629A (en) | 2014-11-25 | 2014-11-25 | Novel gate drive system |
| CN201510307276.9A CN104853512A (en) | 2014-11-25 | 2015-06-06 | Novel grid driving system based on gate driving |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410687508.3A CN104394629A (en) | 2014-11-25 | 2014-11-25 | Novel gate drive system |
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| CN104394629A true CN104394629A (en) | 2015-03-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410687508.3A Pending CN104394629A (en) | 2014-11-25 | 2014-11-25 | Novel gate drive system |
| CN201510307276.9A Pending CN104853512A (en) | 2014-11-25 | 2015-06-06 | Novel grid driving system based on gate driving |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510307276.9A Pending CN104853512A (en) | 2014-11-25 | 2015-06-06 | Novel grid driving system based on gate driving |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104853512A (en) * | 2014-11-25 | 2015-08-19 | 成都冠深科技有限公司 | Novel grid driving system based on gate driving |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101868094B (en) * | 2010-06-22 | 2014-02-12 | 海洋王照明科技股份有限公司 | LED driving circuit and LED lamp |
| CN101959351A (en) * | 2010-10-15 | 2011-01-26 | 上海小糸车灯有限公司 | P-MOS tube driving circuit and driving method thereof |
| CN202094794U (en) * | 2011-05-18 | 2011-12-28 | 南京博兰得电子科技有限公司 | Bootstrap driving and controlling circuit of gate pole |
| CN103917004A (en) * | 2012-12-31 | 2014-07-09 | 杭州展顺科技有限公司 | Three-terminal LED and drive circuit thereof |
| CN104394629A (en) * | 2014-11-25 | 2015-03-04 | 成都创图科技有限公司 | Novel gate drive system |
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2014
- 2014-11-25 CN CN201410687508.3A patent/CN104394629A/en active Pending
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- 2015-06-06 CN CN201510307276.9A patent/CN104853512A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104853512A (en) * | 2014-11-25 | 2015-08-19 | 成都冠深科技有限公司 | Novel grid driving system based on gate driving |
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| CN104853512A (en) | 2015-08-19 |
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Application publication date: 20150304 |