CN204304599U - A kind of power path management circuit - Google Patents
A kind of power path management circuit Download PDFInfo
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- CN204304599U CN204304599U CN201420836608.3U CN201420836608U CN204304599U CN 204304599 U CN204304599 U CN 204304599U CN 201420836608 U CN201420836608 U CN 201420836608U CN 204304599 U CN204304599 U CN 204304599U
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Abstract
The utility model discloses a kind of power path management circuit, at least comprise the first power switch circuit be connected between the first power supply and system power supply output, and the second source on-off circuit be connected between second source and system power supply output, the output of described second source on-off circuit is wherein connected with the control end of described first power switch circuit on a road, an other road is connected with described system power supply output, described power path management circuit also comprises second source over-voltage detection circuit, the input of described second source over-voltage detection circuit is connected with described second source, the output of described second source over-voltage detection circuit is connected with the control end of described second source on-off circuit.Power path management circuit of the present utility model, by adopting discrete electronic device to build circuit, can carry out path management by the first power supply and second source according to certain priority, is detected eliminate safe hidden trouble by overvoltage.
Description
Technical field
The utility model relates to a kind of power circuit, specifically, relates to a kind of power path management circuit.
Background technology
Electronic equipment operationally, in order to reach the longer working time, or in order to various working environment can be applicable to, the power pack of usual electronic equipment, except design becomes the lithium battery that can use and carry in electronic equipment, also by outside USB port, or special external adapter etc. is powered, have at least three-way power like this can power, and three-way power has certain power supply priority level, when to access two-way or two-way with power source simultaneously, the problem that power supply switches will be there is.
The normal mode adopting switch socket is switched for three road input powers, the interface connecing outside battery at equipment establishes a mechanical contact-type switch, when outside battery plug inserts apparatus socket, this switch can be touched, the contact of this switch connects internal battery, thus reaching the effect of breaking inner battery, the priority achieving power supply switches.This mode is when external cell exhausts, and the automatic switchover that can not realize internal cell is powered, and is not real three road automatic switch-over circuits.
Another three road input power switching mode, by arranging multiple switch element, each switch element has preset priority different from, all be connected with external control device in each switch element, for receiving the control signal from external control device, with the break-make of gauge tap unit, multiple power supply and switch element one_to_one corresponding, and then the automatic switchover realized three road input powers, but, this switching mode is transmitted control signal by external control device and carries out control realization, need the control pin taking external control device, when pin has in limited time, cannot realize switching and control, or need to increase device cost, the external control device with abundant control pin is selected to realize, and, the reliability controlled places one's entire reliance upon the running status of control device, when control device crashes or program enters endless loop, the pin of control device can be caused to export single level, when institute's switch element is open mode, preferred sequence is caused to be lost, cannot power according to correct mode.
Summary of the invention
The utility model can not realize the path managements such as automatic switchover to solve existing multi input power supply switch circuit, or switch and need take control device pin and switch insecure technical problem, propose a kind of power path management circuit, can solve the problem.
In order to solve the problems of the technologies described above, the utility model is achieved by the following technical solutions:
A kind of power path management circuit, at least comprise the first power switch circuit be connected between the first power supply and system power supply output, and the second source on-off circuit be connected between second source and system power supply output, the output of described second source on-off circuit is wherein connected with the control end of described first power switch circuit on a road, an other road is connected with described system power supply output, described power path management circuit also comprises second source over-voltage detection circuit, the input of described second source over-voltage detection circuit is connected with described second source, the output of described second source over-voltage detection circuit is connected with the control end of described second source on-off circuit, described second source over-voltage detection circuit produces the control signal for controlling second source on-off circuit break-make according to the overvoltage condition of second source, and be sent to second source on-off circuit.
Further, described power path management circuit also comprises the 3rd power switch circuit be connected between the 3rd power supply and system power supply output, 3rd power supply over-voltage detection circuit, and for controlling the ON-OFF control circuit of described 3rd power switch circuit break-make, the input of described 3rd power supply over-voltage detection circuit is connected with described 3rd power supply, the described output of the 3rd power supply over-voltage detection circuit is connected with one of them input of described ON-OFF control circuit, the another one input of described ON-OFF control circuit is connected with the output of described second source over-voltage detection circuit, the output of described ON-OFF control circuit is connected with the control end of described 3rd power switch circuit, the input of described 3rd power switch circuit is connected with the 3rd power supply, the output of described 3rd power switch circuit is wherein connected with the control end of described first power switch circuit on a road, an other road is connected with described system power supply output, described ON-OFF control circuit receives the output signal of second source over-voltage detection circuit, the insert state of the output signal of the 3rd power supply over-voltage detection circuit and second source and the 3rd power supply, export the control signal for controlling the 3rd power switch circuit break-make, and be sent to the 3rd power switch circuit.
Further, described first on-off circuit comprises the 3rd PMOS, and the drain electrode of described 3rd PMOS is connected with the first power supply, and source electrode is connected with system power supply output, grid is wherein leaded up to the 5th resistance and is connected earth terminal, and an other road is connected with the output of second source on-off circuit.
Further, described second source on-off circuit comprises the 4th NMOS tube and the 5th PMOS, the grid of described 4th NMOS tube is leaded up to the 9th resistance and is connected earth terminal, the 8th resistance of leading up in addition is connected with second source, the source electrode of described 4th NMOS tube connects earth terminal by the 11 resistance, the drain electrode of described 4th NMOS tube is leaded up to the tenth resistance and is connected with second source, an other road is connected with the grid of described 5th PMOS, the source electrode of described 5th PMOS is connected with second source, the drain electrode of described 5th PMOS is leaded up to the 4th diode and is connected with system power supply output, the 9th diode of leading up in addition is connected with the grid of described 3rd PMOS.
Further, described second source over-voltage detection circuit comprises the first comparator and the first same OR circuit, the normal phase input end of described first comparator is connected with described second source by the first bleeder circuit, the inverting input of described first comparator is connected with described second source by the first mu balanced circuit, the output of described first comparator is connected with the first input end of OR circuit with described first, described first is connected with for detecting the second source test side exporting second source insert state with the second input of OR circuit, described first is connected with the source electrode of described 4th NMOS tube with the output of OR circuit.
Further, described first bleeder circuit comprises the 13 resistance and the 14 resistance that are in series, the normal phase input end of described first comparator is connected between described 13 resistance and the 14 resistance, described first mu balanced circuit comprises the 4th resistance and the first Zener diode, described 4th resistance one end is connected with second source, one end is connected with the negative pole of described first Zener diode in addition, the positive pole of described first Zener diode connects earth terminal, the inverting input of described first comparator is connected with the negative pole of described first Zener diode, described second source test side is connected between described 13 resistance and the 14 resistance or with second source testing circuit and is connected, described second source testing circuit one end is connected with second source, one end is held with ground and is connected in addition, comprise the 6th resistance and the 7th resistance that are in series, described second source test side is connected between described 6th resistance and the 7th resistance.
Further, described 3rd power switch circuit comprises the second NMOS tube and the first PMOS, the grid of described second NMOS tube is leaded up to the 3rd resistance and is connected earth terminal, first resistance of leading up in addition is connected with the 3rd power supply, the source electrode of described second NMOS tube connects earth terminal by the 12 resistance, the drain electrode of described second NMOS tube is leaded up to the second resistance and is connected with the 3rd power supply, an other road is connected with the grid of described first PMOS, the source electrode of described first PMOS is connected with the 3rd power supply, the drain electrode of described first PMOS is leaded up to the first diode and is connected with system power supply output, the 8th diode of leading up in addition is connected with the grid of described 3rd PMOS.
Further, described 3rd power supply over-voltage detection circuit comprises the second comparator, second same OR circuit, the normal phase input end of described second comparator is connected with described 3rd power supply by the second bleeder circuit, the inverting input of described second comparator is connected with described 3rd power supply by the second mu balanced circuit, the output of described second comparator is connected with the first input end of OR circuit with described second, described second is connected with the 3rd power detecting end for detecting output the 3rd power supply insert state with the second input of OR circuit, described ON-OFF control circuit comprises the 3rd same OR circuit, first not circuit, and first OR circuit, described 3rd is connected with the output of OR circuit with described second with the first input end of OR circuit, described 3rd is connected with the output of OR circuit with described first with the second input of OR circuit, the input of described first not circuit is connected with the output of OR circuit with described first, the first input end of described first OR circuit is connected with the output of OR circuit with the described 3rd, second input of described first OR circuit is connected with the output of described first not circuit, the output of described first OR circuit is connected with the control end of described 3rd power switch circuit.
Further, described second bleeder circuit comprises the 15 resistance and the 16 resistance that are in series, the normal phase input end of described second comparator is connected between described 15 resistance and the 16 resistance, described second mu balanced circuit comprises the 17 resistance and the second Zener diode, described 17 resistance one end is connected with the 3rd power supply, one end is connected with the negative pole of described second Zener diode in addition, the positive pole of described second Zener diode connects earth terminal, the inverting input of described second comparator is connected with the negative pole of described second Zener diode, described 3rd power detecting end is connected between described 15 resistance and the 16 resistance or with the 3rd power sense circuit and is connected.
Further, described 3rd power sense circuit one end is connected with the 3rd power supply, and one end is held with ground and is connected in addition, and comprise the 18 resistance and the 19 resistance that are in series, described 3rd power detecting end is connected between described 18 resistance and the 19 resistance.
Compared with prior art, advantage of the present utility model and good effect are: power path management circuit of the present utility model, circuit is built by adopting discrete electronic device, first power supply and second source can be carried out path management according to certain priority, when two power supplys insert simultaneously, automatically switch to the Power supply that priority is high, without the need to connecting external control device, do not take the pin of external control device, when the power supply overvoltage that priority is high, when there is potential safety hazard, detected by overvoltage, automatically switch to the Power supply that priority is low, guarantee system power supply safety, and correctly can select according to priority level the running status not relying on control device, completely by logic circuit control realization, reliability is high, first power supply is generally lithium battery, priority is low, second source is externally fed power supply, priority is high, by the low priority that lithium battery is arranged, preferential employing external power source, saving battery electric quantity can also be reached, the object of extension device internal cell working time.
After reading the detailed description of the utility model embodiment by reference to the accompanying drawings, other features of the present utility model and advantage will become clearly.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of embodiment block diagram of the power path management circuit that the utility model proposes;
Fig. 2 is another the embodiment block diagram of the power path management circuit that the utility model proposes;
Fig. 3 is a kind of embodiment circuit theory diagrams of the power path management circuit that the utility model proposes;
Fig. 4 is the second source over-voltage detection circuit of power path management circuit in Fig. 3;
Fig. 5 is the ON-OFF control circuit of power path management circuit in Fig. 3.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment one, the present embodiment proposes a kind of power path management circuit, as shown in Figure 1, this power path management circuit at least comprises the first power switch circuit be connected between the first power supply V1 and system power supply output POWER_OUT, and the second source on-off circuit be connected between second source V2 and system power supply output POWER_OUT, the output 2 of described second source on-off circuit is wherein connected with the control end 3 of described first power switch circuit on a road, an other road is connected with described system power supply output POWER_OUT, the power path management circuit of the present embodiment also comprises second source over-voltage detection circuit, the input 1 of described second source over-voltage detection circuit is connected with described second source V2, the output 2 of second source over-voltage detection circuit is connected with the control end 3 of described second source on-off circuit, described second source over-voltage detection circuit produces the control signal for controlling second source on-off circuit break-make according to the overvoltage condition of second source, and be sent to second source on-off circuit.In the present embodiment, the priority of second source is higher than the priority of the first power supply, the on off operating mode of the first power switch circuit is subject to the control of the output signal of second source on-off circuit, also be, when the first power supply and second source access simultaneously, the conducting of second source on-off circuit, second source exports supply voltage by system power supply output, significant level signal is sent to the control end of the first power switch circuit by second source on-off circuit simultaneously, disconnect to control the first power switch circuit, and then control the first power supply to the supply access of system power supply output and disconnect, system is only powered by second source, second source over-voltage detection circuit detects second source and whether there is overpressure situation in second source power supply process, when overvoltage, produce control signal to turn off to control second source on-off circuit, second source on-off circuit output low level simultaneously, first power switch circuit conducting, and then transfer to by the first lower Power supply of priority, the power path management circuit of the present embodiment, circuit is built by adopting discrete electronic device, first power supply and second source can be carried out path management according to certain priority, when two power supplys insert simultaneously, automatically switch to the Power supply that priority is high, without the need to connecting external control device, do not take the pin of external control device, when the power supply overvoltage that priority is high, when there is potential safety hazard, detected by overvoltage, automatically switch to the Power supply that priority is low, guarantee system power supply safety, and correctly can select according to priority level the running status not relying on control device, completely by logic circuit control realization, reliability is high, first power supply is generally the built-in rechargeable battery such as lithium battery or button cell, priority is low, second source is externally fed power supply, priority is high, by the low priority that lithium battery is arranged, preferential employing external power source, saving battery electric quantity can also be reached, the object of extension device internal cell working time.
Powered by USB port because current externally fed power supply generally comprises, or special external adapter (AC-DC adapter or DC-DC adapter) etc. is powered, in order to improve the universality of this power source path management system, can be applicable to manage at least above-mentioned two kinds of external power sources simultaneously, as shown in Figure 2, the power path management circuit of the present embodiment also comprises the 3rd power switch circuit be connected between the 3rd power supply V3 and system power supply output POWER_OUT, 3rd power supply over-voltage detection circuit, and for controlling the ON-OFF control circuit of described 3rd power switch circuit break-make, the input 1 of described 3rd power supply over-voltage detection circuit is connected with described 3rd power supply V3, the output 2 of the 3rd power supply over-voltage detection circuit is connected with one of them input 11 of described ON-OFF control circuit, the another one input 12 of described ON-OFF control circuit is connected with the output 2 of described second source over-voltage detection circuit, the output 2 of described ON-OFF control circuit is connected with the control end 3 of described 3rd power switch circuit, the input 1 of described 3rd power switch circuit is connected with the 3rd power supply V3, the output 2 of the 3rd power switch circuit is wherein connected with the control end 3 of described first power switch circuit on a road, an other road is connected with described system power supply output POWER_OUT, described ON-OFF control circuit receives the output signal of second source over-voltage detection circuit, the insert state of the output signal of the 3rd power supply over-voltage detection circuit and second source V2 and the 3rd power supply V3, described ON-OFF control circuit is according to the overvoltage condition of second source V2, the overvoltage condition of the 3rd power supply V3, and the priority of second source V2 and the 3rd power supply V3, produce the control signal for controlling the 3rd power switch circuit break-make, and be sent to the 3rd power switch circuit.In the present embodiment, the conducting state of the 3rd power switch circuit is indirectly by the control of second source over-voltage detection circuit, make the power supply priority of the 3rd power supply V3 lower than second source V2,3rd power switch circuit controls the conducting state of the first power switch circuit simultaneously, makes the power supply priority of the 3rd power supply V3 higher than the first power supply.When second source V2, the 3rd power supply V3 insert simultaneously, described ON-OFF control circuit receives the overvoltage detection signal of second source over-voltage detection circuit and the 3rd power supply over-voltage detection circuit, and controls the 3rd power switch circuit.When second source V2 overvoltage, the 3rd power supply V3 not overvoltage, ON-OFF control circuit produces the control signal of control the 3rd power switch circuit conducting, control the 3rd power switch circuit conducting, and when second source do not insert, the 3rd power plug is fashionable, ON-OFF control circuit produces the control signal of control the 3rd power switch circuit conducting equally, control the 3rd power switch circuit conducting, powered by the 3rd power supply V3, the 3rd power switch circuit controls the first power switch circuit simultaneously and turns off.Described ON-OFF control circuit can adopt logic gates to realize.The power path management circuit of the present embodiment, can carry out path management to three input powers according to priority by hardware logic electric circuit, and can detect the overpressure conditions of two external power sources, automatically switch, and ensures power supply safety.In the present embodiment, the first power supply V1 is built-in rechargeable battery, and second source V2 can be adaptor power supplies, 3rd power supply V3 is USB power source, or second source V2 can be USB power source, and the 3rd power supply V3 is adaptor power supplies, can arrange flexibly according to actual needs.
Embodiment two, this gives a kind of preferred electrical architecture realizing power path management circuit in embodiment one, in the present embodiment, as shown in Figure 3, described first on-off circuit comprises the 3rd PMOS Q3, drain electrode and the first power supply VCC_BAT(i.e. first power supply V1 of described 3rd PMOS Q3) be connected, source electrode is connected with system power supply output POWER_OUT, grid wherein leads up to the 5th resistance R5 ground connection, an other road is connected with the output of second source on-off circuit, wherein, the first power supply VCC_BAT is lithium battery.The operation principle of the present embodiment circuit is: the first on-off circuit accepts the control of second source on-off circuit, as second source EXT_PWR(i.e. the first power supply V2) when powering, second source on-off circuit exports high level to the grid of the 3rd PMOS Q3, therefore the 3rd PMOS Q3 cut-off, first power supply VCC_BAT does not power, and, due to the 3rd PMOS Q3 cut-off, the high level that can also prevent second source EXT_PWR from exporting pours in down a chimney in the first power supply VCC_BAT, when second source EXT_PWR does not insert, second source on-off circuit output low level, 3rd PMOS Q3 conducting, therefore the first power supply VCC_BAT and system power supply output POWER_OUT conducting, powered by the first power supply VCC_BAT.
In the present embodiment, described second source on-off circuit comprises the 4th NMOS tube Q4 and the 5th PMOS Q5, the grid of described 4th NMOS tube Q4 is leaded up to the 9th resistance R9 and is connected earth terminal, the 8th resistance R8 of leading up in addition is connected with second source EXT_PWR, and the 9th resistance R9 and the 8th resistance R8 is connected on (namely the grid of the 4th NMOS tube Q4 is connected on the series connection node of the 9th resistance R9 and the 8th resistance R8) between second source EXT_PWR and ground, the source electrode of described 4th NMOS tube Q4 connects earth terminal by the 11 resistance R11, the drain electrode of described 4th NMOS tube Q4 is leaded up to the tenth resistance R10 and is connected with second source EXT_PWR, an other road is connected with the grid of described 5th PMOS Q5, the source electrode of described 5th PMOS Q5 is connected with second source EXT_PWR, the drain electrode of described 5th PMOS Q5 is leaded up to the 4th diode D4 and is connected with system power supply output POWER_OUT, the 9th diode D9 of leading up in addition is connected with the grid of described 3rd PMOS Q3.When second source EXT_PWR inserts, through the dividing potential drop of the 8th resistance R8 and the 9th resistance R9, the grid input high level of the 4th NMOS tube Q4, therefore the 4th NMOS tube Q4 conducting, its drain electrode level is dragged down, because its drain electrode is connected with the grid of the 5th PMOS Q5, therefore the 5th PMOS Q5 conducting, and then, the conducting of whole second source on-off circuit, powered by second source EXT_PWR, the drain electrode of the 5th PMOS Q5 is connected with the grid of described 3rd PMOS Q3 by the 9th diode D9, during due to the 5th PMOS Q5 conducting, its drain electrode is high level, therefore the 9th diode D9 conducting, by the dividing potential drop effect of the 5th resistance R5, the grid of the 3rd PMOS Q3 is high level, therefore the 3rd PMOS Q3 cut-off, first power supply VCC_BAT closes and exports, wherein, when 9th diode D9 and the 4th diode D4 is used for preventing from being powered by the first power supply VCC_BAT, electric current pours in down a chimney in the 5th PMOS Q5, play the effect of protection second source EXT_PWR.
As shown in Figure 4, described second source over-voltage detection circuit comprises the first comparator U1 and first with OR circuit U2, the normal phase input end of described first comparator U1 is connected with described second source EXT_PWR by the first bleeder circuit, the inverting input of described first comparator U1 is connected with described second source EXT_PWR by the first mu balanced circuit, the output of described first comparator U1 is connected with the first input end of OR circuit U2 with described first, described first is connected with for detecting the second source test side EXT_DET exporting second source insert state with second input of OR circuit U2, described first is connected with the source electrode of described 4th NMOS tube Q4 with the output of OR circuit U2.By the second source over-voltage detection circuit of this circuit structure form, the inverting input of the first comparator U1 inputs stable forward voltage, when second source EXT_PWR increases, the inverting input input voltage of the first comparator U1 is constant, and the first bleeder circuit be connected with normal phase input end to increase and dividing potential drop increases along with second source EXT_PWR voltage, when dividing potential drop is greater than the inverting input input voltage of the first comparator U1, first comparator U1 exports high level, otherwise, output low level.By arranging first with OR circuit U2, the second source that the second source overvoltage signal EXT_COMP export the first comparator U1 and second source test side export inserts testing result and carries out logical operation, export the control signal EXT_SEL for controlling second source on-off circuit conducting state, only have detect simultaneously second source insert and the first comparator U1 export high level time, just determine that second source EXT_PWR is overvoltage condition, prevent from only judging easily to occur misjudgment phenomenon with the first comparator U1.Wherein, first is as shown in table 1 with the input and output truth table of OR circuit U2:
| EXT_DET | EXT_COMP | EXT_SEL |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Table 1
In table 1, when control signal EXT_SEL is high level, closed by the 4th NMOS tube Q4, second source is not powered.
As a preferred embodiment, as shown in Figure 4, described first bleeder circuit comprises the 13 resistance R13 and the 14 resistance R14 that are in series, the normal phase input end of described first comparator U1 is connected between described 13 resistance R13 and the 14 resistance R14, described first mu balanced circuit comprises the 4th resistance R4 and the first Zener diode D5, described 4th resistance R4 one end is connected with second source EXT_PWR, one end is connected with the negative pole of described first Zener diode D5 in addition, the positive pole of described first Zener diode D5 connects earth terminal, the inverting input of described first comparator U1 is connected with the negative pole of described first Zener diode D5, described second source test side EXT_DET is connected between described 13 resistance R13 and the 14 resistance R14 or with second source testing circuit and is connected, when needs arrange second source testing circuit, described second source testing circuit one end is connected with second source, one end is held with ground and is connected in addition, comprise the 6th resistance R6 and the 7th resistance R7 that are in series, described second source test side is connected between described 6th resistance R6 and the 7th resistance R7.When really there being second source EXT_PWR to insert, second source test side input high level.
Embodiment three, this gives a kind of power management preferred circuit when including three power supplys, wherein, the interlock circuit of the first power supply and second source etc. can see shown in embodiment two, do not repeat at this, the operation principle of the interlock circuit of the 3rd power supply and the electric power management circuit of whole three power supplys is introduced in detail in the present embodiment, in the present embodiment, as shown in Figure 3, 3rd power switch circuit comprises the second NMOS tube Q2 and the first PMOS Q1, the grid of described second NMOS tube Q2 is leaded up to the 3rd resistance R3 and is connected earth terminal, first resistance R1 of leading up in addition is connected with the 3rd power supply VBUS, the source electrode of described second NMOS tube Q2 connects earth terminal by the 12 resistance R12, the drain electrode of described second NMOS tube Q2 is leaded up to the second resistance R2 and is connected with the 3rd power supply VBUS, an other road is connected with the grid of described first PMOS Q1, the source electrode of described first PMOS Q1 is connected with the 3rd power supply VBUS, the drain electrode of described first PMOS Q1 is leaded up to the first diode D1 and is connected with system power supply output POWER_OUT, the 8th diode D8 of leading up in addition is connected with the grid of described 3rd PMOS Q3.The output of ON-OFF control circuit is connected with the source electrode of the second NMOS tube Q2, by controlling the conducting state of the second NMOS tube Q2 and then realizing control the 3rd power switch circuit conducting state.Wherein, when the first diode D1 and the 8th diode D8 is used for preventing the 3rd power supply from not powering, foreign current pours in down a chimney to the first PMOS Q1, plays the effect of protection the 3rd power supply VBUS.
Described 3rd power supply over-voltage detection circuit comprises the second comparator U3, second with OR circuit U4, the normal phase input end of described second comparator U3 is connected with described 3rd power supply VBUS by the second bleeder circuit, the inverting input of described second comparator U3 is connected with described 3rd power supply VBUS by the second mu balanced circuit, the output of described second comparator U3 is connected with the first input end of OR circuit U4 with described second, described second is connected with the 3rd power detecting end VBUS_DET for detecting output the 3rd power supply insert state with second input of OR circuit U4, as shown in Figure 5, described ON-OFF control circuit comprises the 3rd with OR circuit U5, first not circuit U6, and the first OR circuit U7, described 3rd is connected with the output of OR circuit U4 with described second with the first input end of OR circuit U5, second exports the 3rd power-gating signals USB_SEL with OR circuit U4 to it, described 3rd is connected with the output of OR circuit U2 with described first with second input of OR circuit U5, the input of described first not circuit U6 is connected with the output of OR circuit U2 with described first, the first input end of described first OR circuit U7 is connected with the output of OR circuit U5 with the described 3rd, second input of described first OR circuit U7 is connected with the output of described first not circuit U6, the output of described first OR circuit U7 is connected with the control end of described 3rd power switch circuit.By the 3rd power supply over-voltage detection circuit of this circuit structure form, the inverting input of the second comparator U3 inputs stable forward voltage, when the 3rd power supply VUSB increases, the inverting input input voltage of the second comparator U3 is constant, and the second bleeder circuit be connected with normal phase input end to increase and dividing potential drop increases along with the 3rd power supply VUSB voltage, when dividing potential drop is greater than the inverting input input voltage of the second comparator U3, the second comparator U3 exports high level, otherwise, output low level.By arranging second with OR circuit U4, the 3rd power supply that the 3rd power supply overvoltage signal USB_COMP export the second comparator U3 and the 3rd power detecting end export inserts testing result USB_DET and carries out logical operation, export the 3rd power-gating signals USB_SEL, if directly utilize the words that the 3rd power-gating signals USB_SEL controls, cannot manage the priority of second source EXT_PWR and the 3rd power supply VBUS, therefore, also need further the 3rd power-gating signals USB_SEL and second source overvoltage signal EXT_COM to be carried out logical operation further, export the 3rd power switch signal SUB_SWITCH, for controlling the conducting state of the 3rd power switch circuit, can manage the priority of second source and the 3rd power supply, wherein, second is as shown in table 2 with the logical calculated truth table of OR circuit U4:
| USB_DET | USB_COMP | USB_SEL |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Table 2
The logical calculated truth table of the first OR circuit U7 is as shown in table 3:
| EXT_SEL | USB_SEL | USB_SWITCH |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 1 | 1 |
| 0 | 0 | 1 |
Table 3
The output of described first OR circuit U7 is connected with the control end of described 3rd power switch circuit, also be namely connected with the source electrode of the second NMOS tube Q2, when USB_SWITCH is low level, second NMOS tube Q2 conducting, also i.e. the 3rd power switch circuit conducting, the 3rd power supply VBUS powers, when USB_SWITCH is low level, the physical significance of state of a control is: EXT_SEL=1, USB_SEL=0: when the non-gating of second source, and during the 3rd power supply gating, by the 3rd Power supply.
In the present embodiment, described second bleeder circuit comprises the 15 resistance R15 and the 16 resistance R16 that are in series, the normal phase input end of described second comparator U3 is connected between described 15 resistance R15 and the 16 resistance R16, described second mu balanced circuit comprises the 17 resistance R17 and the second Zener diode D10, described 17 resistance R17 one end is connected with the 3rd power supply VBUS, one end is connected with the negative pole of described second Zener diode D10 in addition, the positive pole of described second Zener diode D10 connects earth terminal, the inverting input of described second comparator U3 is connected with the negative pole of described second Zener diode D10, described 3rd power detecting end is connected between described 15 resistance R15 and the 16 resistance R16 or with the 3rd power sense circuit and is connected.The second bleeder circuit principle of this version is identical with the first bleeder circuit principle, does not repeat at this.
When needs arrange the 3rd power sense circuit, described 3rd power sense circuit one end is connected with the 3rd power supply VBUS, one end is held with ground and is connected in addition, comprise the 18 resistance R18 and the 19 resistance R19 that are in series, described 3rd power detecting end is connected between described 18 resistance R18 and the 19 resistance R19.When really there being the 3rd power supply VBUS to insert, the 3rd power detecting end input high level.
It should be noted that; above are only one of them preferred embodiment of this power path management circuit; be not limited to above-mentioned citing; the electronic device of other versions can also be adopted to substitute realize; such as; first PMOS, the 3rd PMOS or the 5th PMOS can adopt a PNP type triode to substitute and realize; second NMOS tube or the 4th NMOS tube can substitute by a NPN type triode and realize; or the combination of any one alternative form above-mentioned, all belongs to protection domain of the present utility model.
Certainly; above-mentioned explanation is not to restriction of the present utility model; the utility model is also not limited in above-mentioned citing, the change that those skilled in the art make in essential scope of the present utility model, remodeling, interpolation or replacement, also should belong to protection domain of the present utility model.
Claims (10)
1. a power path management circuit, it is characterized in that, at least comprise the first power switch circuit be connected between the first power supply and system power supply output, and the second source on-off circuit be connected between second source and system power supply output, the output of described second source on-off circuit is wherein connected with the control end of described first power switch circuit on a road, an other road is connected with described system power supply output, described power path management circuit also comprises second source over-voltage detection circuit, the input of described second source over-voltage detection circuit is connected with described second source, the output of described second source over-voltage detection circuit is connected with the control end of described second source on-off circuit, described second source over-voltage detection circuit produces the control signal for controlling second source on-off circuit break-make according to the overvoltage condition of second source, and be sent to second source on-off circuit.
2. power path management circuit according to claim 1, it is characterized in that, also comprise the 3rd power switch circuit be connected between the 3rd power supply and system power supply output, 3rd power supply over-voltage detection circuit, and for controlling the ON-OFF control circuit of described 3rd power switch circuit break-make, the input of described 3rd power supply over-voltage detection circuit is connected with described 3rd power supply, the described output of the 3rd power supply over-voltage detection circuit is connected with one of them input of described ON-OFF control circuit, the another one input of described ON-OFF control circuit is connected with the output of described second source over-voltage detection circuit, the input of described 3rd power switch circuit is connected with the 3rd power supply, the output of described 3rd power switch circuit is wherein connected with the control end of described first power switch circuit on a road, an other road is connected with described system power supply output, the output of described ON-OFF control circuit is connected with the control end of described 3rd power switch circuit, described ON-OFF control circuit receives the output signal of second source over-voltage detection circuit, the insert state of the output signal of the 3rd power supply over-voltage detection circuit and second source and the 3rd power supply, export the control signal for controlling the 3rd power switch circuit break-make, and be sent to the 3rd power switch circuit.
3. power path management circuit according to claim 2, it is characterized in that, described first on-off circuit comprises the 3rd PMOS, the drain electrode of described 3rd PMOS is connected with the first power supply, source electrode is connected with system power supply output, grid is wherein leaded up to the 5th resistance and is connected earth terminal, and an other road is connected with the output of second source on-off circuit.
4. power path management circuit according to claim 3, it is characterized in that, described second source on-off circuit comprises the 4th NMOS tube and the 5th PMOS, the grid of described 4th NMOS tube is leaded up to the 9th resistance and is connected earth terminal, the 8th resistance of leading up in addition is connected with second source, the source electrode of described 4th NMOS tube connects earth terminal by the 11 resistance, the drain electrode of described 4th NMOS tube is leaded up to the tenth resistance and is connected with second source, an other road is connected with the grid of described 5th PMOS, the source electrode of described 5th PMOS is connected with second source, the drain electrode of described 5th PMOS is leaded up to the 4th diode and is connected with system power supply output, the 9th diode of leading up in addition is connected with the grid of described 3rd PMOS.
5. power path management circuit according to claim 4, it is characterized in that, described second source over-voltage detection circuit comprises the first comparator and the first same OR circuit, the normal phase input end of described first comparator is connected with described second source by the first bleeder circuit, the inverting input of described first comparator is connected with described second source by the first mu balanced circuit, the output of described first comparator is connected with the first input end of OR circuit with described first, described first is connected with for detecting the second source test side exporting second source insert state with the second input of OR circuit, described first is connected with the source electrode of described 4th NMOS tube with the output of OR circuit.
6. power path management circuit according to claim 5, it is characterized in that, described first bleeder circuit comprises the 13 resistance and the 14 resistance that are in series, the normal phase input end of described first comparator is connected between described 13 resistance and the 14 resistance, described first mu balanced circuit comprises the 4th resistance and the first Zener diode, described 4th resistance one end is connected with second source, one end is connected with the negative pole of described first Zener diode in addition, the positive pole of described first Zener diode connects earth terminal, the inverting input of described first comparator is connected with the negative pole of described first Zener diode, described second source test side is connected between described 13 resistance and the 14 resistance or with second source testing circuit and is connected, described second source testing circuit one end is connected with second source, one end is held with ground and is connected in addition, comprise the 6th resistance and the 7th resistance that are in series, described second source test side is connected between described 6th resistance and the 7th resistance.
7. the power path management circuit according to any one of claim 3-6, it is characterized in that, described 3rd power switch circuit comprises the second NMOS tube and the first PMOS, the grid of described second NMOS tube is leaded up to the 3rd resistance and is connected earth terminal, first resistance of leading up in addition is connected with the 3rd power supply, the source electrode of described second NMOS tube connects earth terminal by the 12 resistance, the drain electrode of described second NMOS tube is leaded up to the second resistance and is connected with the 3rd power supply, an other road is connected with the grid of described first PMOS, the source electrode of described first PMOS is connected with the 3rd power supply, the drain electrode of described first PMOS is leaded up to the first diode and is connected with system power supply output, the 8th diode of leading up in addition is connected with the grid of described 3rd PMOS.
8. power path management circuit according to claim 5, it is characterized in that, described 3rd power supply over-voltage detection circuit comprises the second comparator, second same OR circuit, the normal phase input end of described second comparator is connected with described 3rd power supply by the second bleeder circuit, the inverting input of described second comparator is connected with described 3rd power supply by the second mu balanced circuit, the output of described second comparator is connected with the first input end of OR circuit with described second, described second is connected with the 3rd power detecting end for detecting output the 3rd power supply insert state with the second input of OR circuit, described ON-OFF control circuit comprises the 3rd same OR circuit, first not circuit, and first OR circuit, described 3rd is connected with the output of OR circuit with described second with the first input end of OR circuit, described 3rd is connected with the output of OR circuit with described first with the second input of OR circuit, the input of described first not circuit is connected with the output of OR circuit with described first, the first input end of described first OR circuit is connected with the output of OR circuit with the described 3rd, second input of described first OR circuit is connected with the output of described first not circuit, the output of described first OR circuit is connected with the control end of described 3rd power switch circuit.
9. power path management circuit according to claim 8, it is characterized in that, described second bleeder circuit comprises the 15 resistance and the 16 resistance that are in series, the normal phase input end of described second comparator is connected between described 15 resistance and the 16 resistance, described second mu balanced circuit comprises the 17 resistance and the second Zener diode, described 17 resistance one end is connected with the 3rd power supply, one end is connected with the negative pole of described second Zener diode in addition, the positive pole of described second Zener diode connects earth terminal, the inverting input of described second comparator is connected with the negative pole of described second Zener diode, described 3rd power detecting end is connected between described 15 resistance and the 16 resistance or with the 3rd power sense circuit and is connected.
10. power path management circuit according to claim 9, it is characterized in that, described 3rd power sense circuit one end is connected with the 3rd power supply, one end is held with ground and is connected in addition, comprise the 18 resistance and the 19 resistance that are in series, described 3rd power detecting end is connected between described 18 resistance and the 19 resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420836608.3U CN204304599U (en) | 2014-12-26 | 2014-12-26 | A kind of power path management circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420836608.3U CN204304599U (en) | 2014-12-26 | 2014-12-26 | A kind of power path management circuit |
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| Publication Number | Publication Date |
|---|---|
| CN204304599U true CN204304599U (en) | 2015-04-29 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420836608.3U Withdrawn - After Issue CN204304599U (en) | 2014-12-26 | 2014-12-26 | A kind of power path management circuit |
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| Country | Link |
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| CN (1) | CN204304599U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467167A (en) * | 2014-12-26 | 2015-03-25 | 青岛歌尔声学科技有限公司 | Power source path management circuit |
| CN104901413A (en) * | 2015-05-22 | 2015-09-09 | 成都前锋电子仪器有限责任公司 | Power supply control system used for intelligent gas meter |
| CN115223310A (en) * | 2022-06-30 | 2022-10-21 | 无锡睿勤科技有限公司 | OTG priority selection circuit and multichannel charging circuit |
-
2014
- 2014-12-26 CN CN201420836608.3U patent/CN204304599U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467167A (en) * | 2014-12-26 | 2015-03-25 | 青岛歌尔声学科技有限公司 | Power source path management circuit |
| CN104467167B (en) * | 2014-12-26 | 2016-10-05 | 青岛歌尔声学科技有限公司 | A kind of power path management circuit |
| CN104901413A (en) * | 2015-05-22 | 2015-09-09 | 成都前锋电子仪器有限责任公司 | Power supply control system used for intelligent gas meter |
| CN104901413B (en) * | 2015-05-22 | 2018-05-04 | 成都前锋电子仪器有限责任公司 | A kind of power control system for intelligent gas meter |
| CN115223310A (en) * | 2022-06-30 | 2022-10-21 | 无锡睿勤科技有限公司 | OTG priority selection circuit and multichannel charging circuit |
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