CN204067309U - The test structure that a kind of interlayer dielectric layer punctures - Google Patents
The test structure that a kind of interlayer dielectric layer punctures Download PDFInfo
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- CN204067309U CN204067309U CN201420508299.7U CN201420508299U CN204067309U CN 204067309 U CN204067309 U CN 204067309U CN 201420508299 U CN201420508299 U CN 201420508299U CN 204067309 U CN204067309 U CN 204067309U
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Abstract
The test structure that the utility model provides a kind of interlayer dielectric layer to puncture, at least comprise: be formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer and the second comb metal layer, and described first comb metal layer and the second comb metal layer mutually intersect and kept apart by dielectric layer; Being formed in dielectric layer and being in some of different layers grid arranged in parallel with described metal layer, one end of grid is electrically connected with the gate terminal of a transistor device respectively; The cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer all has coincide point; Described metal layer also comprises the snakelike metal level be inserted between described first comb metal layer and the second comb metal layer.Whether test structure of the present utility model can be monitored between metal level and metal level, between metal level and grid simultaneously and puncture, and can find the number of the location point puncturing generation.
Description
Technical field
The utility model relates to semiconductor test technical field, particularly relates to the test structure that a kind of interlayer dielectric layer punctures.
Background technology
Integrated circuit develops into device up to a million from the very few interconnect devices be manufactured in single silicon.The performance that custom integrated circuit provides and complexity are far beyond the initial imagination.In order to improve complexity and current densities (namely can be packaged in the quantity of the device in given chip area), minimum device feature size (also referred to as device " physical dimension ") is along with often becoming more and more less for integrated circuit.
Increase complexity and performance that current densities not only increases integrated circuit, also for consumer provides lower cost.An integrated circuit or chip manufacturing facility may spend several hundred million even multi-million dollar.Each manufacturing facility has certain wafer throughput, and each wafer has the integrated circuit of some.Therefore, by manufacturing less by each device of integrated circuit, more device can be manufactured on each wafer, thus improve the output of manufacturing facility.Because each technique used in IC manufacturing all has limit, therefore, it is very challenging for being manufactured by device less.In other words, given technique is only reduced to certain characteristic size usually, then then needs to change this technique or device layout.In addition, because device needs more and more faster design, the technique comprising test limitation is present in some common process and the test process for wafer reliability.
As just an example, during aluminum metal layer is used to first generation integrated circuit (IC)-components, aluminum metal layer is the selected material for semiconductor device always.Aluminium is selected to be owing to it providing good conductivity and invest dielectric substance together with semi-conducting material.Recently, aluminum metal layer partly substitute by copper-connection.Copper-connection has used to form advanced conventional semiconductor devices together with the dielectric substance of low-k k.Compared with aluminium, copper has the resistance value of improvement, makes signal propagate through copper-connection at a high speed.
More and more less due to device and demand for integrated level is more and more higher, the limitation of copper and low k dielectric material comprises less desirable Cu diffusion each other and the diffusion between Cu and polysilicon gate, diffusion causes the bridge joint between them, after connecting voltage, easily punctures.
In addition, after CMP, because inter-level dielectric is very thin, easily cause between Cu and polysilicon gate and easily puncture, this is also one of arch-criminal's mechanism affecting copper rear end reliability failure and electric fault.
The test structure that whether punctures between metal and metal is monitored as shown in Figure 1 in prior art, this test structure 100A at least comprises and is formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer 101A and the second comb metal layer 102A, and described first comb metal layer 101A and the second comb metal layer 102A mutually intersects and kept apart by dielectric layer.Also has a kind of structure surveyed metal and inter-metal medium and puncture, as shown in Figure 2, this structure comprises and is formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer 101A and the second comb metal layer 102A, described first comb metal layer 101A and the second comb metal layer 102A mutually intersects and is kept apart by dielectric layer, also comprises the snakelike metal level 103A be inserted between described first comb metal layer 101A and the second comb metal layer 102A.But these two kinds of structures can only be monitored metal and intermetallicly to be punctured, and cannot monitor puncturing between metal and polysilicon gate, and the monitoring punctured between metal and polysilicon gate is also the important topic ensureing reliability.
Therefore, provide a kind of novel be used for monitoring the test structure that interlayer dielectric layer punctures and be necessary.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is the test structure providing a kind of interlayer dielectric layer to puncture, and can not monitor for solving test structure of the prior art the problem whether punctured between metal layer and grid.
For achieving the above object and other relevant objects, the test structure that the utility model provides a kind of interlayer dielectric layer to puncture, described test structure at least comprises:
Be formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer and the second comb metal layer, and described first comb metal layer and the second comb metal layer mutually intersect and kept apart by dielectric layer;
Being formed in dielectric layer and being in some of different layers grid arranged in parallel with described metal layer, one end of grid is electrically connected with the gate terminal of a transistor device respectively; The cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer all has coincide point.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, described metal layer also comprises the snakelike metal level be inserted between described first comb metal layer and the second comb metal layer.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, the cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer and snakelike metal level all has coincide point.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, described metal layer is aluminum metal or copper metal.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, described grid is polysilicon gate.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, described transistor device is NMOS or PMOS.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, described transistor device also comprises source and drain terminal.
The scheme of a kind of optimization of the test structure punctured as the utility model interlayer dielectric layer, is kept apart by dielectric layer between described metal layer and grid.
As mentioned above, the test structure that interlayer dielectric layer of the present utility model punctures, at least comprise structure: be formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer and the second comb metal layer, and described first comb metal layer and the second comb metal layer mutually intersect and kept apart by dielectric layer; Being formed in dielectric layer and being in some of different layers grid arranged in parallel with described metal layer, one end of grid is electrically connected with the gate terminal of a transistor device respectively; The cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer all has coincide point.The test structure that the utility model provides has following beneficial effect:
1. can monitor between metal level and metal level and whether puncture;
2. can monitor between metal level and grid and whether puncture;
3. can find the number of the location point puncturing generation.
Accompanying drawing explanation
Fig. 1 is a kind of test structure schematic diagram of the prior art.
Fig. 2 is another kind of test structure schematic diagram of the prior art.
Fig. 3 is the schematic diagram of the test structure that in the utility model embodiment one, interlayer dielectric layer punctures.
Fig. 4 is the schematic diagram of the test structure that in the utility model embodiment two, interlayer dielectric layer punctures.
Fig. 5 is the schematic diagram punctured between the first comb metal layer and the second comb metal layer in embodiment one.
Fig. 6 is the schematic diagram punctured between metal level and grid in embodiment one.
Element numbers explanation
100,100A test structure
101,101A first comb metal layer
102,102A second comb metal layer
The snakelike metal level of 103,103A
20 grids
30 transistor devices
Embodiment
By particular specific embodiment, execution mode of the present utility model is described below, person skilled in the art scholar the content disclosed by this specification can understand other advantages of the present utility model and effect easily.
Refer to accompanying drawing.Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only in order to coordinate specification to disclose, understand for person skilled in the art scholar and read, and be not used to limit the enforceable qualifications of the utility model, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the utility model can produce and the object that can reach, still all should drop on technology contents that the utility model discloses and obtain in the scope that can contain.Simultaneously, quote in this specification as " on ", D score, "left", "right", " centre " and " one " etc. term, also only for ease of understanding of describing, and be not used to limit the enforceable scope of the utility model, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the utility model.
Embodiment one
As shown in Figure 3, the test structure 100 that the present embodiment provides a kind of interlayer dielectric layer to puncture, described test structure 100 at least comprises: metal layer and some grids 20 arranged in parallel; Wherein, metal layer and grid 20 are all formed in dielectric layer, and described metal layer comprises the first comb metal layer 101 and the second comb metal layer 102, and described first comb metal layer 101 and the second comb metal layer 102 mutually intersect and kept apart by dielectric layer; Described grid 20 is in different layers with described metal layer and is separated by dielectric layer, and one end of grid 20 is electrically connected with the gate terminal of a transistor device 30 respectively; The cross section projection in the vertical direction of each grid 20 and the first comb metal layer 101, second comb metal layer 102 all has coincide point.
The cross section of described first comb metal layer 101 and the second comb metal layer 102 is spaced and substantially parallel to each other, in the present embodiment, described grid 20 is positioned at the below of described metal layer, between kept apart by dielectric layer, the arragement direction of grid 20 is vertical with the arragement direction of the cross section of the second comb metal layer 102 with the first comb metal layer 101.
It should be noted that, described dielectric layer is not shown in the drawings, but metal level making is common process in the dielectric layer, and the position of dielectric layer should be appreciated that.
Exemplarily, described metal layer is aluminum metal or copper metal.In the present embodiment, described metal layer is copper metal.
Exemplarily, described grid 20 is polysilicon gate, can certainly be other suitable grid materials.
Exemplarily, described transistor device 30 is NMOS or PMOS.In the present embodiment, for NMOS, whole test structure and method of testing are introduced.One end of all grids 20 respectively connects a transistor device 30, wherein one end (such as all drain terminals) of transistor device 30 is connected to same current potential, the other end (all sources) is also connected to same current potential, and all transistor devices 30 form a transistor array.
The step utilizing the test structure in the present embodiment to carry out puncturing test is:
(1) first carry out Road test (Stress test), whether observation test structure punctures;
(2) if puncture, then carry out puncturing test, judge that the position puncturing generation is between metal-metal or between metai-gate, and the position number that judgement punctures.
The detailed process of carrying out Road test in step (1) is: as Fig. 3, the high pressure of 20V is applied at the A end of the first comb metal layer 101, the B of the second comb metal layer 102 is held ground connection (GND), and the source C of all crystals tube device 30 NMOS and drain terminal D is unsettled, if read high electric current at A end, then there occurs in explanation test structure and puncture.
The detailed process carrying out puncturing test in step (2) is: apply normal working voltage V at the A end of the first comb metal layer 101
dd, the C of all NMOS is held ground connection (GND), and the B of the second comb metal layer 102 holds and the D end of NMOS is all unsettled.If the electric current read at D end is very little, lower than 1E-8 peace, then illustrates and puncture and occur between metal and metal, as shown in Figure 5; If the electric current read at D end is a transistor device saturation current I
dsat, then illustrate and puncture and occur between metal and grid, and only have a position to puncture; If the electric current read at D end is 2*I
dsat, then illustrate and puncture and occur between metal and grid, and have two positions to puncture, as shown in Figure 6, dotted arrow represents the sense of current.
Embodiment two
As shown in Figure 4, the test structure 100 that the present embodiment provides a kind of interlayer dielectric layer to puncture, described test structure 100 at least comprises: metal layer and some grids 20 arranged in parallel; Wherein, metal layer and grid 20 are all formed in dielectric layer, and described metal layer comprises the first comb metal layer 101, second comb metal layer 102 and is inserted in the snakelike metal level 103 between described first comb metal layer 101 and the second comb metal layer 102; Described first comb metal layer 101 and the second comb metal layer 102 mutually intersect and are kept apart by dielectric layer; Described grid 20 is in different layers with described metal layer, and one end of grid 20 is electrically connected with the gate terminal of a transistor device 30 respectively; The cross section projection in the vertical direction of each grid 20 and the first comb metal layer 101, second comb metal layer 102 and snakelike metal level 103 all has coincide point.
The cross section of described first comb metal layer 101 and the second comb metal layer 102 is spaced and substantially parallel to each other, in this enforcement, described grid 20 is positioned at the below of described metal layer, between kept apart by dielectric layer, the arragement direction of grid 20 is vertical with the arragement direction of the cross section of the second comb metal layer 102 with the first comb metal layer 101.
It should be noted that, described dielectric layer is not shown in the drawings, but metal level making is common process in the dielectric layer, and the position of dielectric layer should be appreciated that.
Exemplarily, described metal layer is aluminum metal or copper metal.In the present embodiment, described metal layer is copper metal.
Exemplarily, described grid 20 is polysilicon gate, can certainly be other suitable grid materials.
Exemplarily, described transistor device 30 is NMOS or PMOS.In the present embodiment, for NMOS, whole test structure and method of testing are introduced.One end of all grids respectively connects a transistor device, wherein one end (such as all drain terminals) of transistor device is connected to same current potential, the other end (all sources) is also connected to same current potential, and all transistor devices 30 form a transistor array.
The testing procedure utilizing the test structure in the present embodiment to carry out puncturing in the step of test and embodiment one is similar, but it should be noted that, A end in embodiment one refers to one end of the first comb metal layer 101,20V high pressure in step (1) is applied on the first comb metal layer 101, and the A end in the present embodiment refers to one end of the first comb metal layer 101 and the second comb metal layer 102, the high pressure 20V in step (1) is applied on the first comb metal layer 101 and the second comb metal layer 102 simultaneously; B end in embodiment one refers to one end of the second comb metal layer 102, in step (1), ground connection is the second comb metal layer 102, and in the present embodiment, B end refers to one end of snakelike metal level 103, in step (1), ground connection is snakelike metal level 103.In step (2), method in like manner.
In sum, the test structure that interlayer dielectric layer of the present utility model punctures, at least comprise structure: be formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer and the second comb metal layer, and described first comb metal layer and the second comb metal layer mutually intersect and kept apart by dielectric layer; Being formed in dielectric layer and being in some of different layers grid arranged in parallel with described metal layer, one end of grid is electrically connected with the gate terminal of a transistor device respectively; The cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer all has coincide point.Whether the utility model test structure can be monitored between metal level and metal level, between metal level and grid simultaneously and puncture, and can find the number of the location point puncturing generation.
So the utility model effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all without prejudice under spirit of the present utility model and category, can modify above-described embodiment or changes.Therefore, such as have in art and usually know that the knowledgeable modifies or changes not departing from all equivalences completed under the spirit and technological thought that the utility model discloses, must be contained by claim of the present utility model.
Claims (8)
1. the test structure that punctures of interlayer dielectric layer, it is characterized in that, described test structure at least comprises:
Be formed at metal layer in dielectric layer, described metal layer comprises the first comb metal layer and the second comb metal layer, and described first comb metal layer and the second comb metal layer mutually intersect and kept apart by dielectric layer;
Being formed in dielectric layer and being in some of different layers grid arranged in parallel with described metal layer, one end of grid is electrically connected with the gate terminal of a transistor device respectively; The cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer all has coincide point.
2. the test structure that punctures of interlayer dielectric layer according to claim 1, is characterized in that: described metal layer also comprises the snakelike metal level be inserted between described first comb metal layer and the second comb metal layer.
3. the test structure that punctures of interlayer dielectric layer according to claim 2, is characterized in that: the cross section projection in the vertical direction of each grid and the first comb metal layer, the second comb metal layer and snakelike metal level all has coincide point.
4. the test structure that punctures of interlayer dielectric layer according to claim 1, is characterized in that: described metal layer is aluminum metal or copper metal.
5. the test structure that punctures of interlayer dielectric layer according to claim 1, is characterized in that: described grid is polysilicon gate.
6. the test structure that punctures of interlayer dielectric layer according to claim 1, is characterized in that: described transistor device is NMOS or PMOS.
7. the test structure that punctures of interlayer dielectric layer according to claim 1, is characterized in that: described transistor device also comprises source and drain terminal.
8. the test structure that punctures of interlayer dielectric layer according to claim 1, is characterized in that: kept apart by dielectric layer between described metal layer and grid.
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| CN201420508299.7U CN204067309U (en) | 2014-09-04 | 2014-09-04 | The test structure that a kind of interlayer dielectric layer punctures |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328630A (en) * | 2016-11-09 | 2017-01-11 | 上海华力微电子有限公司 | Testing structure and testing method for monitoring isolation performance among different layers of metal layer |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN113363241A (en) * | 2021-05-13 | 2021-09-07 | 武汉新芯集成电路制造有限公司 | Test structure and test method |
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2014
- 2014-09-04 CN CN201420508299.7U patent/CN204067309U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328630A (en) * | 2016-11-09 | 2017-01-11 | 上海华力微电子有限公司 | Testing structure and testing method for monitoring isolation performance among different layers of metal layer |
| CN112103202A (en) * | 2020-11-10 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN112103202B (en) * | 2020-11-10 | 2021-02-12 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
| CN113363241A (en) * | 2021-05-13 | 2021-09-07 | 武汉新芯集成电路制造有限公司 | Test structure and test method |
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Granted publication date: 20141231 Termination date: 20190904 |
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