CN204046591U - Possesses the receiving circuit of multiple conversion factor - Google Patents
Possesses the receiving circuit of multiple conversion factor Download PDFInfo
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- CN204046591U CN204046591U CN201420563685.6U CN201420563685U CN204046591U CN 204046591 U CN204046591 U CN 204046591U CN 201420563685 U CN201420563685 U CN 201420563685U CN 204046591 U CN204046591 U CN 204046591U
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Abstract
Possesses the receiving circuit of multiple conversion factor, belong to areas of information technology, by decoding block, automatic transcoding units, interlocking unit, performance element, radio frequency reception demodulator circuit forms jointly, the output of radio frequency reception demodulator circuit connects the input of decoding block, decoding block has four outputs, connect with the input of automatic transcoding units for become code control end, what connect with performance element is last output, all the other two export connection interlocking unit, interlocking unit starts when cracking mistake, the automatic transcoding units of locking and performance element, under initial condition, it is corresponding that reception variation code and transmitting change code, after receiving first time signal, start automatic transcoding units to change, with launch change code change after code corresponding, receive after second time transmits and just start performance element, significantly increase the difficulty cracking decoding, improve the performance of remote control product all sidedly.
Description
Technical field
Belong to areas of information technology.
Background technology
Far distance controlled technology and telecontrol engineering, it is generally used for present RTV remote television, remote-controlled toy vehicle, the remote controller of air-conditioning, the locking and the place such as to unlock of automobile, for front several prods, the level of confidentiality of telecontrol engineering is required not to be very high, prevailing coding techniques just can meet the requirements, but locking and unblock to automobile, the requirement for remote control is but very high, particularly level of confidentiality degree.
Namely the level of confidentiality of remote control is the level of confidentiality of coding, how to promote the level of confidentiality of remote control product, what this just needed the coding category thoroughly changing three kinds of states cracks ability, be exactly macroscopically from other side, increase the conversion requirement of launching and receiving, the existence that this conversion requires, certainly greatly can improve the ability of cracking, and conversion requires more, obviously cracks difficulty larger.Our unit once have developed the transmitting Decision Making of Line Schemes of multiple change code, increase the conversion factor of launching, thus launch a kind of code thread having multiple conversion factor, improve the level of confidentiality degree of coding to a great extent, but also need the receiving lines of decoding to coordinate with it, just can become a complete entirety, if receive the uniqueness accomplishing to export, validity sometimes, this extremely has meaning to lifting level of confidentiality degree, but such reception needs relevant technical support, so be in now in the middle of research.
Summary of the invention
Main purpose of the present utility model proposes a kind of New Measure, the change code receiving circuit matched can be launched with change code, realize the reception that radiating portion sends twice change code, launch for research dicode and create better condition, four kinds of functions can be produced: one is the signal that can receive two kinds of codes after enforcement, two is receive to have sequential, first signal unique for the first time can only be received, then second time signal could be received, three is unique property with output, four is validity sometimes when receiving, owing to adding four kinds of important restrictions, so significantly increase the difficulty cracking decoding, improve the performance of remote control product all sidedly.
The measure that this patent proposes is:
1, the receiving circuit possessing multiple conversion factor is made up of jointly decoding block, automatically transcoding units, interlocking unit, performance element, radio frequency reception demodulator circuit.
Wherein: the output of radio frequency reception demodulator circuit connects the input of decoding block, and decoding block has four output, connect with the input of automatic transcoding units for become code control end, what connect with performance element is last output, all the other two output connection interlocking unit.
Wherein 5 connections of decoding block 8 bit code position are fixed code, and another 3 become change code end, namely change code.
Automatic transcoding units is made up of current-limiting resistance, the first inverter, the second inverter, control switch: receive after the input of the first inverter connects current-limiting resistance and become code control end, the output of the first inverter connects two-way, one tunnel connects the first variation code, another road connects the input of the second inverter, the output of the second inverter connects two-way, and a road connects the 3rd variation code, and another road connects the control end of control switch, the input termination power of control switch, the output of control switch connects the second variation code.
Performance element is made up of with executive circuit trigger resistance, diac: one end of trigger resistance is connected last output, and the other end of trigger resistance and the positive pole of diac are connected together, and the negative pole of diac connects executive circuit.
The positive contact of performance element first locking diode sends out the positive pole of diode, and the negative pole of performance element first locking diode connects and becomes code control end.
Interlocking unit by or gate diode, interlocking inverter, locking diode form:
3rd output exports with the 4th the positive pole meeting or gate diode respectively, or the negative pole of gate diode be connected together connect interlocking inverter input, the output of interlocking inverter connects the negative pole of two locking diodes, the positive contact of a locking diode and performance element second locking diode sends out the positive pole of diode, and the positive pole of another locking diode and automatic transcoding units locking diode connects the input of the first inverter in automatic transcoding units.
2, decoding block used is transient state type.
3, control switch is analog switch.
4, the first inverter, the second inverter, interlocking inverter are same integrated circuits, and there are 6 independently inverters its inside, with 3 wherein in this measure.
5, in decoding block, 5 fixed code should be corresponding with the fixed code of 5 in encoding block.
This measure is explained as follows further:
One, sketch the cardinal principle of single ripple dicode transmitting that our unit for the previous period develops: in 8 bit codes of coding integrated package, wherein 5 is fixed code, all the other 3 is variation code, when launching, launch two subcategory numbers.Transmitter code is 5 fixed code wherein for the first time, and the first subcategory number of the variation code of 3, and the code that second time is launched is 5 constant fixed code, and the coded signal after the variation of 3 variation codes.And receive and also will receive twice signal, be once the first subcategory number that 5 fixed code and 3 change code, be for the second time 5 fixed code and 3 change code change after coded signal.
In the utility model, launch a subcategory number of the first variation code for suspending, code after first variation code variation is 1, one subcategory number of the second variation code is 1, code after second variation code variation is 0, so the subcategory number receiving the first variation code is suspend, the code after the first variation code variation is 1, second variation code is once the code after the 1, second variation code variation is 0.
Two, in this measure, interlocking inverter and the first inverter, the second inverter are same integrated circuits, and this IC interior has 6 independently inverters, and with 3 wherein in this measure, several inverter does not interfere with each other.
In measure 1, produce the line construction of twice decoding: corresponding with 5 bit code lines in decoding block and radiating portion integrated package of encoding.5 bit codes have wherein connected into fixed code (30 in Fig. 2).All the other 3 bit codes become the change code end of a kind of reception twice signal, and when initial condition, in receiving unit, the first variation code initial condition code bit that is a subcategory number presents is 1 state, second variation code initial condition is for suspending, second variation code initial condition is 0 state, and receive first time transmit after just produce decoding in first variation code become 0, second variation code be the state of 1, the 3rd change code 1.Its decoding is integrated with four outputs, wherein first output connects with automatic transcoding units, be and become code control, directly control to become code, the second output connects with performance element, is last output, direct output decoded result, 3rd and the 4th exports and is connected interlocking unit, produce multidigit when exporting, and directly locking becomes code and execution at garbled-reception or when cracking code bit.
Three, automatic transcoding units realizes the reason of transcoding: when become code control end no-output into zero time, the output of the first inverter is high-order, first variation code is high-order, and the second inverter connected be input as low level, 3rd variation code is low level, and the control end of control switch is connected on an output of the second inverter, control end no-voltage, in disconnecting shape, output is access failure power supply also access failure ground wire both, second variation code is also the suspension of both access failure power supply also access failure ground wires, when becoming code control end and having voltage to export, the output of the first inverter becomes low level from a high position, second inverter becomes a high position from low level, the control end of control switch has voltage to make switch be on-state, so the first variation code becomes low level from a high position, second variation code becomes a high position from suspension, 3rd variation code becomes a high position from low level, thus form the transition process of two variation codes.
Four, this measure can produce four kinds of functions after implementing: one is to receive change coded signal, two is receive to have sequential, first signal unique for the first time can only be received, then second time signal could be received, three is unique property with output, four is validity sometimes when receiving, owing to adding four kinds of important restrictions, so significantly increase the difficulty having cracked and decoded.
1, the principle of two kinds of coded signals can be received:
(1), receive the first subcategory number of sending of radiating portion principle: as shown in Figure 2, in an initial condition, change code control end (7 in Fig. 2) Non voltage output of decoding block, the output of the first inverter connected is because logical inversion is for high-order, and the output of the second inverter becomes low level, the control end of control switch is connected on the output of the second inverter, the output no-voltage of the second inverter, control switch is in disconnecting shape, its output is missed electric source also unearthed line both, in suspension, the second variation code that it connects also is suspension, and the first variation code is connected on the first inverter output in high-order, the output that 3rd variation code is connected on the second inverter is low-end trim, now not only can receive 6 fixed code, also a coded signal of variation code can be received.
(2), receive the second subcategory number of sending of radiating portion principle: after receiving the first signal sent, at this moment the change code control end (7 in Fig. 2) of decoding block exports the signal of 1, the first inverter connected is because input is high-order, so export as low level, and the second inverter is because be input as low level, so it is high-order for exporting, the control end of control switch is because there is electricity to make switch connection, and the input of control switch is the power supply connect, therefore its output is also for switching on power in high-order, so it is low level that the first inverter exports the variation code connected, the 3rd variation code that the output of the second inverter connects is high-order, and the second variation code that the output of control switch connects is high-end trim, after changing with the variation code launched, code is identical, so the different coded signal of second time can be received.
2, receive the sequential that has that twice change code must have successively to limit and principle: because the first initial condition becoming code end of decoding block is 1, second becomes the initial condition of code end into suspending, the initial condition of the 3rd variation code is 0, so the first variation code one subcategory number only having radiating portion to send is 1, one subcategory number of the second variation code is for suspending, when 3rd variation code is 0, launching and receiving code could be corresponding, the last output of decoding block just has output, thus cause decoding block variation code just to have the new code of secondary, and this new code could coincide with transmitting, the last output making decoding block connect performance element just has high-order output.If launching what first send is quadratic code 0 signal of the first variation code, and the first variation code of decoding block is also in the suspension signal under initial condition, cannot receive, although the 3rd variation code state is now 0, but code bit is different, so also cannot normally receive, so the last output connecting performance element does not have output.More than analyze, if cracker is first the second subcategory number crack code, but because the first subcategory number is not opened, becoming code control end is low level, and performance element first locking diode (18 in Fig. 2) works, to performance element clamper, only have after the first subcategory number is opened, could receive the second subcategory number, two subcategory numbers correctly just can have last output, namely the output of decoding block connection performance element has voltage, could start performance element.
3, there is the principle of benefit that bit line uniquely receives and formation: in this measure, add interlock function, its benefit is when criminal is when cracking, and the bit line determined is wrong, then therefore cannot crack completely without output.Its reason one only has to become code bit line correctly, and what second time just may be had to receive is correct, otherwise can not normal reception.Two is that the bit line only exported to rear class exports correctly, last output is just had when two subcategory numbers are correct, three is if when multidigit output has output or receives mistake simultaneously, because interlocking inverter input becomes or door, its output is low level, second clamp diode (16 in Fig. 2) of performance element, the automatically clamp diode (17 in Fig. 2) of transcoding units work, clamper is carried out to performance element, automatically transcoding units, cannot start so form performance element, automatically transcoding units.And decoding block the 3rd export with second export all no-voltage time, interlocking inverter input no-voltage, its output must be high pressure, so logic is now correct.
4, the principle of twice receiving code validity sometimes: be the transient state type selected because decoding integrated circuit exports, so criminal can not be allowed to crack the more time, also be that the first subcategory number cracks successfully, second subcategory number must provide in the very short time, otherwise invalid, must will restart two subcategory numbers.
5, the first inverter, the second inverter are same integrated circuit 4069 with interlocking inverter, and there are 6 independently inverters inside, does not disturb each other, inverter is used for logical inversion, voltage by low uprise or by high step-down time, have cushioning effect, rear class element can not be damaged.
After the invention process, after coordinating with the radiating portion applied for before our unit, below outstanding feature:
1, the character of coding integrated circuit is improved, realize the reception that radiating portion sends twice change code, just output is had after must receiving two subcategory numbers after receiving circuit decoding, thus there is the very high anti-ability of cracking, signal transmission is accurate, and keeping cheap advantage, the product making it make possesses the very large market competitiveness.
2, owing to increasing interlocking portions, this reception defines the function of quadruple constraint, substantially increases and cracks difficulty, but but can reliably receive.
If 3 with the combination again of rolling code circuit, it decodes difficulty is superpower, because rolling code is the coding of a class character, and in this measure, dicode transmitting is the coding of a class character, two kinds of coded combinations of different nature are larger than a kind of code breaks difficulty of character.
4, the dicode receiving lines of this measure receives reliable.
Its reason is that the decoding block fixed code in the present invention conforms to completely with the fixed code of radiating portion.Variation code is also also formulated according to the variation code launched, and have followed the rule of this kind of encoding and decoding block completely.Another very important reason is, what the decoding in receiving lines in the present invention realized is " tracking system ", that is to say that just automatically become the code needed for second time, twice receiving course is not disorderly, onside after receiving first change code.
5, crack very difficult: mainly contain three reasons, one is to have twice different code could realize decoding, just has output.Two is that different code needed for twice has timing requirements, can not be disorderly, 3rd major reason is, the requirement that this twice different change codes is also necessary free when launching, because the integrated output of the coding adopted in the present invention is the transient state output type adopted, in other words after receiving signal, its output can only remain a transient state high position, will disappear after blink.If criminal, after correct code is made in exploration in first time, want that within the very of short duration time, feel out the correct code of second time is more obviously very difficult.Also be that criminal wants to crack the present invention must by three passes: one is must twice different dicode, and two is also must have sequential, and three is also must be limited within the very short time just can complete, and therefore adopts " the barcode scanning instrument " of crime to crack and hardly may.From meaning in a certain respect, higher than rolling code, because crack rolling code in theory, there is certain probability in this level of confidentiality, and just this probability is very low, very low, and the present invention is because exist the above-mentioned three elements that crack, this crack probability just may be lower.
6, circuit is reliable, and one is that circuit is simplified.Two is that inverter has cushioning effect, can not damage element when voltage levels converts.
7, produce easily, one be need not be valuable equipment and instrument, two is that technology is simple, and three are that circuit is simplified and component requirements used is low, so can produce very high first-pass yield, very applicable minuscule-type-enterprise produces.
Accompanying drawing explanation
Fig. 1 is total measure figure of the receiving circuit possessing multiple conversion factor.
In figure: 1, radio frequency reception demodulator circuit (as superregenerative reception demodulating unit, or beat reception demodulating unit); 2, decoding block; 3, interlocking unit; 4, the 4th of decoding block the export; 5, the 3rd of decoding block the export; 6, the last output of decoding block; 7, the change code control end of decoding block; 8, performance element; 9, automatic transcoding units; 10, the first variation code; 11, the second variation code; 12, the 3rd variation code.
Fig. 2 is the practical circuit diagram of this measure relative section.
In figure: 1, radio frequency reception demodulator circuit (as superregenerative reception demodulating unit, or beat reception demodulating unit); 2, decoding block; 4, the 4th of decoding block the export; 5, the 3rd of decoding block the export; 6, the last output of decoding block; 7, the change code control end of decoding block; 10, first becomes code end; 11, second becomes code end; 12, the 3rd variation code; 15, trigger resistance; 16, performance element second clamp diode; 17, the clamp diode of automatic transcoding units; 18, the first clamp diode of performance element; 19, diac; 20, executive circuit; 21, the 4th export connect or gate diode; 22, the 3rd export connect or gate diode; 23, inverter is interlocked; 25, current-limiting resistance; 26, the first inverter; 27, the second inverter; 28, control switch switch.
Embodiment
Fig. 1 and Fig. 2 describes the concrete a kind of mode implemented jointly.
1, select element: wherein decoding block selects 2272, analog switch CD4066 selected by control switch, and interlocking inverter, the first inverter, the second inverter select 4069.
2, weld: weld by Fig. 2.Total measure principle as shown in Figure 1.
3, adjustment and detection:
(1), can the Function detection of automatic changing code bit line: when launching first time signal, can reliable reception: the change code control end surveying decoding block with universal instrument has high-order output.
(2), twice signal receiving function detects: after receiving the first signal, secondary signal of fasting ejection very much, at this moment the last output of decoding block has high-order output.Have voltage to export when surveying this with universal instrument, if when adopting oscilloscope, display screen has high-order reaction.
(3) Received signal strength whether sequential, is detected: last output universal instrument or oscilloscope being received decoding block, if first launch secondary signal, now the last output of decoding block is without high pressure, if there is high pressure, first inverter or the second inverter are described, control switch damages, or the clamp diode of transcoding units automatically connects instead.
(4) whether reliably interlocking unit, is detected: the positive pole surveying performance element diac with universal instrument, when multidigit output has output simultaneously, diac positive pole answers no-voltage, otherwise explanation or gate diode do not weld, or interlocking inverter damages, or each clamp diode is bad.
(5), detect whether decoding block is non-interlocking type: first output and second of universal instrument or oscilloscope being received decoding block exports to be observed, and after receiving signal, signal can disappear within the time of short duration, otherwise should change the model of decoding block.
Claims (5)
1. possess the receiving circuit of multiple conversion factor, it is characterized in that: be jointly made up of decoding block, automatically transcoding units, interlocking unit, performance element, radio frequency reception demodulator circuit;
Wherein: the output of radio frequency reception demodulator circuit connects the input of decoding block, and decoding block has four output, connect with the input of automatic transcoding units for become code control end, what connect with performance element is last output, all the other two output connection interlocking unit;
Wherein 5 connections of decoding block 8 bit code position are fixed code, and another 3 become change code end, namely change code;
Automatic transcoding units is made up of current-limiting resistance, the first inverter, the second inverter, control switch: receive after the input of the first inverter connects current-limiting resistance and become code control end, the output of the first inverter connects two-way, one tunnel connects the first variation code, another road connects the input of the second inverter, the output of the second inverter connects two-way, and a road connects the 3rd variation code, and another road connects the control end of control switch, the input termination power of control switch, the output of control switch connects the second variation code;
Performance element is made up of with executive circuit trigger resistance, diac: one end of trigger resistance is connected last output, and the other end of trigger resistance and the positive pole of diac are connected together, and the negative pole of diac connects executive circuit;
The positive contact of performance element first locking diode sends out the positive pole of diode, and the negative pole of performance element first locking diode connects and becomes code control end;
Interlocking unit by or gate diode, interlocking inverter, locking diode form:
3rd output exports with the 4th the positive pole meeting or gate diode respectively, or the negative pole of gate diode be connected together connect interlocking inverter input, the output of interlocking inverter connects the negative pole of two locking diodes, the positive contact of a locking diode and performance element second locking diode sends out the positive pole of diode, and the positive pole of another locking diode and automatic transcoding units locking diode connects the input of the first inverter in automatic transcoding units.
2. the receiving circuit possessing multiple conversion factor according to claim 1, is characterized in that: decoding block used is transient state type.
3. the receiving circuit possessing multiple conversion factor according to claim 1, is characterized in that: control switch is analog switch.
4. the receiving circuit possessing multiple conversion factor according to claim 1, is characterized in that: the first inverter, the second inverter, interlocking inverter are same integrated circuits, and there are 6 independently inverters its inside, with 3 wherein in this measure.
5. the receiving circuit possessing multiple conversion factor according to claim 1, is characterized in that: in decoding block, 5 fixed code should be corresponding with the fixed code of 5 in encoding block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420563685.6U CN204046591U (en) | 2014-09-28 | 2014-09-28 | Possesses the receiving circuit of multiple conversion factor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420563685.6U CN204046591U (en) | 2014-09-28 | 2014-09-28 | Possesses the receiving circuit of multiple conversion factor |
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| Publication Number | Publication Date |
|---|---|
| CN204046591U true CN204046591U (en) | 2014-12-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420563685.6U Expired - Fee Related CN204046591U (en) | 2014-09-28 | 2014-09-28 | Possesses the receiving circuit of multiple conversion factor |
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2014
- 2014-09-28 CN CN201420563685.6U patent/CN204046591U/en not_active Expired - Fee Related
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141224 Termination date: 20160928 |
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| CF01 | Termination of patent right due to non-payment of annual fee |