CN204031152U - A kind of dicode receiving circuit with timing - Google Patents
A kind of dicode receiving circuit with timing Download PDFInfo
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- CN204031152U CN204031152U CN201420524195.5U CN201420524195U CN204031152U CN 204031152 U CN204031152 U CN 204031152U CN 201420524195 U CN201420524195 U CN 201420524195U CN 204031152 U CN204031152 U CN 204031152U
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Abstract
A kind of dicode receiving circuit with timing, belong to telecontrol engineering field, by radio frequency reception demodulator circuit, decoding integrated package, performance element, interlock circuit, automatically transcoding units forms the receiving circuit that can match with dicode launch scenario jointly, the output of radio frequency reception demodulator circuit connects the input of decoding integrated package, decoding integrated package has four outputs, first output become a yard control end and connect automatic transcoding units, the 3rd output is that last output connects performance element, second output is connected interlock circuit with the 4th output, under initial condition, receive and transmit for the first time, make to become code control end into high-order, start automatic transcoding units and carry out transcoding, receive and transmit for the second time, start performance element, if exporting, wrong reception or multidigit have high pressure, interlock circuit starts, make finally to export without high pressure, realize the reception of twice change code of " 0 " that radiating portion sends and " suspensions " yard, the research of twice emitting is created to good condition.
Description
Technical field
Belong to telecontrol engineering field.
Background technology
Remote control coding lift-off technology, the one, kind of application utmost point electronic technology widely occurs very widely in the masses' life, as the security and anti-theft that is used in almost car close the door and open the door upper, be used in high quality anti-theft door open the door with close the door upper etc.High-end remote control product, has the problem that cost is too high, how to use thing cheaply to create high-end product, and this is the thing of always all pursuing.
Low taking 2262 its costs of the coding of the tri-state as representative integrated circuit, make product and have very large price advantage, but coding is simple, level of confidentiality is not high enough, so can not use widely in high-end product, how to use the integrated circuit of encoding cheaply to produce the product of High Security Level degree, allow remote control product use more widely, this is a good problem to study.If imagination can be produced with cheap coding integrated circuit the coding circuit of the highly dense utmost point, obviously the competitiveness that improves product is had a very big significance.
Our unit had once been developed into the transmitting Decision Making of Line Schemes of multiple single ripple dicodes in the time of leading portion, had created good condition for this scheme, but this not enough, and unit also will apply for out that multiple supporting receiving circuits with it become with it as a whole from now on.
Summary of the invention
The main purpose of this patent is to propose a kind of new measure, forming a kind of receiving lines that becomes code matches with the dicode launch scenario of applying for before our unit, realize the reception of twice change code of " 0 " that radiating portion sends and " suspensions " yard, the research of twice emitting is created to good condition, after enforcement, the one, can receive the signal of two kinds of codes, the 2nd, receive and there is sequential, first can only receive unique for the first time signal, then could receive signal for the second time, the 3rd, there is unique property of output, the 4th, effective property while reception, owing to having increased by four kinds of important restrictions, increase greatly and cracked the difficulty of decoding, after other senior class coding integrated circuit combination, can realize the superpower anti-combined effect that cracks.
The measure that this patent proposes is:
1, a kind of dicode receiving circuit with timing is made up of jointly radio frequency reception demodulator circuit, decoding integrated package, performance element, interlock circuit, automatic transcoding units.
The output of radio frequency reception demodulator circuit connects the input of decoding integrated package, decoding integrated package has four outputs, first output become a yard control end and connect automatic transcoding units, and the 3rd output is that last output connects performance element, and second output is connected interlock circuit with the 4th output.
Automatically transcoding units is made up of two bidirectional analog switches: the control end of first bidirectional analog switch connects a change code control end after connecting protective resistance; the input end grounding line of first bidirectional analog switch; the control end of the output of first bidirectional analog switch and second bidirectional analog switch joins; resistance of control termination of second bidirectional analog switch is to power supply; the input end grounding of second bidirectional analog switch, the output of second bidirectional analog switch connects first of decoding integrated package and becomes code end.
Interlock circuit by or gate diode, not gate, clamp diode form.
The second output exports with the 4th the positive pole that is connected respectively or gate diode, or the negative pole of gate diode is connected together and connects the input of not gate, the output of not gate connects the positive pole of two clamp diodes, and one of them clamp diode is the control end that the positive pole of automatic transcoding units clamp diode is connected on first bidirectional analog switch; Another clamp diode is the input that the positive pole of performance element the second clamp diode connects executive circuit in performance element.
Executive circuit: the one end of triggering resistance connects last output, and the other end of circuits for triggering connects the input of executive circuit.
2, bidirectional analog switch is the integrated circuit CD4066 that there are 4 separate analogue switches inside.
3, decoding integrated package is non-locking type.
4, integrated form is made in this measure.
This measure is further explained as follows:
The cardinal principle of single ripple dicode transmitting that, for the previous period, our unit develops:
In 8 bit codes of coding integrated circuit, wherein 7 is fixed code, wherein one is variation code, radiating portion is in the time of transmitting, launch two subcategory numbers, wherein transmitter code is 7 fixed code wherein for the first time, and the first subcategory number of the variation code of, the code of transmitting is for the second time 7 constant fixed code, and a coded signal changing after code variation.And the coded signal for the first time that the receiving unit that the present invention matches is the integrated middle variation of receipt decoding is " 0 ", signal is Floating situation for the second time.(meaning that suspension is is that this code neither connects the code that " 1 " is not again connection " 0 ").And present receiving lines of the present invention, will can receive reliably the variation code sending for the first time is exactly " 0 ", signal is the signal of Floating situation for the second time.
Two, the principle that produces twice decoding is: decoding integrated package has 8 bit codes, 7 bit codes are wherein connect for fixed code (03 in Fig. 2), remaining bit code becomes the change code (04 in Fig. 2) that receives twice signal, in the time of initial condition, because decoding integrated package is not also received signal, therefore decode the not low level of output of integrated package, the control end of first bidirectional analog switch (018 in Fig. 2) is low, now the control end of second bidirectional analog switch (020 in Fig. 2) is high-order, because first bidirectional analog switch access failure, the control end of second bidirectional analog switch has a resistance (021 in Fig. 2) to receive power supply, the control end of second bidirectional analog switch is connected, that its output is just 0, therefore becoming code end is 0, and when receiving after signalling, first bidirectional analog switch connection, the control end of second bidirectional analog switch is received ground wire, second bidirectional analog switch disconnects, thereby formation becomes code.
Decoding integrated package has four outputs, and wherein first output is called again and becomes code control end; the output of this end is connected with first bidirectional analog switch after joining with protective resistance, and the 3rd output, claims again the output to rear class; this output rear class is connected, and is directly to export decoded result at the corresponding levels.The structure of this circuit can realize the present invention and receive the requirement that becomes code.In above-mentioned line construction, the circuit joining with first output is automatic transcoding units.
Three, this measure can produce four kinds of functions after implementing: the one, can receive the signal of two kinds of codes, the 2nd, receive and there is sequential, first can only receive unique for the first time signal, then could receive signal for the second time, the 3rd, there is unique property of output, the 4th, effective property while reception, owing to having increased by four kinds of important restrictions, has cracked so increased greatly the difficulty of decoding.
1, the reason of reception two coded signals is transcoding voluntarily, and its principle is:
(1) receive the first subcategory number of sending of radiating portion principle: in Fig. 2, under initial condition, also access failure of first two-way mould switch, second bidirectional analog switch presents on-state, thereby its output connected code bit initial condition is 0 state, at this moment can not only receive reliably 7 fixed code, can receive that radiating portion becomes the state of " 0 " that code bit sends for the first time simultaneously.First signal " 0 " of sending out with radiating portion is corresponding.Because its principle is not run counter to the performance of existing product.
(2) receive the second subcategory number of sending of radiating portion principle: when receiving after the first signal sending, at this moment decode the first output of integrated circuit, be to become code control end (08 in Fig. 2), the signal of output 1, this signal makes the control end of first bidirectional analog switch for high, make first bidirectional analog switch connection, so the control end of second bidirectional analog switch has been received ground wire, therefore, second bidirectional analog switch disconnects, its output did not both join with ground wire, non-transformer again, therefore, this yard of line is to being suspended state, corresponding with the coded signal of the change for the second time suspension code of radiating portion, thereby can receive second change coded signal that radiating portion sends.
2, the sequential that has that twice change code of reception must have successively limits and principle: because the initial shape of variation code of decoding integrated package is " 0 ", so while only having radiating portion to send variation code for " 0 ", transmitting could be corresponding with receiving code, the change code control end of decoding integrated package just has output, thereby cause that decoding integrated package variation code just has the new code of " suspension ", and this new code could and transmitting coincide, the last output that the integrated package that makes to decode connects performance element just has a high position to export.Otherwise radiating portion is if first to launch be secondary " suspension " signal, and the variation code of the integrated package of now decoding is that under initial condition, " 0 " code does not meet with transmitter code, and the 4th output that connects performance element does not have output.More than analyze, if being the second subcategory number of first use, cracker cracks code, but because the first subcategory number is not opened, first clamp diode (015 in Fig. 2) of performance element works, and to performance element still clamper, only has after the first subcategory number is opened, could receive the second subcategory number, two subcategory numbers correctly just can have last output, and the output that the integrated package of decoding connects performance element has voltage, could start performance element.
3, there is the benefit of the unique reception of bit line and the principle of formation: in measure 1, increased interlock circuit, its benefit is when criminal is in the time cracking, and definite bit line mistake, completely without output, therefore cannot crack.Its reason one is to only have the code bit of change line correct, just may have receive for the second time correct, otherwise can not normally receive.The 2nd, only correct to the bit line output of rear class output, just there is last output when correct in two subcategory numbers, the 3rd, if when multidigit output has output or receives mistake simultaneously, because the input of not gate becomes or door, form interlocking, non-gate output terminal is low level, second clamp diode (014 in Fig. 2) of performance element, the clamp diode (017 in Fig. 2) of automatic transcoding units work, to performance element, automatically transcoding units has carried out clamper, so form performance element, transcoding units cannot start automatically.
4, the principle of twice effective property of receiving code: because decoding integrated circuit output is the transient state type of selecting, so can not allow criminal crack the more time, also be after the first subcategory number cracks successfully, the second subcategory number must provide in the very short time, otherwise invalid, must will restart two subcategory numbers.
Four, the bidirectional analog switch using in measure 1 is CD4066, in the time that control end adds high level, and switch conduction, conduction impedance is lower, and in addition, conduction impedance is substantially constant in whole input reference signal.Eliminated the variation of switching transistor threshold voltage with input signal, therefore within the scope of whole working signal, conduction impedance is lower.Compared with single channel switch, have that input signal peak voltage ranges equals supply voltage and the advantage such as conduction impedance is more stable in input reference signal.Switch cut-off in the time that control end adds low level.When bidirectional analog switch conduction, conducting resistance is tens ohm; When analog switch cut-off, present very high impedance, can become open circuit.Bidirectional analog switch can transmission of digital signals and analog signal, and the upper limiting frequency of the analog signal that can transmit is 40MHz.There are 4 independently analog switches CD4066 inside, and crosstalking of each switch room is very little, and representative value is-50dB.
Bidirectional analog switch is a kind of three-stable state circuit, and it can, according to the level of gating end, determine the state of input end and output.When elected go side is in strobe state, the state of output depends on input end's state; Elected go side in the time of cut-off state, no matter input end's level how, output is all high-impedance state.That bidirectional analog switch has possessed is low in energy consumption, speed fast, machinery-free contact, volume are little and the feature such as long service life.
After the invention process, after coordinating with the radiating portion of applying for before our unit, below outstanding feature:
1, greatly promoted the character of rudimentary coding integrated circuit, present inventor's decoding is integrated just has output after must receiving two subcategory numbers, thereby there is the very high anti-ability of cracking, because rudimentary coding integrated circuit has cheap advantage, so its product has very strong competitiveness.
2, increased interlock function newly, made this reception form the function of quadruple constraint, greatly increased and cracked difficulty, but but can receive reliably.
If 3 with the combination again of rolling code circuit, it decodes difficulty is superpower, because rolling code is the coding of a class character, and in this measure, dicode transmitting is the coding of a class character, two kinds of coded combinations of different nature, crack difficulty than a kind of coding of character larger.
4, the dicode receiving lines of this measure receives reliable:
Its reason is decoding integrated package fixed code in the present invention and conform to completely with the fixed code of radiating portion.And the variation code part receiving, signal code is 0 for the first time, and the code of signal is to suspend for the second time, and the twice change code sending with radiating portion definitely conforms to, and signal is that 0, the second signal is also to suspend for the first time.Follow the rule of this class encoding and decoding integrated package completely.Another very important reason is, what the decoding in receiving lines in the present invention realized is " tracking system ", that is to say receiving after first change code " 0 ", just automatically becomes required for the second time code " suspension ", twice receiving course is not disorderly, onside.
5, crack very difficult: mainly contain three reasons, the one, must have twice different code could realize decoding, just have output.Two is that twice required different code has sequential requirement, can not be disorderly, the 3rd major reason is, this twice different change codes be also necessary free requirement in the time of transmitting, because the integrated output of the coding adopting in the present invention is the transient state output type adopting, that is to say and receiving after signal, its output can only remain a transient state high position, after blink, will disappear.If criminal, does after correct code souning out for the first time, it is obviously very difficult wanting to feel out correct for the second time code within the very of short duration time again.Also be that criminal wants to crack the present invention must be by three passes: the one, must twice different dicode, the 2nd, also must there is sequential, the 3rd, also must be limited within the very short time and just can complete, therefore adopt " the barcode scanning instrument " of crime to crack and hardly may.From in a certain respect, higher than rolling code, because crack rolling code in theory, there is certain probability in this level of confidentiality, is that this probability is very low, very low, and the present invention is because exist the above-mentioned three elements that crack, and this to crack probability just lower.
6, circuit is reliable, and the one, circuit is simplified, and the 2nd, that bidirectional analog switch has possessed is low in energy consumption, speed fast, machinery-free contact, volume are little and the feature such as long service life, and the 3rd, the utilization of reception antenna, reduces ectocine, has increased receiving sensitivity.
7, produce easily, the one, equipment that need not be valuable and instrument, the 2nd, technology is simple, the 3rd, circuit simplify and element requirement used low, so can produce very high first-pass yield, very applicable minuscule-type-enterprise produces.
Brief description of the drawings
Fig. 1 is a kind of total measure figure of the dicode receiving circuit with timing.
In figure: 01, radio frequency reception demodulation part (as superregenerative reception demodulating unit, or beat reception demodulating unit); 02, decoding integrated circuit; 03, the fixed code of decoding integrated circuit; 04, the variation code of decoding integrated circuit; 05, the 4th of decoding integrated circuit the output; 06, the last output of decoding integrated circuit; 07, second of decoding integrated circuit the output; 08, become code control end; 09, interlock circuit; 10, performance element; 11, automatic transcoding units.
Fig. 2 is the practical circuit diagram of this measure relative section.
In figure: 01, radio frequency reception demodulation part (as superregenerative reception demodulating unit, or beat reception demodulating unit); 02, decoding integrated circuit; 03, the fixed code of decoding integrated circuit; 04, the variation code of decoding integrated circuit; 05, the 4th of decoding integrated circuit the output; 06, the last output of decoding integrated circuit; 07, second of decoding integrated circuit the output; 08, become code control end; 010, performance element triggers resistance; 011, first or gate diode; 012, second or gate diode; 013, not gate; 014, performance element the second clamp diode; 015, performance element the first clamp diode; 016, protective resistance; 017, the clamp diode of automatic transcoding units; 018, first bidirectional analog switch; 020, second bidirectional analog switch; 021, the source resistance of second bidirectional analog switch control end; 025, executive circuit.
Embodiment
Fig. 1 and Fig. 2 have described a kind of mode of concrete enforcement jointly.
One, select element: the integrated package of wherein decoding selects 2272, bidirectional analog switch is selected CD4066, and resistance adopts 1/8 watt.
Two, welding: press Fig. 2 welding.
Three, Detection and adjustment:
1, bidirectional analog switch working state is detected: the output of surveying each bidirectional analog switch with universal instrument, when decoding integrated package is not in the time receiving first signal, it is high-order that the output of first bidirectional analog switch should be, and second bidirectional analog switch is output as low level.
2, the Function detection to the integrated automatic changing code bit line of decoding: in the time launching for the first time signal, decoding integrated package energy reliable reception: the first output that universal instrument is surveyed decoding integrated package has high-order output.If now connect the integrated change code bit line of decoding with oscillographic hot junction, the signal of display screen can be become from fair line the phenomenon (representing to become code bit line is suspension) of flower screen.
3, detect that to connect the reception of twice signal correct: coding integrated package is being received after first signal, the secondary signal of fasting ejection very much, the high position output of the oriented rear class of integrated the second output of at this moment encoding.While having universal instrument to survey this, have Voltage-output, if while adopting oscilloscope, display screen has high-order reaction.
4, detect and receive whether sequential of signal: universal instrument or oscilloscope are received to the second integrated output of decoding, if first launch secondary signal, the integrated package second of now decoding is exported without high pressure, if there is high pressure, illustrates that bidirectional analog switch damages.
5, whether detection interlock circuit is reliable: survey the input of executive circuit with universal instrument, in the time that multidigit output has output simultaneously, no-voltage is answered in the input of executive circuit, otherwise the damage of explanation not gate, or clamp diode is bad.
Whether be non-interlocking type: first output of universal instrument or oscilloscope being received to decoding integrated package is observed with the second output, and when receiving after signal, within the time of short duration, signal can disappear if 6, detecting decoding integrated package, otherwise the integrated model that should alternate coding.
Claims (4)
1. a dicode receiving circuit with timing, is characterized in that: circuit is made up of jointly radio frequency reception demodulator circuit, decoding integrated package, performance element, interlock circuit, automatic transcoding units:
The output of radio frequency reception demodulator circuit connects the input of decoding integrated package, decoding integrated package has four outputs, first output become a yard control end and connect automatic transcoding units, and the 3rd output is that last output connects performance element, and second output is connected interlock circuit with the 4th output;
Automatically transcoding units is made up of two bidirectional analog switches: the control end of first bidirectional analog switch connects a change code control end after connecting protective resistance, the input end grounding line of first bidirectional analog switch, the control end of the output of first bidirectional analog switch and second bidirectional analog switch joins, resistance of control termination of second bidirectional analog switch is to power supply, the input end grounding of second bidirectional analog switch, the output of second bidirectional analog switch connects first of decoding integrated package and becomes code end;
Interlock circuit by or gate diode, not gate, clamp diode form;
The second output exports with the 4th the positive pole that is connected respectively or gate diode, or the negative pole of gate diode is connected together and connects the input of not gate, the output of not gate connects the positive pole of two clamp diodes, and one of them clamp diode is the control end that the positive pole of automatic transcoding units clamp diode is connected on first bidirectional analog switch; Another clamp diode is the input that the positive pole of performance element the second clamp diode connects executive circuit in performance element;
Executive circuit: the one end of triggering resistance connects last output, and the other end of circuits for triggering connects the input of executive circuit.
2. a kind of dicode receiving circuit with timing according to claim 1, is characterized in that: bidirectional analog switch is the integrated circuit CD4066 that there are 4 separate analogue switches inside.
3. a kind of dicode receiving circuit with timing according to claim 1, is characterized in that: decoding integrated package is non-locking type.
4. a kind of dicode receiving circuit with timing according to claim 1, is characterized in that: integrated form is made in this measure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420524195.5U CN204031152U (en) | 2014-09-13 | 2014-09-13 | A kind of dicode receiving circuit with timing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420524195.5U CN204031152U (en) | 2014-09-13 | 2014-09-13 | A kind of dicode receiving circuit with timing |
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| CN204031152U true CN204031152U (en) | 2014-12-17 |
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| CN201420524195.5U Expired - Fee Related CN204031152U (en) | 2014-09-13 | 2014-09-13 | A kind of dicode receiving circuit with timing |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108154849A (en) * | 2016-11-28 | 2018-06-12 | 伊格尼斯创新公司 | Pixel, reference circuit and time sequential technique |
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2014
- 2014-09-13 CN CN201420524195.5U patent/CN204031152U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108154849A (en) * | 2016-11-28 | 2018-06-12 | 伊格尼斯创新公司 | Pixel, reference circuit and time sequential technique |
| CN108154849B (en) * | 2016-11-28 | 2020-12-01 | 伊格尼斯创新公司 | Pixel, reference circuit and timing technique |
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