CN203911882U - Integration series hybrid operation SPWM generator - Google Patents
Integration series hybrid operation SPWM generator Download PDFInfo
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- CN203911882U CN203911882U CN201420348651.5U CN201420348651U CN203911882U CN 203911882 U CN203911882 U CN 203911882U CN 201420348651 U CN201420348651 U CN 201420348651U CN 203911882 U CN203911882 U CN 203911882U
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Abstract
An integration series hybrid operation SPWM generator is provided. The SPWM generator can be applied to the fields of a photovoltaic inverter, a frequency conversion power supply, a motor speed regulation control and a UPS power supply and the like. The SPWM generator is composed of a series hybrid operation circuit, an address generator circuit, a virtual ROM circuit, a dead zone adjusting circuit, a waveform synthesis circuit, a carrier frequency generator circuit, a work state arranging circuit, and a clock generator circuit. After the integration series hybrid operation SPWM generator provide by the utility model is powered on, sine modulated wave data are computed in the chip through a mathematic method and stored in the virtual ROM circuit instantiated by the RAM, used for generating SPWM signals and integrated on a special control chip, without a ROM . The area of the chip is effectively decreased and cost and power consumption of the chip are reduced.
Description
Technical field
The utility model relates to microelectric technique, power electronic technology, inverter, variable frequency power supply, motor driving and technical field of new energies, particularly a kind of structure of Sine Wave Pulse Width Modulation SPWM signal generator.
Background technology
Sinusoidal pulse width modulation (SPWM) is a kind of energy conversion technique based on area equivalent theory, can be by DC power supply, as solar cell, convert sinusoidal wave single-phase or three-phase alternating current to, be used for realizing solar inverter, variable frequency power supply, uninterruption power source, the driving of high-performance motor and speed governing, Design of Stepper Motor Subdivision control etc., in fields such as aviation, navigation, power electronics, new forms of energy application, there is application very widely.
Traditional SPWM generator is divided into analog circuit mode and digital control approach, wherein analog circuit is to produce sine wave and triangular wave with simulative generator, utilize analog comparator to synthesize SPWM signal, this method circuit structure is simple, but it is low to exist control precision, the shortcomings such as temperature drift is large, poor anti jamming capability.And digital control SPWM technology can overcome these shortcomings effectively, by digital circuit, there is programmable feature, become very soon technology main flow, and on market, also occurred that some application-specific integrated circuit (ASIC)s can supply system designer select.But this digital control SPWM generator adopts look-up table to realize mostly, in a jumbo ROM, store the sinusoidal wave data of one-period, design for SPWM special integrated circuit, ROM is arranged in to chip internal, can increase chip area and power consumption, thereby increased the cost of chip, ROM has been arranged in to the cost that chip exterior also can increase the design of SPWM circuit system.
Summary of the invention
The utility model object is to overcome prior art above shortcomings, and a kind of integrated progression hybrid operation SPWM generator without ROM memory is provided.Realize a kind of comparison method SPWM generator that does not need ROM.
A kind of integrated progression hybrid operation SPWM generator that the utility model provides comprises: clock generator circuit, progression mixed arichmetic circuitry, virtual ROM circuit, address generator circuit, carrier generator circuit, operating state arrange circuit, dead zone adjusting circuit and waveform combiner circuit.
The input of clock generator circuit is connected with external timing signal input, and four outputs of clock generator circuit are connected with progression mixed arichmetic circuitry, address generator circuit, carrier generator circuit and the input end of clock that operating state arranges circuit respectively.
The input of progression mixed arichmetic circuitry has two, the output that with clock generator circuit and operating state circuit is set is respectively connected, the output of progression mixed arichmetic circuitry has two, is connected respectively with input of virtual ROM circuit and an input of address generator circuit; The input of address generator circuit has three, and an output that with progression mixed arichmetic circuitry, clock generator circuit and operating state circuit is set is respectively connected, and the output of address generator circuit is linked an input of virtual ROM circuit; The output of virtual ROM circuit is connected with an input of dead zone adjusting circuit; Dead zone adjusting circuit has two inputs, and an output that with virtual ROM circuit and operating state circuit is set is respectively connected, and dead zone adjusting circuit output is connected with waveform combiner circuit.
Carrier generator circuit has two inputs, and an output that with clock generator circuit and operating state circuit is set is respectively connected, and its output is connected with an input of waveform combiner circuit; Waveform combiner circuit has three inputs, an output that with carrier generator circuit, dead zone adjusting circuit and operating state circuit is set is respectively connected, waveform combiner circuit output has two, and an input that with operating state circuit is set is respectively connected with outside SPWM signal output part.
Operating state arranges five inputs of circuit, enables respectively, external data enables, an output of clock generator and waveform combiner circuit is connected with external data line, outside gating; Five outputs that operating state arranges circuit are connected with an input of progression mixed arichmetic circuitry, carrier generator circuit, address generator circuit, dead zone adjusting circuit and waveform combiner circuit respectively, and another output is connected with outside.
At the disclosed a kind of integrated progression hybrid operation SPWM generator of the utility model, utilize virtual ROM storage sine waveform data.Described virtual ROM circuit is the ROM memory space that utilizes RAM exampleization to generate, and in described integrated progression hybrid operation SPWM generator, as actual ROM circuit, uses, and can utilize like this RAM simple in structure to replace ROM.
Progression mixed arichmetic circuitry takes advantage of circuit, second times to take advantage of circuit, the 3rd times to take advantage of circuit, the first summing circuit, the second summing circuit, the 3rd summing circuit, the 4th summing circuit, the 5th summing circuit, the 6th summing circuit, symmetry operation circuit and address count pulse generator the electric circuit constitute by control circuit, scaling circuit, the first Power raising circuit, the second Power raising circuit, the 3rd Power raising circuit, first times.The input of control circuit is connected with an output of clock generator circuit, and its output has eight, and the first output ctr1 is connected with an input of scaling circuit; The second output ctr2 is connected with an input of the first Power raising circuit; The 3rd output ctr3 takes advantage of an input of circuit to be connected with an input of the second Power raising circuit with first times simultaneously; The 4th output ctr4 simultaneously takes advantage of an input of circuit and the first summing circuit to be connected with the 3rd Power raising circuit, second times; The 5th output ctr5 takes advantage of an input of circuit to be connected with the second summing circuit, the 3rd summing circuit with the 3rd times simultaneously; The 6th output ctr6 is connected with an input of the 4th summing circuit; The 7th output ctr7 is connected with an input of the 5th summing circuit; The 8th output ctr8 is connected with an input of the 6th summing circuit.Control circuit generates eight tunnel control signals under clock control, controls all power and takes advantage of, doubly takes advantage of the calculating process with summing circuit.The input of scaling circuit has two, is connected respectively with output of clock generator circuit and the output ctr1 of control circuit, and its output is connected with the first Power raising circuit.The first Power raising circuit has three inputs, be connected with output of the output of scaling circuit, clock generator circuit and the output ctr2 of control circuit respectively, its output has two, one of them output takes advantage of an input of circuit to be connected with first times, and another output is connected with an input of the second Power raising circuit and the 3rd Power raising circuit simultaneously.The second Power raising circuit has three inputs, be connected with output of the output of the first Power raising circuit, clock generator circuit and the output ctr3 of control circuit respectively, its output has two, takes advantage of an output of circuit to be connected respectively with the 3rd Power raising circuit with second times.The 3rd Power raising circuit has four inputs, respectively with an output of the first Power raising circuit, output of an output of the second Power raising circuit, clock generator circuit and the output ctr4 of control circuit are connected, its output takes advantage of an input of circuit to be connected with the 3rd times.Take advantage of circuit to have three inputs for first times, be connected with an output, the output of the first Power raising circuit and the output ctr3 of control circuit of clock generator circuit respectively.Take advantage of circuit to have three inputs for second times, be connected with an output, the output of the second Power raising circuit and the output ctr4 of control circuit of clock generator circuit respectively.Take advantage of circuit to have three inputs for the 3rd times, be connected respectively with an output, the output of the 3rd Power raising circuit and the output ctr5 of control circuit of clock generator circuit, its output is connected with an input of the 6th summing circuit.The first summing circuit has three inputs, is connected respectively with the output ctr4 of an output of clock generator circuit, first times of output of taking advantage of circuit and control circuit, and its output is connected with an input of the 3rd summing circuit.The second summing circuit has three inputs, is connected respectively with the output ctr5 of an output of clock generator circuit, second times of output of taking advantage of circuit and control circuit, and its output is connected with an input of the 4th summing circuit.The 3rd summing circuit has three inputs, is connected respectively with an output, the output of the first summing circuit and the output ctr5 of control circuit of clock generator circuit, and its output is connected with an input of the 5th summing circuit.The 4th summing circuit has three inputs, is connected respectively with an output, the output of the second summing circuit and the output ctr6 of control circuit of clock generator circuit, and its output is connected with an input of the 5th summing circuit.The 5th summing circuit has four inputs, be connected with an output, the output of the 3rd summing circuit, the output ctr7 of the output of the 4th summing circuit and control circuit of clock generator circuit respectively, its output is connected with an input of the 6th summing circuit.The 6th summing circuit has four inputs, respectively with an output of clock generator circuit, the output of the 5th summing circuit, the 3rd times take advantage of the output of circuit and the output ctr8 of control circuit to be connected, its output is connected with an input of symmetry operation circuit.Symmetry operation circuit has two inputs, be connected with the output of the 6th summing circuit with an output of clock generator circuit respectively, its output has two, is connected respectively with an input of virtual ROM circuit with the input of address count pulse generator.The output of address count pulse generator is connected with an input of address generator circuit.
Waveform combiner circuit is by sinusoidal wave testing circuit, carrier detecting circuit, comparator, gating circuit and form with door.The sinusoidal wave input of testing circuit and the output of dead zone adjusting circuit are connected, and the output of sinusoidal wave testing circuit has two, and one of them output is connected with the negative input end of comparator, another output be connected with an input of door.
What sinusoidal wave testing circuit outputed to comparator is sine wave signal, through comparator and carrier signal, synthesize SPWM output signal, sinusoidal wave testing circuit output to door be status signal, when sine wave signal being detected, be high level when normal, otherwise be low level; The input of carrier detecting circuit is connected with the output of carrier generator circuit, carrier detecting circuit output has two, respectively with comparator be connected with the input of door, what output to comparator is carrier signal, through comparator and sine wave signal, synthesize SPWM output signal, carrier detecting circuit output to door be status signal, when carrier signal being detected, be high level when normal, otherwise be low level; Two inputs of AND circuit are connected with the output of sinusoidal wave testing circuit and the output of carrier detecting circuit respectively, output is connected with the input that operating state arranges circuit, when the output of sinusoidal wave testing circuit and the output of carrier detecting circuit are all high level, the output of AND circuit is high level, shows that progression mixed arichmetic circuitry is working properly; Two inputs of gating circuit connect respectively the output that comparator and operating state arrange circuit, and the output of gating circuit is linked outside SPWM signal output part.
Described operating state arranges circuit and is comprised of strobe register, data register, flag register, period register, maximum address register, carrier wave register and dead band adjustment register; Two inputs of strobe register are connected with data wire with outside gating enable signal respectively, and four outputs of strobe register are connected with an input of period register, maximum address register, carrier wave register and dead band adjustment register respectively; Two inputs of data register are connected with data wire with outside data enable signal respectively, and the output of data register is connected with an input of period register, maximum address register, carrier wave register and dead band adjustment register simultaneously; Two inputs of flag register are connected with the marking signal from comparator circuit with data register respectively, and two outputs of flag register are connected with internal comparator output control signal with outside id signal respectively; Register is adjusted in period register, maximum address register, carrier wave register and dead band a gating signal, data write signal and clock signal input terminal, and respectively with the output of strobe register, an output of the output of data register and clock generator be connected; The output of period register is connected with an input of progression mixed arichmetic circuitry; Maximum address register output is connected with an input of address generator circuit; The output of carrier wave register is connected with an input of carrier generator circuit; Dead band is adjusted register output and is connected with an input of dead zone adjusting circuit.
Operating state arranges circuit, and gating externally enables, under the control with data enable signal, by data wire, progression mixed arichmetic circuitry, carrier generator circuit, address generator circuit and dead zone adjusting circuit to be arranged.Operating state arranges the output that circuit is linked waveform combiner circuit, is used for controlling the break-make of SPWM output signal.
The integrated progression hybrid operation SPWM generator the utility model proposes, adopt the method for virtual ROM, one group of sine waveform data is placed in the RAM of low cost of manufacture, can solve current digital control SPWM generator needs the problem of large capacity ROM, can effectively reduce the area of chip, the compact that improves SPWM control system, reduces costs.
The disclosed integrated progression hybrid operation SPWM generator of the utility model, adopt CMOS technological design to become special-purpose integrated circuit (IC) chip, compare with the scheme of tradition based on look-up table design SPWM generator, do not need ROM memory, have simple in structure, chip area is little, low in energy consumption, functional reliability is high, chip and application system cost are low, the feature such as easy to utilize is a kind of new technology with development prospect.
advantage of the present utility model and good effect:
The integrated progression hybrid operation SPWM generator that the utility model provides is the data of sinusoidal wave calibration curve, stores in the virtual ROM memory of system RAM resource, and recycling look-up table generates SPWM waveform signal.Therefore, the circuit that the utility model provides, does not need the ROM memory that chip area is large, cost is high, is integrated in special integrated circuit, can effectively reduce chip area, reduces cost and the power consumption of chip.The control circuit that can be used for photovoltaic DC-to-AC converter, variable frequency power supply, uninterrupted power supply etc., has great application prospect.
Accompanying drawing explanation
Fig. 1 is a kind of integrated progression hybrid operation SPWM generator architecture figure the utility model proposes;
Fig. 2 is the structured flowchart of the progression mixed arichmetic circuitry 1 that the utility model proposes;
Fig. 3 is the structured flowchart of the waveform combiner circuit 5 that the utility model proposes;
Fig. 4 is the structured flowchart that the operating state that the utility model proposes arranges circuit 7;
Fig. 5 is the input/output signal oscillogram of control circuit 24 in the progression hybrid circuit the utility model proposes.
Embodiment
embodiment 1, a kind of integrated progression hybrid operation SPWM generator
As shown in Figure 1, a kind of integrated progression hybrid operation SPWM generator that the utility model provides, comprising:
Clock generator circuit 8, progression mixed arichmetic circuitry 1, address generator circuit 2, virtual ROM circuit 3, dead zone adjusting circuit 4, waveform combiner circuit 5, carrier generator circuit 6 and operating state arrange circuit 7; The input of clock generator circuit 8 is connected with external clock input, and its output arranges circuit 7 with progression mixed arichmetic circuitry 1, address generator circuit 2, carrier generator circuit 5 and operating state respectively and is connected; The input of progression mixed arichmetic circuitry 1 has two, arranges 7 be respectively connected with clock generator circuit 8 and operating state, and its output has two, is connected respectively with input of virtual ROM circuit 3 and an input of address generator circuit 2; The input of address generator circuit 2 has three, and an output that with progression mixed arichmetic circuitry 1, clock generator circuit 8 and operating state circuit 7 is set is respectively connected, and its output is linked an input of virtual ROM circuit 3; The output of virtual ROM circuit 3 is connected with an input of dead zone adjusting circuit 4; Dead zone adjusting circuit 4 has two inputs, and an output that with virtual ROM circuit 3 and operating state circuit 7 is set is respectively connected, and its output is connected with waveform combiner circuit 5; Carrier generator circuit 6 has two inputs, and an output that with clock generator circuit 1 and operating state circuit 7 is set is respectively connected, and its output is connected with an input of waveform combiner circuit 5; Waveform combiner circuit 5 has three inputs, an output that with carrier generator circuit 6, dead zone adjusting circuit 4 and operating state circuit 7 is set is respectively connected, its output has two, and an input that with operating state circuit 7 is set is respectively connected with outside SPWM signal output part; Operating state arranges circuit 7 five inputs, enables respectively, external data enables, an output of clock generator circuit 8 and waveform combiner circuit 5 is connected with external data line, outside gating; Operating state arranges circuit 7 five outputs, is connected respectively with an input of progression mixed arichmetic circuitry 1, carrier generator circuit 5, address generator circuit 2, dead zone adjusting circuit 4 and waveform combiner circuit 5.
Described virtual ROM circuit 3 is ROM memory spaces that exampleization generates in system RAM circuit, in the disclosed a kind of integrated progression hybrid operation SPWM generator of the utility model, utilizes virtual ROM storage sine waveform data.After system powers on, the sine waveform data of progression mixed arichmetic circuitry 1 direct generation standard, and the address signal producing according to address generator circuit 2, sinusoidal wave data is write in virtual ROM circuit 3, progression mixed arichmetic circuitry 1 is by the holding state in low power consumption afterwards.
embodiment 2, progression mixed arichmetic circuitry
Utilize the progression mixed arichmetic circuitry shown in Fig. 2 to realize first four of Maclaurin series of SIN function, described progression mixed arichmetic circuitry 1 is by control circuit 24, scaling circuit 9, the first Power raising circuit 10, the second Power raising circuit 22, the 3rd Power raising circuit 23, take advantage of circuit 11 for first times, take advantage of circuit 20 for second times, take advantage of circuit 21 for the 3rd times, the first summing circuit 12, the second summing circuit 19, the 3rd summing circuit 13, the 4th summing circuit 14, the 5th summing circuit 15, the 6th summing circuit 16, symmetry operation circuit 17 and address count pulse generator circuit 18 form.
The input of control circuit 24 is connected with an output of clock generator circuit 8, and its output has eight, and the first output ctr1 is connected with an input of scaling circuit 9; The second output ctr2 is connected with an input of the first Power raising circuit 10; The 3rd output ctr3 takes advantage of an input of circuit 11 to be connected with an input of the second Power raising circuit 22 with first times simultaneously; The 4th output ctr4 simultaneously takes advantage of an input of circuit 20 and the first summing circuit 12 to be connected with the 3rd Power raising circuit 23, second times; The 5th output ctr5 takes advantage of an input of circuit 21 to be connected with the second summing circuit 19, the 3rd summing circuit 13 with the 3rd times simultaneously; The 6th output ctr6 is connected with an input of the 4th summing circuit 14; The 7th output ctr7 is connected with an input of the 5th summing circuit 15; The 8th output ctr8 is connected with an input of the 6th summing circuit 16.Control circuit 24 generates eight tunnel control signals under clock control, and control all power and take advantage of, doubly take advantage of the calculating process with summing circuit, as shown in Figure 5, be the input/output signal waveform of control circuit 24.The input of scaling circuit 9 has two, is connected respectively with output of clock generator circuit 8 and the output ctr1 of control circuit 24, and its output is connected with the first Power raising circuit 10.The first Power raising circuit 10 has three inputs, be connected with output of the output of scaling circuit 9, clock generator circuit 8 and the output ctr2 of control circuit 24 respectively, its output has two, one of them output takes advantage of an input of circuit 11 to be connected with first times, and another output is connected with an input of the second Power raising circuit 22 and the 3rd Power raising circuit 23 simultaneously.The second Power raising circuit 22 has three inputs, be connected with output of the output of the first Power raising circuit 10, clock generator circuit 8 and the output ctr3 of control circuit 24 respectively, its output has two, takes advantage of an output of circuit 20 to be connected respectively with the 3rd Power raising circuit 23 with second times.The 3rd Power raising circuit 23 has four inputs, respectively with an output of the first Power raising circuit 10, output of an output of the second Power raising circuit 22, clock generator circuit 8 and the output ctr4 of control circuit 24 are connected, its output takes advantage of an input of circuit 21 to be connected with the 3rd times.Take advantage of circuit 11 to have three inputs for first times, be connected with an output, the output of the first Power raising circuit 10 and the output ctr3 of control circuit 24 of clock generator circuit 8 respectively.Take advantage of circuit 20 to have three inputs for second times, be connected with an output, the output of the second Power raising circuit 22 and the output ctr4 of control circuit 24 of clock generator circuit 8 respectively.Take advantage of circuit 21 to have three inputs for the 3rd times, be connected respectively with an output, the output of the 3rd Power raising circuit 23 and the output ctr5 of control circuit 24 of clock generator circuit 8, its output is connected with an input of the 6th summing circuit 16.The first summing circuit 12 has three inputs, is connected respectively with the output ctr4 of an output of clock generator circuit 8, first times of output of taking advantage of circuit 11 and control circuit 24, and its output is connected with an input of the 3rd summing circuit 13.The second summing circuit 19 has three inputs, is connected respectively with the output ctr5 of an output of clock generator circuit 8, second times of output of taking advantage of circuit 20 and control circuit 24, and its output is connected with an input of the 4th summing circuit 14.The 3rd summing circuit 13 has three inputs, is connected respectively with an output, the output of the first summing circuit 12 and the output ctr5 of control circuit 24 of clock generator circuit 8, and its output is connected with an input of the 5th summing circuit 15.The 4th summing circuit 14 has three inputs, is connected respectively with an output, the output of the second summing circuit 19 and the output ctr6 of control circuit 24 of clock generator circuit 8, and its output is connected with an input of the 5th summing circuit 15.The 5th summing circuit 15 has four inputs, be connected with the output ctr7 of an output, the output of the 3rd summing circuit 13, the output of the 4th summing circuit 14 and the control circuit 24 of clock generator circuit 8 respectively, its output is connected with an input of the 6th summing circuit 16.The 6th summing circuit 16 has four inputs, respectively with an output of clock generator circuit 8, the output of the 5th summing circuit 15, the 3rd times take advantage of the output of circuit 21 and the output ctr8 of control circuit 24 to be connected, its output is connected with an input of symmetry operation circuit 17.Symmetry operation circuit 17 has two inputs, be connected with the output of the 6th summing circuit 16 with an output of clock generator circuit 8 respectively, its output has two, is connected respectively with an input of virtual ROM circuit 3 with the input of address count pulse generator 18.The output of address count pulse generator 18 is connected with an input of address generator circuit.
embodiment 3, waveform combiner circuit
As shown in Figure 3, described waveform combiner circuit 5 is by sinusoidal wave testing circuit 25, carrier detecting circuit 28, comparator 26, gating circuit 27 with form with door 29.Its function is to compare by offset of sinusoidal ripple signal and carrier signal, exports the synthetic of SPWM ripple.
The input of described sinusoidal wave testing circuit 25 is connected with the output of dead zone adjusting circuit 4, and its output has two, and one of them output is connected with the negative input end of comparator 26, another output be connected with an input of door 29.The input of carrier detecting circuit 28 is connected with the output of carrier generator circuit 6, and its output has two, and one of them output is connected with the positive input terminal of comparator 26, another output be connected with an input of door 29.Comparator has two inputs, is connected respectively with an output of sinusoidal wave testing circuit 25 and carrier detecting circuit 28, and its output is connected with an input of gating circuit 27.There are two inputs with door 29, be connected with an output of sinusoidal wave testing circuit 25 and carrier detecting circuit 28 respectively, its output is connected with the input that operating state arranges circuit 7, when two inputs with door 29 are all high level, with door output high level, show that sine-wave generator circuit and carrier generator circuit working are normal.Gating circuit 27 has two inputs, and an output that with comparator 26 and operating state circuit 7 is set is respectively connected, and its output is connected with outside, and output SPWM signal is given circuit below.
embodiment 4, operating state arrange circuit
As shown in Figure 4, described operating state arranges circuit 7 and by strobe register 36, data register 35, flag register 34, period register 30, maximum address register 31, carrier wave register 32 and dead band, adjusts register 33 and form.Operating state arranges circuit 7 and completes initialization, setting and the Working Status Monitoring to whole circuit
Described strobe register 36 has two inputs, be connected with data wire with outside gating enable signal respectively, its output has four, is connected respectively with an input of period register 30, maximum address register 31, carrier wave register 32 and dead band adjustment register 33.Data register 35 has two inputs, be connected with data wire with outside data enable signal respectively, its output has one, is connected with an input of period register 30, maximum address register 31, carrier wave register 32 and dead band adjustment register 33 simultaneously.Flag register 34 has two inputs, is connected respectively with data register 35 with the marking signal from waveform combiner circuit 5, and its output also has two, is connected respectively with an output of outside id signal and waveform combiner circuit 5.Register 33 is adjusted in period register 30, maximum address register 31, carrier wave register 32 and dead band a gating signal, data write signal and clock signal, respectively with the output of strobe register 36, an output of the output of data register 35 and clock generator circuit 8 be connected.The output of period register 30 is connected with an input of progression mixed arichmetic circuitry 1.The output of maximum address register 31 is connected with an input of address generator circuit 2.The output of carrier wave register 32 is connected with an input of carrier generator circuit 6; The output of register 33 is adjusted in dead band and an input of dead zone adjusting circuit 4 is connected.Operating state arranges circuit 7 gating externally and enables, under the control with data enable signal, by data wire, progression mixed arichmetic circuitry 1, carrier generator circuit 6, address generator circuit 2 and dead zone adjusting circuit 4 to be arranged.The output that it is connected to waveform combiner circuit 5, is used for controlling the break-make of SPWM output signal.
Claims (5)
1. an integrated progression hybrid operation SPWM generator, is characterized in that this integrated progression hybrid operation SPWM generator comprises: clock generator circuit, progression mixed arichmetic circuitry, virtual ROM circuit, address generator circuit, carrier generator circuit, operating state arrange circuit, dead zone adjusting circuit and waveform combiner circuit;
The input of clock generator circuit is connected with external timing signal input, and four outputs of clock generator circuit are connected with progression mixed arichmetic circuitry, carrier generator circuit, address generator circuit and the input end of clock that operating state arranges circuit respectively;
The input of progression mixed arichmetic circuitry has two, and the output that with clock generator circuit and operating state circuit is set is respectively connected; The output of progression mixed arichmetic circuitry has two, is connected respectively with input of virtual ROM circuit and an input of address generator circuit; The output that other two inputs of address generator circuit arrange circuit with clock generator circuit and operating state is respectively connected, and the output of address generator circuit is linked an input of virtual ROM circuit; The output of virtual ROM circuit is connected with an input of dead zone adjusting circuit; Another one input and the operating state of dead zone adjusting circuit arrange circuit and are connected, and dead zone adjusting circuit output is connected with waveform combiner circuit;
Carrier generator circuit has two inputs, and an output that with clock generator circuit and operating state circuit is set is respectively connected, and the output of carrier generator circuit is connected with an input of waveform combiner circuit; The output that other two inputs of waveform combiner circuit arrange circuit with dead zone adjusting circuit and operating state is respectively connected, waveform combiner circuit output has two, one of them output is connected with the input that operating state arranges circuit, and another output is linked outside SPWM signal output part;
Operating state arranges circuit five inputs, in five inputs, there are three inputs to enable to be connected with data enable end with outside data wire, gating respectively, other two inputs are connected with an output of waveform combiner circuit and clock generator circuit respectively, five outputs that operating state arranges circuit are connected with an input of progression mixed arichmetic circuitry, carrier generator circuit, address generator circuit, dead zone adjusting circuit and waveform combiner circuit respectively, and another output is connected with outside.
2. integrated progression hybrid operation SPWM generator according to claim 1, it is characterized in that, described virtual ROM circuit is the ROM memory space that utilizes RAM exampleization to generate, and in described integrated progression hybrid operation SPWM generator, as actual ROM circuit, uses.
3. integrated progression hybrid operation SPWM generator according to claim 1, is characterized in that, described waveform combiner circuit is by sinusoidal wave testing circuit, carrier detecting circuit, comparator, gating circuit and form with door;
The sinusoidal wave input of testing circuit and the output of dead zone adjusting circuit are connected, and the output of sinusoidal wave testing circuit has two, respectively with comparator be connected with the input of door; The input of carrier detecting circuit is connected with the output of carrier generator circuit, and carrier detecting circuit output has two, respectively with comparator be connected with the input of door; Two inputs of AND circuit are connected with the output of sinusoidal wave testing circuit and the output of carrier detecting circuit respectively, and output is connected with the input that operating state arranges circuit; Two inputs of gating circuit connect respectively the output that comparator and operating state arrange circuit, and the output of gating circuit is linked outside SPWM signal output part.
4. integrated progression hybrid operation SPWM generator according to claim 1, it is characterized in that, described operating state arranges circuit and is comprised of strobe register, data register, flag register, period register, maximum address register, carrier wave register and dead band adjustment register; Two inputs of strobe register are connected with data wire with outside gating enable signal respectively, and four outputs of strobe register are connected with an input of period register, maximum address register, carrier wave register and dead band adjustment register respectively; Two inputs of data register are connected with data wire with outside data enable signal respectively, and the output of data register is connected with an input of period register, maximum address register, carrier wave register and dead band adjustment register simultaneously; Two inputs of flag register are connected with the marking signal from comparator circuit with data register respectively, and two outputs of flag register are connected with internal comparator output control signal with outside id signal respectively; Register is adjusted in period register, maximum address register, carrier wave register and dead band a gating signal, data write signal and clock signal input terminal, and respectively with the output of strobe register, an output of the output of data register and clock generator be connected; The output of period register is connected with an input of progression mixed arichmetic circuitry; Maximum address register output is connected with an input of address generator circuit; The output of carrier wave register is connected with an input of carrier generator circuit; Dead band is adjusted register output and is connected with an input of dead zone adjusting circuit.
5. integrated progression hybrid operation SPWM generator according to claim 1, it is characterized in that, described progression mixed arichmetic circuitry takes advantage of circuit, second times to take advantage of circuit, the 3rd times to take advantage of circuit, the first summing circuit, the second summing circuit, the 3rd summing circuit, the 4th summing circuit, the 5th summing circuit, the 6th summing circuit, symmetry operation circuit and address count pulse generator the electric circuit constitute by control circuit, scaling circuit, the first Power raising circuit, the second Power raising circuit, the 3rd Power raising circuit, first times; The input of control circuit is connected with an output of clock generator circuit, and its output has eight, and the first output ctr1 is connected with an input of scaling circuit; The second output ctr2 is connected with an input of the first Power raising circuit; The 3rd output ctr3 takes advantage of an input of circuit to be connected with an input of the second Power raising circuit with first times simultaneously; The 4th output ctr4 simultaneously takes advantage of an input of circuit and the first summing circuit to be connected with the 3rd Power raising circuit, second times; The 5th output ctr5 takes advantage of an input of circuit to be connected with the second summing circuit, the 3rd summing circuit with the 3rd times simultaneously; The 6th output ctr6 is connected with an input of the 4th summing circuit; The 7th output ctr7 is connected with an input of the 5th summing circuit; The 8th output ctr8 is connected with an input of the 6th summing circuit, and control circuit generates eight tunnel control signals under clock control, controls all power and takes advantage of, doubly takes advantage of the calculating process with summing circuit; The input of scaling circuit has two, is connected respectively with output of clock generator circuit and the output ctr1 of control circuit, and its output is connected with the first Power raising circuit; The first Power raising circuit has three inputs, be connected with output of the output of scaling circuit, clock generator circuit and the output ctr2 of control circuit respectively, its output has two, one of them output takes advantage of an input of circuit to be connected with first times, and another output is connected with an input of the second Power raising circuit and the 3rd Power raising circuit simultaneously; The second Power raising circuit has three inputs, be connected with output of the output of the first Power raising circuit, clock generator circuit and the output ctr3 of control circuit respectively, its output has two, takes advantage of an output of circuit to be connected respectively with the 3rd Power raising circuit with second times; The 3rd Power raising circuit has four inputs, respectively with an output of the first Power raising circuit, output of an output of the second Power raising circuit, clock generator circuit and the output ctr4 of control circuit are connected, its output takes advantage of an input of circuit to be connected with the 3rd times; Take advantage of circuit to have three inputs for first times, be connected with an output, the output of the first Power raising circuit and the output ctr3 of control circuit of clock generator circuit respectively; Take advantage of circuit to have three inputs for second times, be connected with an output, the output of the second Power raising circuit and the output ctr4 of control circuit of clock generator circuit respectively; Take advantage of circuit to have three inputs for the 3rd times, be connected respectively with an output, the output of the 3rd Power raising circuit and the output ctr5 of control circuit of clock generator circuit, its output is connected with an input of the 6th summing circuit; The first summing circuit has three inputs, is connected respectively with the output ctr4 of an output of clock generator circuit, first times of output of taking advantage of circuit and control circuit, and its output is connected with an input of the 3rd summing circuit; The second summing circuit has three inputs, is connected respectively with the output ctr5 of an output of clock generator circuit, second times of output of taking advantage of circuit and control circuit, and its output is connected with an input of the 4th summing circuit; The 3rd summing circuit has three inputs, is connected respectively with an output, the output of the first summing circuit and the output ctr5 of control circuit of clock generator circuit, and its output is connected with an input of the 5th summing circuit; The 4th summing circuit has three inputs, is connected respectively with an output, the output of the second summing circuit and the output ctr6 of control circuit of clock generator circuit, and its output is connected with an input of the 5th summing circuit; The 5th summing circuit has four inputs, be connected with an output, the output of the 3rd summing circuit, the output ctr7 of the output of the 4th summing circuit and control circuit of clock generator circuit respectively, its output is connected with an input of the 6th summing circuit; The 6th summing circuit has four inputs, respectively with an output of clock generator circuit, the output of the 5th summing circuit, the 3rd times take advantage of the output of circuit and the output ctr8 of control circuit to be connected, its output is connected with an input of symmetry operation circuit; Symmetry operation circuit has two inputs, be connected with the output of the 6th summing circuit with an output of clock generator circuit respectively, its output has two, is connected respectively with an input of virtual ROM circuit with the input of address count pulse generator; The output of address count pulse generator is connected with an input of address generator circuit.
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| CN201420348651.5U CN203911882U (en) | 2014-06-27 | 2014-06-27 | Integration series hybrid operation SPWM generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038187A (en) * | 2014-06-27 | 2014-09-10 | 南开大学 | Integration series hybrid operation SPWM generator and achievement method |
| CN113098454A (en) * | 2021-03-31 | 2021-07-09 | 上海电气风电集团股份有限公司 | PWM signal generation method, single-phase PWM signal generation module and three-phase PWM signal generation module |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038187A (en) * | 2014-06-27 | 2014-09-10 | 南开大学 | Integration series hybrid operation SPWM generator and achievement method |
| CN104038187B (en) * | 2014-06-27 | 2016-06-29 | 南开大学 | A kind of integrated progression hybrid operation SPWM generator and realize method |
| CN113098454A (en) * | 2021-03-31 | 2021-07-09 | 上海电气风电集团股份有限公司 | PWM signal generation method, single-phase PWM signal generation module and three-phase PWM signal generation module |
| CN113098454B (en) * | 2021-03-31 | 2023-03-31 | 上海电气风电集团股份有限公司 | PWM signal generation method, single-phase PWM signal generation module and three-phase PWM signal generation module |
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