CN104202023A

CN104202023A - Unipolarity sinusoidal pulse width modulation (SPWM) pulse signal achieving method based on field programmable gate array (FPGA)

Info

Publication number: CN104202023A
Application number: CN201410413772.8A
Authority: CN
Inventors: 杨帆; 盛波
Original assignee: Shanghai University of Electric Power
Current assignee: Shanghai University of Electric Power; University of Shanghai for Science and Technology
Priority date: 2014-08-21
Filing date: 2014-08-21
Publication date: 2014-12-10
Anticipated expiration: 2034-08-21
Also published as: CN104202023B

Abstract

The invention relates to a unipolarity sinusoidal pulse width modulation (SPWM) pulse signal achieving method based on a field programmable gate array (FPGA). A system clock control module provides a work clock for a triangle carrier signal generator and a sinusoidal modulation wave signal generator. The sinusoidal modulation wave signal generator outputs and generates sinusoidal wave signals. The system clock control module adjusts the frequency of the work clock and controls the frequency of the sinusoidal wave signals. Anode triangle carrier and cathode triangle carrier generated by the triangle carrier signal generator utilize sinusoidal wave signals as gating signals, and finally unipolarity triangle carrier signals are generated and output. The generated unipolarity carrier triangle carrier signals and the sinusoidal wave signals are utilized as input signals of a comparison negation module, the comparison negation module outputs the signals and enters a dead zone delaying control module, and the dead zone delaying control module outputs the SPWM pulse signals. The SPWM pulse signals generated by the method have the advantages of high accuracy, high speed, high stability, online programmable algorithm modification and the like.

Description

A kind of Unipolar SPWM pulse signal implementation method based on FPGA

Technical field

The present invention relates to a kind of control technology of single-phase full bridge formula inverter circuit, particularly a kind of Unipolar SPWM pulse signal implementation method based on FPGA.

Background technology

SPWM(Using Sinusoidal Pulse Width Modulation) modulation be a kind of PWM control technology of comparative maturity; It is widely used in motor, photovoltaic inversion dispatch control system.The mode that produces at present SPWM pulse signal has a lot; For example utilize analog circuit to carrier wave and modulating wave comparison, obtain SPWM signal; Utilize special SPWM generator integrated circuit, as SLE4520, SA4828 etc. produce SPWM signal; Utilize TMS2812, the DSP such as 28335 to generate SPWM ripple.But these methods all have certain limitation.Utilize cost and the complexity of special SPWM generator integrated circuit all higher, and flexibility is very low; And utilize DSP can only generate 6 tunnels or 12 road PWM waveforms.

Along with the extensive use of digital integration circuit, FPGA(field programmable gate array) become the first-selection of novel digital integrated chip exploitation.FPGA has that the construction cycle is short, power consumption is low, integrated level advantages of higher.The appearance of FPGA has overcome that special asic chip is subject to that clock affects and the shortcoming such as the construction cycle is long, is widely used in industrial each field.

Summary of the invention

The SPWM Using Sinusoidal Pulse Width Modulation method in present PWM control technology that the present invention be directed to has circumscribed problem, has proposed a kind of Unipolar SPWM pulse signal implementation method based on FPGA, can realize high accuracy, high stability pulse signal.

Technical scheme of the present invention is: the Unipolar SPWM pulse signal implementation method based on FPGA, system clock control module provides work clock to triangular carrier signal generator and Sine Modulated wave generator, the output of Sine Modulated wave generator generates sine wave signal, system clock control module regulates the frequency of work clock, controls the frequency of sine wave signal; The both positive and negative polarity two-way triangular carrier that triangular carrier signal generator generates, using sine wave signal as gating signal, finally generates the triangular signal of output single-pole; By the unipolarity carrier wave triangular signal generating and two input signals of modulated sinusoid signal negate module as a comparison, relatively the output of negate module enters dead band time delay control module, dead band time delay control module output SPWM pulse signal.

The generation of described sine wave signal or two triangular carriers of both positive and negative polarity:

Under MATLAB software platform, programming produces the data list file MIF file of sine wave signal or both positive and negative polarity triangular carrier, MIF file is stored in FPGA internal storage space ROM, provide work clock by system clock control module for ROM core module, ROM core will read MIF file data according to work clock order and generate sine wave signal or both positive and negative polarity triangular carrier.

Described by the unipolarity carrier wave triangular signal generating and two input signals of modulated sinusoid signal negate module as a comparison, in the time that carrier wave is more than or equal to modulation wave signal, output high level; In the time that carrier wave is less than modulating wave, output low level, then through relatively processing and can generate a road SPWM1 signal, by the SPWM1 signal negate generating, can obtain another road SPWM2 signal, SPWM1 and SPWM2 signal are the complementary pulse signals without dead band time delay.

Beneficial effect of the present invention is: the present invention is based on the Unipolar SPWM pulse signal implementation method of FPGA, in view of the many merits of FPGA; The SPWM pulse signal producing based on FPGA, has precision high, and speed is fast, and stability is strong, can revise the advantages such as algorithm by online programming.The present invention can provide for electronic power inversion circuit the control wave of high accuracy, high stability.

Brief description of the drawings

Fig. 1 is the Unipolar SPWM generator architecture block diagram that the present invention is based on FPGA;

Fig. 2 is the triangular signal generator based module principle structure chart of unipolarity that the present invention is based on FPGA;

Fig. 3 is the Unipolar SPWM generator schematic diagram that the present invention is based on FPGA;

Fig. 4 is the dead band delay time structure chart based on FPGA of the present invention.

Embodiment

Adopt the full digital algorithm based on FPGA to realize Unipolar SPWM signal generator system.The structured flowchart of system as shown in Figure 1, system is mainly made up of system clock control module, unipolarity triangular carrier signal generator, Sine Modulated wave generator, comparison negate module, dead band time delay control module.

Under MATLAB software platform, programming produces the data list file (.MIF file) of sine wave signal.MIF file is stored in to the free IP cores module of FPGA--in ROM (free IP cores module be Quartus develop software be provided freely to developer use, there is very high stability).Provide work clock by system clock control module for ROM core module, ROM core will read MIF file data according to work clock order and generate sine wave signal, and can, by regulating the frequency of work clock, control the frequency of sine wave signal.

In like manner, under MATLAB software platform, programming produces the data list file (.MIF file) of the two-way triangular signal of positive polarity and negative polarity.MIF file is stored in respectively to the free IP cores of FPGA--in ROM.Provide work clock by system clock control module for ROM core module, ROM core will read MIF file data according to work clock order, generate the two-way triangular signal of positive polarity and negative polarity.

Gating signal using sinusoidal signal as selector, uses two paths of data selector (MUX) to select the polarity of two-way triangular signal.When sine wave signal is timing, select positive polarity triangular signal; When sine wave is when negative, select negative polarity triangular signal.Can generate so unipolar triangular signal, and can, by regulating the frequency of work clock, control the frequency of triangular signal.Three grades of wave generator module principle structure charts of unipolarity as shown in Figure 2.

Unipolar SPWM generator schematic diagram based on FPGA as shown in Figure 3, by unipolarity carrier wave (triangular wave) signal generating and the input signal of modulating wave (sine wave) signal negate module as a comparison.In the time that carrier wave is more than or equal to modulation wave signal, output high level; In the time that carrier wave is less than modulating wave, output low level.Through relatively processing and can generate a road SPWM signal, be designated as SPWM1 like this.By the SPWM1 signal negate generating, can obtain another road SPWM signal, be designated as SPWM2.SPWM1 and SPWM2 signal are the complementary pulse signals without dead band time delay.

Two-way complementation SPWM signal by generating: SPWM1 and SPWM2 signal, as the input of dead band time delay control module.Through dead band delay algorithm computing, output is with the two-way SPWM pulse signal of dead band delay time.

In this embodiment, the power frequency sine wave signal that modulation signal is 50Hz, the triangular signal that carrier signal is 400Hz.The modulation ratio of sinusoidal modulation signal and unipolarity triangular carrier signal is 0.8, frequency ratio is 1/8.What generate is the two-way SPWM signal with dead band time delay.

Utilize MATLAB instrument, generate minimum value and maximum and be respectively the data file of 0 and 127 negative polarity triangular signal; It is MIF file.Profit uses the same method and generates minimum value and maximum and be respectively the data file of 128 and 255 positive polarity triangular signal.The data value MIF file of sine wave signal can utilize MATLAB instrument to generate equally, and what this embodiment generated is that minimum value and maximum are respectively 26 and 230 sinusoidal modulation wave signal (taking 128 as horizontal reference 0 point).Modulation ratio is now:

（230-26）/255=0.8。

Tables of data (MIF) file of the sine wave signal generating is stored in to FPGA internal storage space---in ROM.The data list file of the triangular signal of positive polarity and negative polarity is also stored in ROM, select the polarity of triangular signal by data selector.

180 ° of the triangular signal phase phasic differences of positive polarity and negative polarity.In the time that sinusoidal modulation signal is greater than 128, select positive polarity triangular signal; In the time that sinusoidal modulation signal is less than 128, select negative polarity triangular signal.The triangular signal that this method generates has the polarity identical with sine wave signal (128 is horizontal reference 0 point); Be unipolarity modulation system.

The clock that the external crystal-controlled oscillation clock 50MHz of FPGA obtains after 1024 frequency divisions is sinusoidal modulation wave control clock, according to the sinusoidal signal value in the Clockreading ROM after frequency division, the sine wave signal that output frequency is 50Hz.The clock that external crystal-controlled oscillation clock 50MHz obtains after 128 frequency divisions is simultaneously triangular signal control clock, according to the triangular signal value in the Clockreading ROM after frequency division, the triangular signal that generated frequency is 400Hz.1024 and 128 frequency divisions of clock signal can be realized by 10 digit counters.

Unipolarity triangular signal and the sine wave signal of generation are compared.In the time that triangular signal is more than or equal to sine wave signal, be output as high level; In the time that triangular signal is less than sine wave signal, be output as low level.So just obtain Liao Yi road SPWM1 control signal.By the SPWM1 signal negate obtaining, can obtain an other road SPWM2 signal.

The 50MHz clock that the clock of dead band time delay control module is external crystal-controlled oscillation.Adopt rolling counters forward pattern to generate time of delay.The delay time of choosing in this embodiment is 4us; The i.e. rolling counters forward taking 50MHz as count frequency 200 times.The 4us inhibit signal generating by dead band control module and former SPWM signal carry out and computing, can obtain the Unipolar SPWM pulse signal with dead band time delay.The structure chart that Dead Time produces as shown in Figure 4.

Claims

1. the Unipolar SPWM pulse signal implementation method based on FPGA, it is characterized in that, system clock control module provides work clock to triangular carrier signal generator and Sine Modulated wave generator, the output of Sine Modulated wave generator generates sine wave signal, system clock control module regulates the frequency of work clock, controls the frequency of sine wave signal; The both positive and negative polarity two-way triangular carrier that triangular carrier signal generator generates, using sine wave signal as gating signal, finally generates the triangular signal of output single-pole; By the unipolarity carrier wave triangular signal generating and two input signals of modulated sinusoid signal negate module as a comparison, relatively the output of negate module enters dead band time delay control module, dead band time delay control module output SPWM pulse signal.

2. the Unipolar SPWM pulse signal implementation method based on FPGA according to claim 1, is characterized in that the generation of described sine wave signal or two triangular carriers of both positive and negative polarity:

3. the Unipolar SPWM pulse signal implementation method based on FPGA according to claim 2, it is characterized in that, described by the unipolarity carrier wave triangular signal generating and two input signals of modulated sinusoid signal negate module as a comparison, in the time that carrier wave is more than or equal to modulation wave signal, output high level; In the time that carrier wave is less than modulating wave, output low level, then through relatively processing and can generate a road SPWM1 signal, by the SPWM1 signal negate generating, can obtain another road SPWM2 signal, SPWM1 and SPWM2 signal are the complementary pulse signals without dead band time delay.