CN203840320U - Peripheral circuit for main control circuit - Google Patents
Peripheral circuit for main control circuit Download PDFInfo
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- CN203840320U CN203840320U CN201420261457.3U CN201420261457U CN203840320U CN 203840320 U CN203840320 U CN 203840320U CN 201420261457 U CN201420261457 U CN 201420261457U CN 203840320 U CN203840320 U CN 203840320U
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- governor circuit
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Abstract
The utility model discloses a peripheral circuit for a main control circuit in the integrated circuit field. The main control circuit is provided with an L1 port, an L2 port, a GND port, an I/O port, a VCC port and a CLK port, wherein the GND port is grounded; the L1 port is connected with a first branch M1 via a first current limiting resistor R1; the L2 port is connected with a second branch M2 via a second current limiting resistor R2; and the VCC port is connected with the first branch M1 and the second branch M2 at the same time. the peripheral circuit comprises a discharge capacitor C1, a DC voltage source Vs, a current limiting resistor R4, a diode D1 and a discharge resistor R3, wherein the negative electrode of the discharge capacitor C1 is grounded and the positive electrode is connected with the VCC port of the main control circuit; the negative electrode of the DC voltage source Vs is grounded and the positive electrode is connected with the positive electrode of the diode D1 via a switch K; the negative electrode of the diode D1 is connected with the VCC port of the main control circuit; one end of the current limiting resistor R4 is connected with the positive electrode of the diode D1, and the other end is connected with the CLK port of the main control circuit; and one end of the discharge resistor R3 is connected with the I/O port of the main control circuit and the other end is grounded.
Description
Technical field
The utility model relates to a kind of governor circuit peripheral circuit of integrated circuit fields.
Background technology
In integrated circuit, the back segment PMOS pipe power supply on two branch roads that the direct voltage source Vs of governor circuit controls to governor circuit and governor circuit by peripheral circuit.Peripheral circuit is by giving the operating state that powers on again to switch two branch roads that governor circuit controls after governor circuit power-off.
Refer to Fig. 1, in prior art, governor circuit at least comprises following port: L1 port, L2 port, GND port, I/O port, VCC port and CLK port.GND port ground connection, the grid of the first back segment PMOS pipe Q1 on the first branch road M1 that governor circuit is controlled is connected with the L1 port of governor circuit by the first current-limiting resistance R1, and the grid of the second back segment PMOS pipe Q2 on the second branch road M2 is connected with the L2 port of governor circuit by the second current-limiting resistance R2.The source electrode of the first back segment PMOS pipe Q1 on the first branch road M1 and the source electrode of the second back segment PMOS pipe Q2 on the second branch road M2 connect the VCC port of governor circuit simultaneously, thereby realize the first branch road M1 while and the L1 port of governor circuit and being connected of VCC port, and the second branch road M2 while and the L2 port of governor circuit and being connected of VCC port.The drain electrode of the first back segment PMOS pipe Q1 on the first branch road M1, and the corresponding subsequent conditioning circuit connecting separately of drain electrode of the second back segment PMOS pipe Q2 on the second branch road M2.In the governor circuit of conventional design, I/O port can connect and control the 3rd branch road (not showing in Fig. 1), any one in L1 port or L2 port is during in high level state, I/O port is in high level state, and when L1 port and L2 port are simultaneously in low level or while being in high level state together, I/O port is in low level state.
Governor circuit comprises with peripheral circuit: discharge capacity C1, direct voltage source Vs, current-limiting resistance R4, diode D1 and K switch, wherein, discharge capacity C1 minus earth, positive pole connects the VCC port of governor circuit, direct voltage source Vs minus earth, the anodal positive pole that connects diode D1 by K switch, the negative pole of diode D1 connects the VCC port of governor circuit, one end of current-limiting resistance R4 connects the CLK port of governor circuit, one end connects the positive pole of diode D1 in addition, and direct voltage source Vs can be powered to the positive pole of current-limiting resistance R4 and diode D1 by K switch.
The principle of the first branch road M1 that governor circuit switching governor circuit is controlled and the operating state of the second branch road M2 is as follows: when K switch closure powers on for the first time, governor circuit detects to switch the state of the first branch road M1 by rising edge, the first back segment PMOS pipe Q1 conducting, the first branch road M1 work, the second branch road M2 does not work, L1 port in low level state and L2 port in high level state.When closed again after K switch disconnects, switch the state of the second branch road M2, the second back segment PMOS pipe Q2 conducting, the second branch road M2 work, the first branch road M1 does not work, L2 port in low level state and L1 port in high level state.K switch disconnects rear closure for the third time, the first back segment PMOS pipe Q1 and the second back segment PMOS pipe Q2 conducting simultaneously, and the first branch road M1 and the second branch road M2 work simultaneously, and L1 port and L2 port are simultaneously in low level state.Disconnect again Closing Switch K, get back to the first state, i.e. the first branch road M1 work, the second branch road M2 does not work, L1 port in low level state and L2 port in high level state, circulation successively.In Fig. 1, the I/O of governor circuit end is unsettled, does not connect the 3rd branch road.
The first branch road M1 and the second branch road M2 power by direct voltage source Vs, determine the discharge time of the memory time of governor circuit by discharge capacity C1, when the first branch road M1 or the second branch road M2 work independently, be 3s the discharge time of the discharge capacity C1 that typical capacity is 220uF.After K switch disconnects, the first branch road M1 is or/and T memory time of the power supply of the second branch road M2 and governor circuit must rely on discharge capacity C1 to maintain, and T memory time of governor circuit is the discharge time of discharge capacity C1.When the first branch road M1 or the second branch road M2 work independently, the discharge time of discharge capacity C1 is consistent.When the first branch road M1 and the second branch road M2 work simultaneously, the too fast governor circuit that causes of electric discharge of discharge capacity C1 shortens memory time, after K switch disconnects, half left and right while only having the discharge time of discharge capacity C1 the first branch road M1 or the second branch road M2 to work independently.Cause that the equal time-switching state of governor circuit cannot remember.
Utility model content
This method object is to provide a kind of governor circuit peripheral circuit, and no matter its two branch roads that can guarantee that governor circuit is controlled work independently or work simultaneously, and governor circuit can, after power-off, keep the consistent of memory time.
A kind of technical scheme that realizes above-mentioned purpose is: a kind of governor circuit peripheral circuit, described governor circuit is provided with L1 port, L2 port, GND port, I/O port, VCC port and CLK port, wherein said GND port ground connection, described L1 port connects the first branch road M1 by the first current-limiting resistance R1, described L2 port connects the second branch road M2 by the second current-limiting resistance R2, and described VCC port connects described the first branch road M1 and described the second branch road M2 simultaneously;
This peripheral circuit comprises: discharge capacity C1, direct voltage source Vs, K switch, current-limiting resistance R4 and diode D1, the minus earth of described discharge capacity C1, positive pole connects the VCC port of described governor circuit, described direct voltage source Vs minus earth, the anodal positive pole that meets described diode D1 through described K switch, the negative pole of described diode D1 connects the VCC port of described governor circuit, the positive pole of diode D1 described in a termination of described current-limiting resistance R4, the CLK port of governor circuit described in an other termination
It also comprises that one end is connected with the I/O port of described governor circuit this peripheral circuit, the discharge resistance R3 of other end ground connection.
Further, the resistance of described the first current-limiting resistance R1, described the second current-limiting resistance R2, described current-limiting resistance R4 is 1～10K Ω, and the resistance of described discharge resistance R3 is 10～100K Ω, and the capacity of described discharge capacity C1 is 100～1000 μ F.
Further, this peripheral circuit also comprises the first divider resistance R7 and the second divider resistance R8, described the first divider resistance R7 and the series connection of described K switch, the positive pole that connects described current-limiting resistance R4 and described direct voltage source Vs, and the positive pole of the positive pole of described direct voltage source Vs and described diode D1, one end of described the second divider resistance R8 connects the positive pole of described current-limiting resistance R4 and described diode D1, one end ground connection in addition, described the first divider resistance R7 and described the second divider resistance R8 are variable resistor.
Further, described the second divider resistance R8 is parallel with the voltage stabilizing didoe Z1 of a 5V.
Further, this peripheral circuit also comprises that an one end connects the CLK port of described governor circuit, in addition the filter capacitor C2 of one end ground connection.
Also want further, the resistance of described the first current-limiting resistance R1, described the second current-limiting resistance R2, described current-limiting resistance R4 is 1～10K Ω, the resistance of described discharge resistance R3 is 10～100K Ω, the capacity of described discharge capacity is 100～1000 μ F, and the capacity of described filter capacitor C2 is 1～1000nF.
Further, described governor circuit is BL22P02 type main control chip.
Further, described the first branch road M1 comprises that a source electrode connects the VCC port of described governor circuit, grid connects the first back segment PMOS pipe Q1 of described the first current-limiting resistance R1, described the second branch road M2 comprises that a source electrode connects the VCC port of described governor circuit, and grid connects the second back segment PMOS pipe Q2 of described the second current-limiting resistance R2.
Further, described the first branch road M1 also comprises that connects the described first back segment PMOS pipe source electrode of Q1 and a first biasing resistor R5 of grid, and described the second branch road M2 also comprises that connects the described second back segment PMOS pipe source electrode of Q2 and a second biasing resistor R6 of grid.
Adopt the technical scheme of peripheral circuit for a kind of governor circuit of the present utility model, at the VCC of governor circuit port, increased the technical scheme of the discharge resistance R3 of a ground connection.Its technique effect is: no matter its two branch roads that can guarantee that governor circuit is controlled work independently or work simultaneously, and governor circuit can, after power-off, keep the consistent of memory time.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of peripheral circuit for the governor circuit of prior art.
Fig. 2 is the first embodiment circuit diagram of peripheral circuit for a kind of governor circuit of the present utility model.
Fig. 3 is the second embodiment circuit diagram of peripheral circuit for a kind of governor circuit of the present utility model.
Embodiment
Refer to Fig. 1, inventor of the present utility model is in order to understand the technical solution of the utility model better, below by embodiment particularly, and is described in detail by reference to the accompanying drawings:
The first embodiment:
Refer to Fig. 2, a kind of governor circuit of the present utility model is used for a kind of governor circuit that can simultaneously control two branch road operating states with peripheral circuit, this governor circuit at least comprises following port: L1 port, L2 port, GND port, I/O port, VCC port and CLK port, any one in L1 port or L2 port is during in high level state, I/O port is in high level state, and when L1 port and L2 port are simultaneously in low level or while being in high level state together, I/O port is in low level state.The GND port ground connection of governor circuit, the grid of the first back segment PMOS pipe Q1 on the first branch road M1 that governor circuit is controlled is connected with the L1 port of governor circuit by the first current-limiting resistance R1, and the grid of the second back segment PMOS pipe Q2 on the second branch road M2 is connected with the L2 port of governor circuit by the second current-limiting resistance R2.The source electrode of the first back segment PMOS pipe Q1 on the first branch road M1 and the source electrode of the second back segment PMOS pipe Q2 on the second branch road M2 connect the VCC port of governor circuit simultaneously, thereby realize the first branch road M1 while and the L1 port of governor circuit and being connected of VCC port, the second branch road M2 while and the L2 port of governor circuit and being connected of VCC port.The drain electrode of the first back segment PMOS pipe Q1 on the first branch road M1, and the corresponding subsequent conditioning circuit connecting separately of drain electrode of the second back segment PMOS pipe Q2 on the second branch road M2.
Governor circuit of the present utility model comprises with peripheral circuit: discharge capacity C1, direct voltage source Vs, K switch, current-limiting resistance R4, diode D1 and discharge resistance R3.The minus earth of discharge capacity C1 wherein, positive pole connects the VCC port of governor circuit.Direct voltage source Vs minus earth, the anodal positive pole that meets diode D1 by K switch, the negative pole of diode D1 connects the VCC port of governor circuit, the positive pole of a terminating diode D1 of current-limiting resistance R4, the CLK port of an other termination governor circuit, thus direct voltage source Vs can power to current-limiting resistance R4 and diode D1 by K switch.The I/O port of governor circuit is by discharge resistance R3 ground connection.This governor circuit has just been to increase one end with the greatest improvement point of peripheral circuit and has been connected with the I/O port of governor circuit, the discharge resistance R3 of other end ground connection.
A kind of governor circuit of the present utility model is by the object that increases discharge resistance R3 in peripheral circuit: when, in the first branch road M1 or the second branch road M2, there is any one branch road in running order, be in L1 port or L2 port, there is any one port in low level state, and another one port is when high level state, I/O port is in high level state, and governor circuit can discharge over the ground by discharge resistance R3.The first branch road M1 or the second branch road M2 work simultaneously, and L1 port and L2 port are simultaneously when low level state, and I/O port is in low level state, and governor circuit cannot discharge over the ground by discharge resistance R3.No matter the second branch road M2 connecting due to the first branch road M1 connecting at L1 port or L2 port is to work simultaneously or work independently, and discharge capacity C1 carries out two-way electric discharge simultaneously.No matter guarantee when the first branch road M1 or the second branch road M2 work independently, or when the first branch road M1 and the second branch road M2 work simultaneously, governor circuit can guarantee that memory time is consistent.
In the present embodiment, the capacity of discharge capacity C1 is 100-1000uF, and the resistance of the first current-limiting resistance R1 is 1-10K Ω, and the resistance of the second current-limiting resistance R2 is 1-10K Ω, and the resistance of discharge resistance R3 is 10-100K Ω, and the resistance of current-limiting resistance R4 is 1-10K Ω.When the first branch road M1 and the second branch road M2 work simultaneously, or the first branch road M1 or the second branch road M2 are when work independently, and mainly by the capacity of discharge capacity C1 and the resistance of discharge resistance R3, are determined the discharge time of discharge capacity C1.
The second embodiment:
Refer to Fig. 3, at a kind of governor circuit peripheral circuit of the present utility model, can be used for as governor circuits such as BL22P02 main control chips.The GND port ground connection of governor circuit.The first branch road M1 that governor circuit is controlled is connected with L2 port with the L1 port of governor circuit by the first current-limiting resistance R1, the second current-limiting resistance R2 are corresponding with the second branch road M2.On the basis of the first embodiment, on the first branch road M1, increased by one and connected the first back segment PMOS pipe source electrode of Q1 and the first biasing resistor R5 of grid.On the second branch road M2, increase by one and connected the second back segment PMOS pipe source electrode of Q2 and the second biasing resistor R6 of grid.Governor circuit switches the operating state of the first branch road M1 and the second branch road M2 by controlling the first back segment PMOS pipe Q1 and the second back segment PMOS pipe Q2.
Governor circuit of the present utility model comprises with peripheral circuit: discharge capacity C1, direct voltage source Vs, K switch, current-limiting resistance R4, diode D1 and discharge resistance R3.The minus earth of discharge capacity C1 wherein, positive pole connects the VCC port of governor circuit.Direct voltage source Vs minus earth, the anodal positive pole that meets diode D1 by K switch, the negative pole of diode D1 connects the VCC port of governor circuit, the positive pole of a terminating diode D1 of current-limiting resistance R4, the CLK port of an other termination governor circuit, thus direct voltage source Vs can power to current-limiting resistance R4 and diode D1 by K switch.The I/O port of governor circuit is by discharge resistance R3 ground connection.This governor circuit has just been to increase one end with the greatest improvement point of peripheral circuit and has been connected with the I/O port of governor circuit, the discharge resistance R3 of other end ground connection.
A kind of peripheral circuit governor circuit of the present utility model, has also increased the first divider resistance R7 and the second divider resistance R8.One end connecting valve K of the first divider resistance R7, one end connects the positive pole of current-limiting resistance R4 and diode D1 in addition, thereby direct voltage source Vs must be powered to current-limiting resistance R4 and diode D1 by the first divider resistance R7 and K switch.One end ground connection of the second divider resistance R8, one end connects the positive pole of current-limiting resistance R4 and diode D1 in addition.Wherein the first divider resistance R7 and the second divider resistance R8 are variable resistor, its role is to make current-limiting resistance R4 by dividing potential drop, to obtain the burning voltage of a 5V.Wherein, the second divider resistance R8 is also in parallel with the voltage stabilizing didoe Z1 of a 5V, and this voltage stabilizing didoe Z1 is used for after clamper dividing potential drop, and the magnitude of voltage of the VCC port of governor circuit, plays the protective effect to governor circuit.This governor circuit is with in peripheral circuit, and the effect of diode D1 is: preventing that K switch from closing has no progeny, the impact that the voltage on discharge capacity C1 is discharged by the second divider resistance R8 simultaneously, and affect memory time of governor circuit.
In addition, a kind of governor circuit peripheral circuit of the present utility model, also comprises that an one end connects the CLK port of governor circuit, in addition the filter capacitor C2 of one end ground connection.The effect of filter capacitor C2 is mainly filter action, prevents that interference signal from causing the false triggering of the CLK port of governor circuit.
In the present embodiment, the capacity of discharge capacity C1 is 100-1000uF, and the resistance of the first current-limiting resistance R1 is 10-10K Ω, and the resistance of the second current-limiting resistance R2 is 10-10K Ω, and the resistance of discharge resistance R3 is 10-100K Ω, and the resistance of current-limiting resistance R4 is 1-10K Ω.The capacity of filter capacitor C2 is generally 1-1000nF.
Those of ordinary skill in the art will be appreciated that, above embodiment is only for the utility model is described, and be not used as restriction of the present utility model, as long as within the scope of connotation of the present utility model, to the variation of above embodiment, modification, all will drop within the scope of claims of the present utility model.
Claims (9)
1. a governor circuit peripheral circuit, described governor circuit is provided with L1 port, L2 port, GND port, I/O port, VCC port and CLK port, wherein said GND port ground connection, described L1 port connects the first branch road M1 by the first current-limiting resistance R1, described L2 port connects the second branch road M2 by the second current-limiting resistance R2, and described VCC port connects described the first branch road M1 and described the second branch road M2 simultaneously;
This peripheral circuit comprises: discharge capacity C1, direct voltage source Vs, K switch, current-limiting resistance R4 and diode D1, the minus earth of described discharge capacity C1, positive pole connects the VCC port of described governor circuit, described direct voltage source Vs minus earth, the anodal positive pole that meets described diode D1 through described K switch, the negative pole of described diode D1 connects the VCC port of described governor circuit, the positive pole of diode D1 described in a termination of described current-limiting resistance R4, the CLK port of governor circuit described in an other termination, is characterized in that:
It also comprises that one end is connected with the I/O port of described governor circuit, the discharge resistance R3 of other end ground connection.
2. a kind of governor circuit peripheral circuit according to claim 2, it is characterized in that: the resistance of described the first current-limiting resistance R1, described the second current-limiting resistance R2, described current-limiting resistance R4 is 1～10K Ω, the resistance of described discharge resistance R3 is 10～100K Ω, and the capacity of described discharge capacity C1 is 100～1000 μ F.
3. a kind of governor circuit peripheral circuit according to claim 1, it is characterized in that: this peripheral circuit also comprises the first divider resistance R7 and the second divider resistance R8, described the first divider resistance R7 and the series connection of described K switch, the positive pole that connects described current-limiting resistance R4 and described direct voltage source Vs, and the positive pole of the positive pole of described direct voltage source Vs and described diode D1, one end of described the second divider resistance R8 connects the positive pole of described current-limiting resistance R4 and described diode D1, one end ground connection in addition, described the first divider resistance R7 and described the second divider resistance R8 are variable resistor.
4. a kind of governor circuit peripheral circuit according to claim 3, is characterized in that: described the second divider resistance R8 is parallel with the voltage stabilizing didoe Z1 of a 5V.
5. a kind of governor circuit peripheral circuit according to claim 4, is characterized in that: this peripheral circuit also comprises that an one end connects the CLK port of described governor circuit, in addition the filter capacitor C2 of one end ground connection.
6. a kind of governor circuit peripheral circuit according to claim 5, it is characterized in that: the resistance of described the first current-limiting resistance R1, described the second current-limiting resistance R2, described current-limiting resistance R4 is 1～10K Ω, the resistance of described discharge resistance R3 is 10～100K Ω, the capacity of described discharge capacity is 100～1000 μ F, and the capacity of described filter capacitor C2 is 1～1000nF.
7. according to a kind of governor circuit peripheral circuit described in claim 3～6, it is characterized in that: described governor circuit is BL22P02 type main control chip.
8. according to a kind of governor circuit peripheral circuit described in any one in claim 1～6, it is characterized in that: described the first branch road M1 comprises that a source electrode connects the VCC port of described governor circuit, grid connects the first back segment PMOS pipe Q1 of described the first current-limiting resistance R1, described the second branch road M2 comprises that a source electrode connects the VCC port of described governor circuit, and grid connects the second back segment PMOS pipe Q2 of described the second current-limiting resistance R2.
9. a kind of governor circuit peripheral circuit according to claim 8, it is characterized in that: described the first branch road M1 also comprises that connects the described first back segment PMOS pipe source electrode of Q1 and a first biasing resistor R5 of grid, and described the second branch road M2 also comprises that connects the described second back segment PMOS pipe source electrode of Q2 and a second biasing resistor R6 of grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420261457.3U CN203840320U (en) | 2014-05-20 | 2014-05-20 | Peripheral circuit for main control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420261457.3U CN203840320U (en) | 2014-05-20 | 2014-05-20 | Peripheral circuit for main control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203840320U true CN203840320U (en) | 2014-09-17 |
Family
ID=51518113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420261457.3U Withdrawn - After Issue CN203840320U (en) | 2014-05-20 | 2014-05-20 | Peripheral circuit for main control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203840320U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103973293A (en) * | 2014-05-20 | 2014-08-06 | 上海贝岭股份有限公司 | Peripheral circuit for master control circuit |
-
2014
- 2014-05-20 CN CN201420261457.3U patent/CN203840320U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103973293A (en) * | 2014-05-20 | 2014-08-06 | 上海贝岭股份有限公司 | Peripheral circuit for master control circuit |
| CN103973293B (en) * | 2014-05-20 | 2016-11-23 | 上海贝岭股份有限公司 | A kind of governor circuit peripheral circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140917 Effective date of abandoning: 20161012 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |