CN203839363U - Ultrathin diode pin - Google Patents
Ultrathin diode pin Download PDFInfo
- Publication number
- CN203839363U CN203839363U CN201420273532.8U CN201420273532U CN203839363U CN 203839363 U CN203839363 U CN 203839363U CN 201420273532 U CN201420273532 U CN 201420273532U CN 203839363 U CN203839363 U CN 203839363U
- Authority
- CN
- China
- Prior art keywords
- pin
- inner face
- face
- end surface
- insert
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides an ultrathin diode pin which is strong in power-on capability, increased in solder surfaces and is suitable for a large chip. The ultrathin diode pin comprises a pin 1, a pin 2 and a packaging body. The pin 1 and the pin 2 are in sheet shape. The pin 1 comprises an inner end surface 1 and an outer end surface 1. The pin 2 comprises an inner end surface 2 and an outer end surface 2. The inner end surface 1 is connected with one end of the packaging body. The inner end surface 2 is connected with the other end of the packaging body. The end portion of the inner end surface 1 is provided with a square groove 1. An insert block 1 is also included, and the insert block 1 is arranged in the square groove 1. The plane area of the insert block 1 is larger than that of the inner end surface 1. The ultrathin diode pin provides a new design idea for diodes; and the conventional straight-up-and-down design of the pin is changed into a design that the place where the pin and the chip are contacted is partially enlarged, that is, the insert block. Under the premise of not influencing packaging, the plane areas of the insert blocks are enlarged as much as possible; and large chips are utilized, and the power-on capability of the product can be improved.
Description
Technical field
The utility model relates to diode, relates in particular to the pin of the ultra-thin diode that photovoltaic uses.
Background technology
Electrical type industry at present, product appearance is to miniaturization, microminiaturized future development, product ability is to high efficiency, the future development of low energy consumption, this makes our semiconductor device arrive under very little condition in product design, increases the chip size of our product, improves the energising ability of product.Traditional product structure mostly is straight up and down formula design (as shown in Figure 13-15), and due to design limitation itself, running into large chip encapsulation, need to increase base copper face long-pending, and increase copper material area has been subject to again the little restriction of small product size, so cannot realize.
Utility model content
The utility model, for above problem, provides a kind of energising ability strong, increases solder side, applicable to the ultra-thin diode pin of large chip.
The technical scheme of utility model is: comprise pin one, pin two and packaging body, described pin one and described pin two are in the form of sheets, described pin one comprises inner face one and outer face one, described pin two comprises inner face two and outer face two, described inner face one connects one end of described packaging body, described inner face two connects the other end of described packaging body, the end of described inner face one is provided with square groove one, also comprise and insert one, be located in described groove one, described in insert inner face one described in one area of plane > the area of plane.
Described one the end face inserted exceeds the end face of described inner face one.
The width of inner face one described in described one the width G reatT.GreaT.GT of inserting.
The width of packaging body described in described one the width < of inserting.
Described pin two is provided with inserts two, and the end of described inner face two is provided with square groove two, described in insert and two be located in described groove two, described in insert inner face two described in two area of plane > the area of plane.
Described two the end face inserted exceeds the end face of described inner face two.
The width of inner face two described in described two the width G reatT.GreaT.GT of inserting.
The width of packaging body described in described two the width < of inserting.
Described outer face one and described outer face two are respectively equipped with through hole, have one at least for waist hole in described through hole, and another is circular hole or waist hole.
The utility model is skillfully constructed, and for diode provides new design concept, traditional pin is designed by formula straight up and down, changes to local increase the in place that pin contacts with chip, is and inserts.Not affecting under the prerequisite of encapsulation, according to concrete product requirement, as much as possible the area of plane of inserting is increased, use large chip, the galvanization ability of product can be improved.The utility model can change diode overall dimension and client pad (equipment by chips welding on pin) size simultaneously, realizes the versatility of frock, equipment, reduces production costs.
Brief description of the drawings
Fig. 1 is the structural representation of the utility model the first execution mode,
Fig. 2 is the left view of Fig. 1,
Fig. 3 is the rearview of Fig. 1,
Fig. 4 is the structural representation of inner face one and outer face one in Fig. 1,
Fig. 5 is the left view of Fig. 4,
Fig. 6 is the structural representation of pin one in Fig. 1,
Fig. 7 is the left view of Fig. 6,
Fig. 8 is the structural representation of the further prioritization scheme of the utility model the first execution mode,
Fig. 9 is the structural representation of inner face two and outer face two in Fig. 1,
Figure 10 is the left view of Fig. 9,
Figure 11 is the structural representation of the utility model the second execution mode,
Figure 12 is the left view of Figure 11,
Figure 13 is the structural representation of the utility model background technology,
Figure 14 is the left view of Figure 13,
Figure 15 is the rearview of Figure 13;
In figure, 1 is packaging body, the 2nd, and pin one, 21st, inner face one, 211st, groove one, 22nd, outer face one, the 23rd, insert one, 3rd, pin two, 31st, inner face two, 311st, groove two, 32nd, outer face two, the 33rd, insert two, 4th, chip, the 5th, wire jumper, the 6th, waist hole, the 7th, circular hole.
Embodiment
The utility model the first execution mode is as shown in Fig. 1-7, comprise pin 1, pin 23, packaging body 1, chip 4 and wire jumper 5, described pin 1 and described pin 23 are in the form of sheets, described pin 1 comprises inner face 1 and outer face 1, the end of described inner face 1 is provided with square groove 1, described pin 23 comprises inner face 2 31 and outer face 2 32, described inner face 1 connects one end of described packaging body 1, and described inner face 2 31 connects the other end of described packaging body 1;
Also comprise and insert 1, be located in described groove 1, form cross sections with described inner face 1, the area of plane of inner face 1 described in described one 23 the area of plane > of inserting, described one 23 the end face inserted exceeds the end face of described inner face 1, the width of inner face 1 described in described one 23 the width G reatT.GreaT.GT of inserting, the width of packaging body 1 described in described one 23 the width < of inserting, described in insert one 23 upper plane concordant with the upper plane of described outer face 1.
The further prioritization scheme of the utility model the first execution mode is as shown in Fig. 6-10, on described pin 23, be provided with and insert 2 33, realize described ultra-thin diode and can be applicable to multiple product (for example twin-core chip), the end of described inner face 2 31 is provided with square groove 2 311, described inserting 2 33 is located in described groove 2 311, form cross section with described outer face 2 32, the area of plane of inner face 2 31 described in described 2 33 the area of plane > of inserting, described 2 33 the end face inserted exceeds the end face of described inner face 2 31, the width of inner face 2 31 described in described 2 33 the width G reatT.GreaT.GT of inserting, the width of packaging body 1 described in described 2 33 the width < of inserting, described 2 33 the upper plane of inserting is concordant with the upper plane of described outer face 2 32.For convenience and the cost considering to produce, described in insert the relatively described inner face 1 in one 23 both sides with described in the 2 33 relative described inner faces 2 31 in both sides of inserting be symmetrical arranged as the best.
Described chip 4 insert described in being located at 1 and/or described in insert on 2 33, described wire jumper 5 is located on described chip 4 and described pin 1 and/or pin 23, plays connection function.
The utility model the second execution mode is as shown in Figure 11-12, described outer face 1 and described outer face 2 32 are respectively equipped with through hole, in described through hole, has one at least for waist hole 6, another is circular hole 7 or waist hole 6, in the time that ultra-thin diode is fixed on surface-mounted integrated circuit, can be fixed by described through hole, when the object that described waist hole 6 is set is to prevent installation deviation, leave adjusting surplus.
Claims (9)
1. a ultra-thin diode pin, comprise pin one, pin two and packaging body, described pin one and described pin two are in the form of sheets, described pin one comprises inner face one and outer face one, described pin two comprises inner face two and outer face two, described inner face one connects one end of described packaging body, described inner face two connects the other end of described packaging body, it is characterized in that, the end of described inner face one is provided with square groove one, also comprise and insert one, be located in described groove one, the area of plane of inner face one described in described one the area of plane > of inserting.
2. the ultra-thin diode pin of one according to claim 1, is characterized in that, described in insert one end face exceed the end face of described inner face one.
3. the ultra-thin diode pin of one according to claim 1, is characterized in that, described in the insert width of inner face one described in one width G reatT.GreaT.GT.
4. the ultra-thin diode pin of one according to claim 1, is characterized in that, described in the insert width of packaging body described in one width <.
5. the ultra-thin diode pin of one according to claim 1, it is characterized in that, described pin two is provided with inserts two, the end of described inner face two is provided with square groove two, described inserting two is located in described groove two, described in insert inner face two described in two area of plane > the area of plane.
6. the ultra-thin diode pin of one according to claim 5, is characterized in that, described in insert two end face exceed the end face of described inner face two.
7. the ultra-thin diode pin of one according to claim 5, is characterized in that, described in the insert width of inner face two described in two width G reatT.GreaT.GT.
8. the ultra-thin diode pin of one according to claim 5, is characterized in that, described in the insert width of packaging body described in two width <.
9. the ultra-thin diode pin of one according to claim 1, is characterized in that, described outer face one and described outer face two are respectively equipped with through hole, has one at least for waist hole in described through hole, and another is circular hole or waist hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420273532.8U CN203839363U (en) | 2014-05-26 | 2014-05-26 | Ultrathin diode pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420273532.8U CN203839363U (en) | 2014-05-26 | 2014-05-26 | Ultrathin diode pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203839363U true CN203839363U (en) | 2014-09-17 |
Family
ID=51517169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420273532.8U Expired - Fee Related CN203839363U (en) | 2014-05-26 | 2014-05-26 | Ultrathin diode pin |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203839363U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108540086A (en) * | 2018-01-18 | 2018-09-14 | 浙江人和光伏科技有限公司 | A kind of conductive module of solar battery connecting box |
-
2014
- 2014-05-26 CN CN201420273532.8U patent/CN203839363U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108540086A (en) * | 2018-01-18 | 2018-09-14 | 浙江人和光伏科技有限公司 | A kind of conductive module of solar battery connecting box |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140917 Termination date: 20180526 |