CN203813760U - Shift frequency divider circuit - Google Patents
Shift frequency divider circuit Download PDFInfo
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- CN203813760U CN203813760U CN201420143546.8U CN201420143546U CN203813760U CN 203813760 U CN203813760 U CN 203813760U CN 201420143546 U CN201420143546 U CN 201420143546U CN 203813760 U CN203813760 U CN 203813760U
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Abstract
The utility model discloses a shift frequency divider circuit, and further relates to a shift frequency divider circuit of N-frequency division, wherein the N represents an integer which is equal to or more than 2. The shift frequency divider circuit comprises a phase inverter, (N-1) registers, and (N-2) logic gate devices; the output terminal of the (N-1)th register is connected to the input terminal of the phase inverter, the output terminal of the phase inverter is connected to the input terminal of the first register and the input terminals of each logic gate device; all logic gate device are arranged between the output terminals and input terminals of the first register to the (N-1)th register, the output terminal of the first register is connected to the other input terminal of the first logic gate device, the output terminal of the first logic gate device is connected to the input terminal of the second register, and the output terminal of the (N-2)th logic gate device is connected to the input terminal of the (N-1)th register. The shift frequency divider circuit has a simple structure, requires fewer registers and logic gate devices under the same frequency division requirements, and can go back to normal frequency division after interference.
Description
Technical field
The utility model relates to digital IC technical field, relates more specifically to a kind of shift frequency divider circuit.
Background technology
Common frequency divider generally has two kinds: shift frequency divider and frequency-dividing counter.
Frequency-dividing counter, because phase place is more complicated than shift frequency divider control logic, often cannot meet sequential requirement in high-frequency design, is therefore usually used in the desiging frequency divider of medium and low frequency clock.And shift frequency divider logic is fairly simple, even also can meet sequential requirement in high-frequency design, be therefore usually used in the desiging frequency divider of high frequency clock.But, traditional shift frequency divider, after frequency division, the quality of clock depends on initial condition and the conversion of the state in running of register group completely, once because some unforeseen reasons cause status error, will directly cause frequency division to go wrong, even completely mistake.
Therefore, for the problems referred to above, be necessary to provide a kind of improved shift frequency divider circuit to overcome above-mentioned defect.
Utility model content
The purpose of this utility model is to provide a kind of shift frequency divider circuit, and shift frequency divider circuit structure of the present utility model is simple, and under identical frequency division demand, required register and gate device still less, and can normally recover frequency division later disturbing.
For achieving the above object, the utility model provides a kind of shift frequency divider circuit, and is the shift frequency divider circuit of Fractional-N frequency, wherein, N is more than or equal to 2 positive integer, and described shift frequency divider circuit comprises inverter, a N-1 register and N-2 gate device; Described in each, the reset terminal of register is all connected with systematic reset signal end, and described in each, the clock end of register is connected with external high frequency output terminal of clock; The output of described N-1 register is connected with the input of described inverter, and the output of described inverter is connected with the input of described the 1st register and an input of each gate device respectively; Described in each, gate device is connected between the output and input of the 1st register to the N-1 register, and the output of the 1st register is connected with another input of the 1st gate device, the output of the 1st gate device is connected with the input of the 2nd register, the output of N-2 register is connected with another input of N-1 gate device, and the output of N-2 gate device is connected with the input of N-1 register.
Preferably, when N equals 2, described shift frequency divider comprises inverter and 1 register, and the output of described register is connected with the input of described inverter, and the output of described inverter is connected with the input of described register.
Preferably, described gate device is and door.
Preferably, described gate device is or door.
Compared with prior art, shift frequency divider circuit of the present utility model, owing to comprising inverter and N-2 gate device, makes to realize Fractional-N frequency and only needs N-1 register, has simplified the structure of shift frequency divider, is convenient to realize; And the inverter of shift frequency divider circuit of the present utility model all reverses to the output of N-1 register within each clock cycle, and input to the 1st register and each gate device, thereby after the intermediateness of described shift frequency divider makes mistake, can return within a certain period of time normal, and after recovery, can guarantee that frequency dividing ratio is constant, improve the scope of application of shift frequency divider circuit, reduced the impact of external disturbance on frequency division.
By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the utility model shift frequency divider circuit.
Fig. 2 is the circuit structure diagram of the first embodiment of the utility model shift frequency divider circuit.
Fig. 3 is the circuit structure diagram that shown in Fig. 2, shift frequency divider circuit carries out 6 frequency divisions.
Fig. 4 is the sequential chart of the normal work of circuit shown in Fig. 3.
Fig. 5 is the sequential chart of work when circuit is interfered shown in Fig. 3.
Fig. 6 is the circuit structure diagram of the second embodiment of the utility model shift frequency divider circuit.
Fig. 7 is the circuit structure diagram that shown in Fig. 6, shift frequency divider circuit carries out 6 frequency divisions.
Fig. 8 is the sequential chart of the normal work of circuit shown in Fig. 7.
Fig. 9 is the sequential chart of work when circuit is interfered shown in Fig. 7.
Figure 10 is the circuit structure diagram of the 3rd embodiment of the utility model shift frequency divider circuit.
Embodiment
With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of shift frequency divider circuit, and shift frequency divider circuit structure of the present utility model is simple, and under identical frequency division demand, required register and gate device still less, and can normally recover frequency division later disturbing.
Please refer to Fig. 1, as shown in the figure, the shift frequency divider that the shift frequency divider of the utility model shift frequency divider circuit is Fractional-N frequency, N is more than or equal to 2 positive integer; Described shift frequency divider comprises inverter, a N-1 register and N-2 gate device; Described in each, the reset terminal of register is all connected with systematic reset signal end, and described in each, the clock end of register is connected with external high frequency output terminal of clock; The output of described N-1 register is connected with the input of described inverter, and the output of described inverter is connected with the input of described the 1st register and an input of each gate device respectively; Described in each, gate device is connected between the output and input of the 1st register to the N-1 register, and the output of the 1st register is connected with another input of the 1st gate device, the output of the 1st gate device is connected with the input of the 2nd register, and the output of N-2 gate device is connected with the input of N-1 register; Thereby the direct input as the 1st register after the output negate of described N-1 register, and the input of the 2nd register to the N-1 register is output and the N-1 register output negate of last register and by gate device, carries out the result of logical operation, so, experienced after N clock pulse, N-1 register always can allow other N-2 register enter reset mode, reverts to initial condition completely.Then, then carry out the circulation of N state next time, even if shake is occurred, shift frequency divider circuit of the present utility model also can recover normal work.
Particularly, please refer to Fig. 2 to Fig. 5, describe first embodiment of the utility model.As shown in Figure 2, the gate device of the shift frequency divider circuit of the present embodiment is and door, it comprises inverter INV, a N-1 register (the 1st register RE1, the 2nd register RE2 ... N-1 register REN-1) and N-2 and door (the 1st with a door AND1, the 2nd with a door AND2 ... N-2 and door ANDN-2), N is the frequency dividing ratio of described shift frequency divider, and for being more than or equal to 2 positive integer; And D is the input of register described in each, Q is the output of register described in each, also identical in follow-up each figure.Wherein, described in each, the reset terminal RN of register is all connected with systematic reset signal end, systematic reset signal end is to the RN input system reset signal RSTN of the reset terminal of each register, in the starting stage, shift frequency divider is carried out to integral reset, even if each register is all set to " 1 " or " 0 "; Described in each, the clock end CK of register is connected with external high frequency output terminal of clock, and external high frequency output terminal of clock output high frequency clock CLK is to the clock end CK of each register, to control the operation of each register.The output of described N-1 register REN-1 is connected with the input of described inverter INV, the output of described inverter INV is connected with an input of door with the input of described the 1st register RE1 and each respectively, thus described inverter INV by after the output output negate of described N-1 register REN-1, input to described the 1st register RE1 and each and.Each and door are connected between the input and output of the 1st register to the N-1 register, and the output of the 1st register RE1 is connected with another input of door AND1 with the 1st, the output of N-2 register REN-2 is connected with another input of door ANDN-2 with N-2, the 1st is connected with the input of the 2nd register RE2 with the output of door AND1, and N-2 is connected with the input of N-1 register REN-1 with the output of door ANDN-2.
When the shift-register circuit of the present embodiment is worked, the initial condition of each register is set to " 0 ".Described in each, register is shifted successively, and described in each the output of register and the output negate of N-1 register REN-1 and with the next register of rear input; After the output negate of N-1 register REN-1, directly input the input of the first register RE1, the output negate of the output of the 1st register RE1 and N-1 register REN-1 is also inputted 2nd register RE2 with door after AND1 through the 1st, the output negate of the output of the 2nd register RE2 and N-1 register REN-1 is also inputted 3rd register RE3 with door after AND2 through the 2nd, by that analogy.Like this, experienced after N clock pulse, N-1 register REN-1 always can allow other N-2 register enter reset mode, reverts to initial condition completely.Then carry out the circulation of N state next time then.Like this, even if the middle operating state of described shift frequency divider goes wrong, also can recover over time normal, thereby assurance frequency divider is normally worked.Wherein, see Fig. 3, the shift frequency divider circuit that Fig. 3 is the present embodiment carries out the circuit structure diagram of 6 frequency divisions, when it is normally worked, the waveform of output as shown in Figure 4, each register is 6 frequency-dividing clocks outputs, and duty ratio is different, and wherein distributor (cyc[2]) output clock duty ratio is 1:1, from oscillogram, can find out, the state of register value is respectively 00000,00001,00011,00111,01111,1111, circulation always, thus produce frequency-dividing clock; And when shift frequency divider circuit is interfered, as Fig. 5 indicating line M1 place, buffer status value should be 111, but because abnormal conditions are modified to 110, makes frequency divider enter error condition, but after several clocks, at graticule M2 place, register is reset, and its state value returns to 0 normal condition entirely, from then on frequency division enters normal frequency division state, from abnormality, recovers.Therefore,, even if there is abnormal shake, the divider circuit of the present embodiment can return to normal condition again after several clocks (the longest N-2 of a needs clock), has guaranteed normally carrying out of frequency division.
Refer again to Fig. 6-8 and describe the second embodiment of the present utility model, as shown in Figure 6, the shift frequency divider circuit of the present embodiment and the difference of embodiment 1 be only, the gate device in the present embodiment is or door (OR1, OR2 ... ORN-2), specifically see Fig. 6.And, the course of work of device circuit is posted in the displacement of the present embodiment and the difference of embodiment 1 is only, in the present embodiment, described systematic reset signal RSTN is all set to " 0 " output of register and output negate of N-1 register REN-1 mutually or afterwards as the input of next register described in each using each register, meanwhile, the direct input as the first register RE1 after the output negate of N-1 register REN-1; Like this, experienced after N clock pulse, N-1 register REN-1 always can allow other N-2 register enter reset mode, reverts to initial condition completely; Then carry out the circulation of N state next time then.Like this, even if the middle operating state of described shift frequency divider goes wrong, also can recover over time normal, thereby assurance frequency divider is normally worked.Specifically, Fig. 7 is the circuit structure diagram that the shift frequency divider of the present embodiment carries out 6 frequency divisions, during its normal work, the waveform of output as shown in Figure 8, from oscillogram, can find out, the state of register value is respectively 11111,11110,11100,11000,10000,00000, circulation always, thus frequency-dividing clock produced; And when shift frequency divider circuit is interfered, as Fig. 9 indicating line M1 place, buffer status value should be 11100, but because abnormal conditions are modified to 10111, makes frequency divider enter error condition, but after several clocks, at graticule M2 place, register is reset, and its state value returns to 1 normal condition entirely, from then on frequency division enters normal frequency division state, from abnormality, recovers.
Please again in conjunction with reference to Figure 10, Figure 10 shows that a specific embodiments of the utility model shift frequency divider circuit, the shift frequency divider circuit of the present embodiment is realized 2 frequency divisions to high frequency clock CLK, and the difference of the present embodiment and other embodiment is only that the shift frequency divider circuit of the present embodiment does not comprise gate device, and other is all identical.Particularly, the shift frequency divider circuit of the present embodiment comprises inverter INV and register RE1, and the concrete annexation of each device is shown in Figure 10, no longer carefully states.The shift frequency divider circuit of the present embodiment, due to a register, makes whole register only have two states, is " 0 ", " 1 "; Thereby even the intermediateness of described shift frequency divider circuit goes wrong, can not exceed outside these 2 states yet; Therefore the shift frequency divider circuit of the present embodiment not only can normally carry out 2 frequency divisions to high frequency clock CLK, and its course of work can not occur because of the variation of intermediateness extremely.
Above combination most preferred embodiment is described the utility model, but the utility model is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present utility model, equivalent combinations.
Claims (4)
1. a shift frequency divider circuit, and be the shift frequency divider circuit of Fractional-N frequency, it is characterized in that, N is more than or equal to 2 positive integer, and described shift frequency divider circuit comprises inverter, a N-1 register and N-2 gate device; Described in each, the reset terminal of register is all connected with systematic reset signal end, and described in each, the clock end of register is connected with external high frequency output terminal of clock; The output of described N-1 register is connected with the input of described inverter, and the output of described inverter is connected with the input of described the 1st register and an input of each gate device respectively; Described in each, gate device is connected between the output and input of the 1st register to the N-1 register, and the output of the 1st register is connected with another input of the 1st gate device, the output of the 1st gate device is connected with the input of the 2nd register, the output of N-2 register is connected with another input of N-1 gate device, and the output of N-2 gate device is connected with the input of N-1 register.
2. shift frequency divider circuit as claimed in claim 1, it is characterized in that, when N equals 2, described shift frequency divider comprises inverter and 1 register, the output of described register is connected with the input of described inverter, and the output of described inverter is connected with the input of described register.
3. shift frequency divider circuit as claimed in claim 2, is characterized in that, described gate device is and door.
4. shift frequency divider circuit as claimed in claim 2, is characterized in that, described gate device is or door.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420143546.8U CN203813760U (en) | 2014-03-27 | 2014-03-27 | Shift frequency divider circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420143546.8U CN203813760U (en) | 2014-03-27 | 2014-03-27 | Shift frequency divider circuit |
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|---|---|
| CN203813760U true CN203813760U (en) | 2014-09-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420143546.8U Expired - Fee Related CN203813760U (en) | 2014-03-27 | 2014-03-27 | Shift frequency divider circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103905034A (en) * | 2014-03-27 | 2014-07-02 | 四川和芯微电子股份有限公司 | Shifting frequency divider circuit |
| CN103905035A (en) * | 2014-03-27 | 2014-07-02 | 四川和芯微电子股份有限公司 | Shifting frequency divider circuit |
-
2014
- 2014-03-27 CN CN201420143546.8U patent/CN203813760U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103905034A (en) * | 2014-03-27 | 2014-07-02 | 四川和芯微电子股份有限公司 | Shifting frequency divider circuit |
| CN103905035A (en) * | 2014-03-27 | 2014-07-02 | 四川和芯微电子股份有限公司 | Shifting frequency divider circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140903 Termination date: 20190327 |