CN203645321U - A foolproof protection circuit - Google Patents
A foolproof protection circuit Download PDFInfo
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- CN203645321U CN203645321U CN201320724558.5U CN201320724558U CN203645321U CN 203645321 U CN203645321 U CN 203645321U CN 201320724558 U CN201320724558 U CN 201320724558U CN 203645321 U CN203645321 U CN 203645321U
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Abstract
The utility model relates to a protection circuit, and discloses a foolproof protection circuit. The foolproof protection circuit of the utility model comprises a control pin, a first control circuit, a second control circuit, a switch circuit and a power supply. The switch circuit is a power supply switch. The first control circuit comprises two input terminals and one output terminal. When high level signals are input through the two input terminals of the first control circuit, the output terminal outputs low level signals; When a high level signal and a low level signal are respectively input through the two input terminals of the first control circuit, the output terminal outputs high level signals; The control pin is connected with both one fixing metal probe of a test clamp and one input terminal of the first control circuit; The switch circuit is disconnected when the second control circuit receives low level signals output by the first control circuit;. otherwise, the switch circuit is connected. Compared with foolproof protection circuits in the prior art, the foolproof protection circuit of the utility model can conveniently prevent burnout of tested products (e.g., chips) due to incorrect placing.
Description
Technical field
The utility model relates to chip detection technology, particularly the protective circuit in chip detection.
Background technology
Current chip, the symmetric design that integrated circuit modules adopts similar square or rectangular more, this design cannot be profile the first placement of foot of Direct Recognition chip or integrated circuit modules.Conventionally adopt in the package surface of product and identify by printing tag, but this method need carefully be checked product surface silk-screen, also need to use magnifying glass for the less device of encapsulation.
This back end test that produces line with regard to giving is made troubles.Conventionally produce line and can, for a certain production test fixture, product be put into fixture, connect peripheral circuit by fixture and test.Distribute than the product of comparatively dense for pin, normally adopt very accurate metal probe to be connected with product.Because product design adopts symmetric design, surperficial silk-screen is difficult for again checking, so can be because operating personnel's carelessness puts back product in a lot of situation.And power supply is connected to product by metal probe, and power supply is a direct power supply, therefore, if module direction is placed mistake, be not symmetric design because the pin of product distributes so, so power supply will be connected on other pins, easily burn product.
It is anti-mostly current more protective circuit is to prevent that power supply from connecing.Fool proof protection major part for chip or integrated circuit modules product is the design for product design.
Utility model content
The purpose of this utility model is to provide a kind of fool proof protective circuit, while making to avoid easily product (as the chip) mistake of test to place, is burnt.
For solving the problems of the technologies described above, the utility model provides a kind of fool proof protective circuit, comprises: control pin, first control circuit, second control circuit, switching circuit and power supply;
Wherein, described switching circuit is mains switch;
Described first control circuit comprises two inputs and an output; Described output outputs signal to described second control circuit according to the signal of two input inputs;
When the equal input high level signal of two inputs of described first control circuit, described output output low level signal; When an input input high level signal of described first control circuit, another input input low level signal, described output output high level signal;
Described control pin is all connected with an input of a fixing metal probe of test fixture, described first control circuit; The output of described first control circuit is connected with the input of described second control circuit; The output of described second control circuit is connected with the first port of described switching circuit; The second port, the 3rd port of described switching circuit are connected with the positive and negative electrode of described power supply respectively;
Described second control circuit disconnects described switching circuit while receiving the low level signal of described first control circuit output; Switching circuit described in conducting when described second control circuit receives the high level signal of described first control circuit output.
The utility model execution mode in terms of existing technologies, when test chip is correctly placed, a fixing metal probe of test fixture is connected with the ground pin of test chip, simultaneously, this fixing metal probe is connected with control pin, like this, and the input input low level signal of the first control circuit being connected with control pin, another input input high level signal, the output output high level signal of first control circuit is to second control circuit.Only have the signal of input second control circuit while being high level signal, second control circuit just conducting output low level signal to switching circuit.Only just conducting in the time of input low level signal of switching circuit, i.e. turn-on power switch, power turn-on, can test chip.When test chip mistake is placed, above-mentioned fixing metal probe is not connected with the ground pin of test chip, the equal input high level signal of two inputs of first control circuit, and like this, the output output low level signal of first control circuit is to second control circuit.The signal of input second control circuit is while being low level signal, second control circuit cut-off, and its output is high level, the first port of switching circuit is high level.When the first port of switching circuit is high level, switching circuit disconnects, i.e. disconnecting power switch, and power supply is disconnected, and makes to avoid the chip of test to be burnt.
In addition, also comprise delay circuit.Delay circuit is used for preventing power supply spike.
In addition, delay circuit also comprises the first resistance, for the protection of first control circuit.
In addition, second control circuit comprises the 3rd resistance, for the protection of second control circuit.
In addition, switching circuit also comprises the 4th resistance, for the protection of switching circuit.
In addition, also comprise load, for the protection of power supply.
Brief description of the drawings
Fig. 1 is according to the structural representation of the fool proof protective circuit of the utility model the first execution mode;
Fig. 2 is according to the correct implementation schematic diagram of placing of the test chip in the utility model the first execution mode;
Fig. 3 is the implementation schematic diagram of placing according to the test chip mistake in the utility model the first execution mode;
Fig. 4 is according to the structural representation of the fool proof protective circuit of the utility model the second execution mode.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing, each execution mode of the present utility model is explained in detail.But, persons of ordinary skill in the art may appreciate that in the each execution mode of the utility model, in order to make reader understand the application better, many ins and outs are proposed.But, even without these ins and outs and the many variations based on following execution mode and amendment, also can realize the each claim of the application technical scheme required for protection.
The first execution mode of the present utility model relates to a kind of fool proof protective circuit, as shown in Figure 1, comprises and controls pin, first control circuit, delay circuit, second control circuit, switching circuit, load and power supply.
Wherein, switching circuit is mains switch.
Specifically, first control circuit comprises two inputs and an output, and output is according to the signal output signal of two input inputs.Wherein, when the equal input high level signal of two inputs of first control circuit, output output low level signal; When an input input high level signal of first control circuit, another input input low level signal, output output high level signal.
Controlling pin is connected with a fixing metal probe (not shown) of test fixture; An input of first control circuit is connected with control pin, and another input is connected with other function pin of test chip (this input input high level signal), and the output of first control circuit is connected with the input of delay circuit; The output of delay circuit is connected with the input of second control circuit; The output of second control circuit is connected with the first port of switching circuit; The second port of switching circuit is connected with the positive pole of power supply, and the 3rd port is connected with one end of load; The other end of load is connected with the negative pole of power supply.Wherein, load is for the protection of power supply.
Second control circuit is by the control to switching circuit, and in the time that the signal of first control circuit output is low level signal, disconnecting power switch, cuts off the electricity supply; In the time that the signal of first control circuit output is high level signal, turn-on power switch, power turn-on.
Be example taking product to be measured as chip below, be specifically described.In the present embodiment, a ground pin of test chip is drawn as control pin.
When test chip is correctly placed, the control pin of this test chip is connected with a fixing metal probe of test fixture, and this fixing metal probe is connected with the control pin of fool proof protective circuit, and specific implementation as shown in Figure 2.1 is the metal probe on test fixture; 2 is the control pin on the test chip 4 of metal probe connection, the ground pin that this control pin is test chip.When test chip placement direction is correct, 1 is connected to the ground pin of test chip; 3 is on test chip and the pin of 2 pin symmetric positions.
Now, the input input low level signal of the first control circuit being connected with control pin, another input input high level signal, the output output high level signal of first control circuit is to delay circuit.
Delay circuit will export second control circuit to after the high level signal time delay of reception, with the power supply spike of avoiding producing because of the shake of test products.
Conducting when second control circuit receives high level signal, and output low level signal is to switching circuit.
Conducting when switching circuit receives low level signal, i.e. power switch conducts, power turn-on, can test products.
But, when test chip mistake is placed, the control pin of test chip is not connected with the fixing metal probe of above-mentioned test fixture, because this fixing metal probe is connected with control pin, what be connected with control pin is not the ground pin of test chip, but other function pin of test chip, specific implementation is as shown in Figure 3.In the time that test chip direction puts back, metal probe 1 touches pin 3, and this pin 3 is not ground pin.
In this case, the equal input high level signal of two inputs of first control circuit, the output output low level signal of first control circuit is to delay circuit.
Delay circuit will export second control circuit to after the low level signal time delay of reception.
When receiving low level signal, ends second control circuit.
When second control circuit cut-off, the first port in switching circuit is high level, and the second port is also high level, switching circuit cut-off, switching circuit disconnects, i.e. disconnecting power switch, power supply is cut off, and makes to avoid the product of test to place and burnt because of mistake.
In the present embodiment, control pin and be connected with a fixing metal probe of test fixture, in the time that test products is correctly placed, this fixing metal probe is connected with the ground pin of test products, controlling pin is fixing low level, and power switch conducts can test products; In the time that test products mistake is placed, this fixing metal probe is not connected with the ground pin of test products, and controlling pin is not low level, and mains switch disconnects, and avoids test products to be burnt.Like this, just can draw in the fixed position of test products ground pin, be used in conjunction with fixing metal probe, make to avoid easily test products to be burnt, simple to operate, easily realize.
The second execution mode of the present invention relates to a kind of fool proof protective circuit.The second execution mode is the further refinement of the first execution mode.In the second execution mode, the concrete structure of fool proof protective circuit as shown in Figure 4.
In the present embodiment, first control circuit is NAND gate circuit.Output output low level signal when two equal input high level signals of input of NAND gate; When an input input low level signal of NAND gate, another input input high level signal, output output high level signal.
Delay circuit comprises the first resistance and electric capacity; One end of the first resistance is connected with the output of first control circuit, and the other end is connected with the input of second control circuit; Electric capacity one end is connected with the input of second control circuit, other end ground connection.Wherein, the first resistance is for the protection of first control circuit.
Second control circuit comprises NPN type triode, the second resistance and the 3rd resistance; NPN type triode comprises base stage, emitter and collector electrode, the input that base stage is second control circuit, and grounded emitter, current collection is the output of second control circuit very; One end of the second resistance is connected with the base stage of NPN type triode, and the other end is connected with the emitter of NPN type triode; The 3rd one end of resistance R 3 and the output of delay circuit are connected, and the other end is connected with the base stage of NPN type triode.Wherein, the second resistance is for setting up bias voltage intrinsic between NPN type triode when work base stage and emitter.The 3rd resistance is for the protection of second control circuit.
Switching circuit comprises P-MOS pipe and the 4th resistance; P-MOS pipe comprises grid, source electrode and drain electrode; Grid is the first port of switching circuit, and the second port that source electrode is switching circuit drains as the 3rd port of switching circuit; The 4th resistance one end is connected with grid, and the other end is connected with source electrode.
The grid of P-MOS pipe is low level, source electrode while being high level, the conducting of P-MOS pipe, and switching circuit conducting fool proof protective circuit, can test products; But when the grid of P-MOS pipe, source electrode are high level, P-MOS manages cut-off, switching circuit turn-offs fool proof protective circuit, makes to avoid test products to be burnt.Wherein, the 4th resistance is for the protection of switching circuit, and intrinsic bias voltage between grid and source electrode while producing the work of P-MOS pipe.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiment of the utility model, and in actual applications, can do various changes to it in the form and details, and do not depart from spirit and scope of the present utility model.
Claims (10)
1. a fool proof protective circuit, is characterized in that, comprises: control pin, first control circuit, second control circuit, switching circuit and power supply;
Wherein, described switching circuit is mains switch;
Described first control circuit comprises two inputs and an output; Described output outputs signal to described second control circuit according to the signal of two input inputs;
When the equal input high level signal of two inputs of described first control circuit, described output output low level signal; When an input input high level signal of described first control circuit, another input input low level signal, described output output high level signal;
Described control pin is all connected with an input of a fixing metal probe of test fixture, described first control circuit; The output of described first control circuit is connected with the input of described second control circuit; The output of described second control circuit is connected with the first port of described switching circuit; The second port, the 3rd port of described switching circuit are connected with the positive and negative electrode of described power supply respectively;
Described second control circuit disconnects described switching circuit while receiving the low level signal of described first control circuit output; Switching circuit described in conducting when described second control circuit receives the high level signal of described first control circuit output.
2. fool proof protective circuit according to claim 1, is characterized in that, also comprises delay circuit;
Described delay circuit is all connected with described first control circuit, described second control circuit;
The input of described delay circuit receives the signal of described first control circuit output; The output of described delay circuit exports time delayed signal to described second control circuit.
3. fool proof protective circuit according to claim 1, is characterized in that, described first control circuit is NAND gate circuit;
Described not circuit comprises two inputs and an output;
The input of described first control circuit is the input of described NAND gate circuit; The output of described first control circuit is the output of described NAND gate circuit.
4. fool proof protective circuit according to claim 2, is characterized in that, described second control circuit comprises NPN type triode;
Described NPN type triode comprises base stage, emitter and collector electrode;
Described base stage is the input of described second control circuit; Described grounded emitter; The output of the very described second control circuit of described current collection.
5. fool proof protective circuit according to claim 4, is characterized in that, described second control circuit also comprises the second resistance R
2;
One end of described the second resistance is connected with the base stage of described NPN type triode, and the other end is connected with the emitter of described NPN type triode;
Described the second resistance is set up bias voltage intrinsic between described base stage and emitter.
6. fool proof protective circuit according to claim 4, is characterized in that, described second control circuit also comprises the 3rd resistance R
3;
Described the 3rd resistance R
3one end be connected with the output of described delay circuit, the other end is connected with the base stage of described NPN type triode.
7. fool proof protective circuit according to claim 2, is characterized in that, described delay circuit comprises the first resistance R
1and capacitor C;
One end of described the first resistance is connected with the output of described first control circuit, and the other end is connected with the input of described second control circuit;
Described electric capacity one end is connected with the input of described second control circuit, other end ground connection.
8. fool proof protective circuit according to claim 1, is characterized in that, described switching circuit is P-MOS pipe;
Described P-MOS pipe comprises grid, source electrode and drain electrode;
Described grid is the first port of described switching circuit; Described source electrode is the second port of described switching circuit; Described drain electrode is the 3rd port of described switching circuit.
9. fool proof protective circuit according to claim 8, is characterized in that, described switching circuit also comprises the 4th resistance R
4;
Described the 4th resistance one end is connected with described grid, and the other end is connected with described source electrode;
Described the 4th resistance is set up bias voltage intrinsic between described grid and described source electrode.
10. fool proof protective circuit according to claim 1, is characterized in that, also comprises load;
Described load one end is connected with the negative pole of described power supply, and the other end is connected with the 3rd port of described switching circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320724558.5U CN203645321U (en) | 2013-11-15 | 2013-11-15 | A foolproof protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320724558.5U CN203645321U (en) | 2013-11-15 | 2013-11-15 | A foolproof protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203645321U true CN203645321U (en) | 2014-06-11 |
Family
ID=50876542
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320724558.5U Expired - Fee Related CN203645321U (en) | 2013-11-15 | 2013-11-15 | A foolproof protection circuit |
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| Country | Link |
|---|---|
| CN (1) | CN203645321U (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579282A (en) * | 2014-12-16 | 2015-04-29 | 苏州福丰科技有限公司 | Load detection circuit for radio frequency matrix switch |
| CN104767520A (en) * | 2015-03-26 | 2015-07-08 | 苏州锟恩电子科技有限公司 | Radio frequency matrix switch load detection circuit |
| CN108169663A (en) * | 2017-12-28 | 2018-06-15 | 湖南国科微电子股份有限公司 | A kind of pcb board with fool proof debugging interface |
| CN109239575A (en) * | 2018-08-01 | 2019-01-18 | 上海移远通信技术股份有限公司 | A kind of detection device, detection method and automated detection system |
| CN109412134A (en) * | 2018-12-18 | 2019-03-01 | 惠科股份有限公司 | A kind of fool proof circuit, connector and display device |
| CN110378155A (en) * | 2019-06-25 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of server serial port disabling protection circuit, method |
| CN112462166A (en) * | 2020-11-04 | 2021-03-09 | 龙尚科技（上海）有限公司 | Fool-proof detection circuit and clamp |
| CN113067325A (en) * | 2021-03-05 | 2021-07-02 | 山东英信计算机技术有限公司 | Chip protection circuit and board card |
-
2013
- 2013-11-15 CN CN201320724558.5U patent/CN203645321U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579282A (en) * | 2014-12-16 | 2015-04-29 | 苏州福丰科技有限公司 | Load detection circuit for radio frequency matrix switch |
| CN104767520A (en) * | 2015-03-26 | 2015-07-08 | 苏州锟恩电子科技有限公司 | Radio frequency matrix switch load detection circuit |
| CN108169663A (en) * | 2017-12-28 | 2018-06-15 | 湖南国科微电子股份有限公司 | A kind of pcb board with fool proof debugging interface |
| CN109239575A (en) * | 2018-08-01 | 2019-01-18 | 上海移远通信技术股份有限公司 | A kind of detection device, detection method and automated detection system |
| CN109412134A (en) * | 2018-12-18 | 2019-03-01 | 惠科股份有限公司 | A kind of fool proof circuit, connector and display device |
| CN110378155A (en) * | 2019-06-25 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of server serial port disabling protection circuit, method |
| CN112462166A (en) * | 2020-11-04 | 2021-03-09 | 龙尚科技（上海）有限公司 | Fool-proof detection circuit and clamp |
| CN113067325A (en) * | 2021-03-05 | 2021-07-02 | 山东英信计算机技术有限公司 | Chip protection circuit and board card |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140611 Termination date: 20201115 |