CN203587987U - Novel multi-channel timing instrument - Google Patents
Novel multi-channel timing instrument Download PDFInfo
- Publication number
- CN203587987U CN203587987U CN201320829425.4U CN201320829425U CN203587987U CN 203587987 U CN203587987 U CN 203587987U CN 201320829425 U CN201320829425 U CN 201320829425U CN 203587987 U CN203587987 U CN 203587987U
- Authority
- CN
- China
- Prior art keywords
- signal
- control signal
- output terminal
- receiving end
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Electric Clocks (AREA)
Abstract
The utility model relates to a novel multi-channel timing instrument. The novel multi-channel timing instrument comprises a signal conditioner, a writing control signal generator, a signal storage, a time storage, a clock signal generator, a counter, an I/O (Input/Output) interface and a computer, wherein the output end of the signal conditioner is connected with the input end of the writing control signal generator; the trigger signal output end of the writing control signal generator is connected with the trigger signal information input end of the signal storage; the writing control signal output end of the writing control signal generator is connected with the writing control signal receiving end of the signal storage and the writing control signal receiving end of the time storage. By adopting the novel multi-channel timing instrument, the flying time of fragments can be measured continuously in each of multiple channels. Meanwhile, the channel quantity and measuring time can be increased and prolonged as required. The stability and reliability of the multi-channel timing instrument are improved, and the testing accuracy is increased.
Description
Technical field
The utility model relates to a kind of electronic gauge, is specifically related to a kind of novel multi-channel calculagraph.
Background technology
The calculagraph that the flight time of fragmentation and velocity survey are used at present mainly contains single channel calculagraph, dual timer and Multipath timing instrument.Usually, the flight time and the speed (tens even up to a hundred) that when measuring flight time of fragmentation and speed, all need to measure a plurality of fragmentations in different directions and same direction, existing calculagraph, no matter be single channel calculagraph, dual timer or Multipath timing instrument, each passage once can only be measured the flight time of a fragmentation, also be that the party makes progress flight time of the fastest fragmentation of flying speed, data capture amount is extremely low, is difficult to meet test request.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of novel multi-channel calculagraph, can carry out the flight time that hyperchannel and each passage all can continuous coverage fragmentations, meets and measures requirement.
The technical scheme that the utility model solves the problems of the technologies described above is as follows: a kind of novel multi-channel calculagraph, comprise signal conditioner, write control signal generator, signal storage, time memory, clock-signal generator, counter, I/O interface, computing machine
The output terminal of described signal conditioner is connected with the input end of described write control signal generator;
The trigger pip output terminal of described write control signal generator is connected with the trigger pip information input terminal of signal storage;
Described write control signal generator write control signal output terminal be connected with the write control signal receiving end of described signal storage and the write control signal receiving end of time memory respectively;
The clock pulse signal output terminal of described clock-signal generator is connected with the pulsed signal end of the pulsed signal end sum counter of described write control signal generator respectively;
The carry signal output terminal of described counter is connected with the carry signal receiving end of described write control signal generator;
The temporal information output terminal of described counter is connected with the temporal information receiving end of described time memory;
The marking signal output terminal of described time memory and the marking signal output terminal of signal storage are connected with the marking signal receiving end of described computing machine by I/O interface;
The memory read control signal output terminal of described computing machine is connected with the memory read control signal receiving end of described signal storage and the memory read control signal receiving end of time memory respectively by I/O interface;
The reset signal output terminal of described computing machine is connected with the reset signal receiving end of the reset signal receiving end of described counter, the reset signal receiving end of time memory and signal storage respectively by I/O interface;
The trigger pip information output of described signal storage and the temporal information output terminal of time memory are connected with the internal memory of described computing machine by I/O interface.
The beneficial effects of the utility model are: a kind of novel multi-channel calculagraph of the utility model can carry out the flight time that hyperchannel and each passage all can continuous coverage fragmentations, can as required, increase port number and Measuring Time simultaneously; Stability and the reliability of novel multi-channel calculagraph have arrived raising, and measuring accuracy is improved.
On the basis of technique scheme, the utility model can also be done following improvement.
Further, in described calculator memory, be provided with a counting memory block.
Further, described computing machine is connected with described I/O interface by IEEE1284 interface.
Further, described clock-signal generator is constant-temperature crystal oscillator.
Further, described counter is 16 2 system Counters can synchronously removing with carry end.
Further, described time memory is 16 * 1024, is with and independently reads and writes pointer and empty zone bit, purgeable pushup storage.
Further, described signal storage is c position * 1024, band independent read-write pointer and empty zone bit, purgeable pushup storage, and the figure place c of described storer is consistent with the port number of calculagraph.
Accompanying drawing explanation
Fig. 1 is the circuit module block diagram of a kind of novel multi-channel calculagraph of the utility model.
In accompanying drawing, the information of each label representative is as follows:
1, shot break pick device and fragmentation position signalling pick device, 101, fragmentation position signalling, 2, novel multi-channel calculagraph, 201, the trigger pip of signal conditioner, 202, the trigger pip information of write control signal generator, 203, the write control signal of write control signal generator, 204, the clock signal of clock-signal generator output, 205, counter output carry signal, 206, the temporal information of counter output, 207, the marking signal of storer, 208, memory read control signal, 209, IEEE1284 interface, 210, the trigger pip information of signal storage output, 211, the time signal information of time memory output, 212, reset signal.
Embodiment
Below in conjunction with accompanying drawing, principle of the present utility model and feature are described, example, only for explaining the utility model, is not intended to limit scope of the present utility model.
As shown in Figure 1, a kind of novel multi-channel calculagraph, comprise signal conditioner, write control signal generator, signal storage, time memory, clock-signal generator, counter, I/O interface, computing machine, the output terminal of described signal conditioner is connected with the input end of described write control signal generator; The trigger pip output terminal of described write control signal generator is connected with the trigger pip information input terminal of signal storage; Described write control signal generator write control signal output terminal be connected with the write control signal receiving end of described signal storage and the write control signal receiving end of time memory respectively; The clock pulse signal output terminal of described clock-signal generator is connected with the pulsed signal end of the pulsed signal end sum counter of described write control signal generator respectively; The carry signal output terminal of described counter is connected with the carry signal receiving end of described write control signal generator; The temporal information output terminal of described counter is connected with the temporal information receiving end of described time memory; The marking signal output terminal of described time memory and the marking signal output terminal of signal storage are connected with the marking signal receiving end of described computing machine by I/O interface; The memory read control signal output terminal of described computing machine is connected with the memory read control signal receiving end of described signal storage and the memory read control signal receiving end of time memory respectively by I/O interface; The reset signal output terminal of described computing machine is connected with the reset signal receiving end of the reset signal receiving end of described counter, the reset signal receiving end of time memory and signal storage respectively by I/O interface; The trigger pip information output of described signal storage and the temporal information output terminal of time memory are connected with the internal memory of described computing machine by I/O interface.
In the utility model course of work, first novel multi-channel calculagraph 2 is connected with fragmentation position signalling pick device 1 with shot break pick device, in Fig. 1:
101 is the fragmentation position signalling of shot break pick device and the perception of fragmentation position signalling pick device;
201 is the trigger pip that fragmentation position signalling 101 forms after signal conditioner conditioning, and amplitude is Transistor-Transistor Logic level, the low level signal that width is 1us;
202 for after arriving when trigger pip 201, when the rising edge of next clock pulse signal 204 arrives, the TTL low level signal of the clock period width being produced by write control signal generator is (when the frequency of the clock signal 204 of clock-signal generator output is 10MHz, its width is 0.1us), both trigger pip information;
203 for after trigger pip 201 arrivals or low 16 digit counters produced the TTL high level signal of a clock period width of carry signal 205(), when the negative edge of next clock pulse signal 204 arrives, the TTL low level signal of the half clock period width being produced by write control signal generator is (when the frequency of the clock signal 204 of clock-signal generator output is 10MHz, its width is 0.05us), both write control signals;
204 clock pulse signals for clock-signal generator output, frequency is 10MHz;
205 is the carry signal that low 16 digit counters produce, the TTL high level signal of a clock period width of exporting when low 16 digit counter countings reach maximal value;
206 is the number of time clock of its record of low 16 digit counters outputs, i.e. temporal information, with the product in cycle of clock signal 204, is the time value of new type multipath calculagraph hardware components record;
207 is the marking signal of storer (signal storage and time memory), and when this signal is TTL low level, representing has trigger pip information and temporal information or have carry signal information in storer;
208 is memory read control signal;
209 is IEEE1284 interface;
The 210 trigger pip information for signal storage output;
The 211 time signal information for time memory output;
212 is (zero clearing) signal that resets, Low level effective.
In the present embodiment, clock-signal generator adopts the constant-temperature crystal oscillator of high stability, and the frequency of the clock signal 204 of its output is 10MHz, and amplitude is Transistor-Transistor Logic level, the square-wave signal that dutycycle is 50%.
Counter is 16 2 system Counters can synchronously removing with carry end, and when clock frequency is 10MHz, maximum age time is 6.5536ms, every 6.5536ms, produces a carry signal 205.In described calculator memory, be provided with a counting memory block simultaneously, in calculator memory, open up a memory block (supposing that the numeral in this memory block represents with a), computing machine often detects after the carry signal 205 of low 16 digit counter outputs, digital a in this memory block is added to 1, as the number of the pulse signal of the clock signal 204 of low 16 digit counter records represents with b, time value t=a * 6553.6+b (us) that novel multi-channel calculagraph records.Adopt in theory the method, the maximum age time of calculagraph is endless.
Time memory is 16 * 1024, the independent read-write of band pointer (read pointer and write pointer are independent) and empty zone bit, purgeable pushup storage;
Signal storage is c position * 1024, the independent read-write of band pointer (read pointer and write pointer are independent) and empty zone bit, purgeable pushup storage.The figure place c general consistent with the port number of calculagraph (when port number is less) of storer, when port number is more, in order to reduce the figure place (being mainly in order to reduce the quantity of hardware) of storer, can adopt zonal coding technology, for example, when port number is 64, if do not adopted zonal coding technology, the figure place c of signal storage should be 64, if 64 trigger pips 201 are divided into 8 districts, in each district, have 8 trigger pips, only needing 16(c is 16) position a signal storage just can meet the demands.The port number that adopts in theory the method design calculagraph is no maximum restriction.
The detection method of the carry signal 204 of counter is: the temporal information 211 in the time memory that computing machine reads by IEEE1284 interface 209 and I/O interface is 0, is the carry signal 204 that low 16 digit counters produce.
The principle of work of a kind of novel multi-channel calculagraph of the utility model is: after novel multi-channel calculagraph 2 powers up, by computing machine, by IEEE1284 interface and I/O interface, send reset (zero clearing) signal (Low level effective) 212, to low 16 digit counters, time memory and signal storage zero clearing, after reset signal 212 finishes, (when the rising edge of reset signal 212 arrives) low 16 digit counters start counting, when the input end of novel multi-channel calculagraph 2 receives after fragmentation position signalling 101, after signal conditioner conditioning, exporting an amplitude is Transistor-Transistor Logic level, width is that the figure place of trigger pip 201 of low level trigger pip 201(signal conditioner output of 1us is identical with the port number of multi channel timing instrument, no matter be that passage at any time has 101 inputs of fragmentation position signalling, it is Transistor-Transistor Logic level that the corresponding position of the output terminal of signal conditioner all produces an amplitude, width is the low level trigger pip 201 of 1us, therefore the temporal resolution of same passage continuous acquisition fragmentation signal is 1us), when write control signal generator receives after trigger pip 201, when the rising edge of next clock pulse signal 204 arrives, produce the TTL low level signal 202(of a clock period width when the frequency of the clock signal 204 of clock-signal generator output is 10MHz, its width is 0.1us), both trigger pip information, when the negative edge of this clock pulse signal 204 arrives, produce the TTL low level signal of half clock period width, write control signal 203, under the effect of write control signal 203, the number of the time clock of its record of low 16 digit counters outputs during by trigger pip information 202 and trigger pip 201 arrival, temporal information 206 is stored in respectively in signal storage and time memory, when reaching maximal value, export low 16 digit counter countings the TTL high level carry signal 205 of a clock period width, when write control signal generator receives after the carry signal 205 of low 16 digit counter outputs, when the negative edge of next clock pulse signal 204 arrives, the TTL low level signal that produces half clock period width, write control signal 203, under the effect of write control signal 203, the number of the time clock of its record of low 16 digit counters outputs during by trigger pip information 202 and trigger pip 201 arrival, temporal information 206(is low level) be stored in respectively in signal storage and time memory, computing machine is by the marking signal 207 of IEEE1284 interface 209 and I/O interface read memory (signal storage and time memory), when the marking signal 207 of storer (signal storage and time memory) is TTL low level, representing has trigger pip information and temporal information or has carry signal information in storer, computing machine is by IEEE1284 interface and a TTL low level signal of I/O interface output, it is memory read control signal 208, under the effect of memory read control signal 208, signal storage and time memory are respectively by trigger pip information 210 and temporal information 211 outputs, then computing machine is by IEEE1284 interface and I/O interface, trigger pip information 210 and temporal information 211 are read in to calculator memory, computing machine is analyzed judgement to the trigger pip information 210 of reading in and temporal information 211, if the carry signal 205 of low 16 digit counters, a high position for counter is added to 1, otherwise, further trigger pip information is analyzed, the time value when input end of fragmentation position signalling 101 is arrived with this signal is corresponding one by one, has realized hyperchannel, the flight time that each passage all can continuous coverage fragmentation.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.
Claims (7)
1. a novel multi-channel calculagraph, is characterized in that: comprise signal conditioner, write control signal generator, signal storage, time memory, clock-signal generator, counter, I/O interface, computing machine,
The output terminal of described signal conditioner is connected with the input end of described write control signal generator;
The trigger pip output terminal of described write control signal generator is connected with the trigger pip information input terminal of signal storage;
Described write control signal generator write control signal output terminal be connected with the write control signal receiving end of described signal storage and the write control signal receiving end of time memory respectively;
The clock pulse signal output terminal of described clock-signal generator is connected with the pulsed signal end of the pulsed signal end sum counter of described write control signal generator respectively;
The carry signal output terminal of described counter is connected with the carry signal receiving end of described write control signal generator;
The temporal information output terminal of described counter is connected with the temporal information receiving end of time memory;
The marking signal output terminal of described time memory and the marking signal output terminal of signal storage are connected with the marking signal receiving end of described computing machine by I/O interface;
The memory read control signal output terminal of described computing machine is connected with the memory read control signal receiving end of described signal storage and the memory read control signal receiving end of time memory respectively by I/O interface;
The reset signal output terminal of described computing machine is connected with the reset signal receiving end of the reset signal receiving end of described counter, the reset signal receiving end of time memory and signal storage respectively by I/O interface;
The trigger pip information output of described signal storage and the temporal information output terminal of time memory are connected with the internal memory of described computing machine by I/O interface.
2. a kind of novel multi-channel calculagraph according to claim 1, is characterized in that: in described calculator memory, be provided with a counting memory block.
3. a kind of novel multi-channel calculagraph according to claim 1 and 2, is characterized in that: described computing machine is connected with described I/O interface by IEEE1284 interface.
4. according to profit, require a kind of novel multi-channel calculagraph described in 1 or 2, it is characterized in that: described clock-signal generator is constant-temperature crystal oscillator.
5. a kind of novel multi-channel calculagraph according to claim 1 and 2, is characterized in that: described counter is 16 2 system Counters can synchronously removing with carry end.
6. a kind of novel multi-channel calculagraph according to claim 1 and 2, is characterized in that: described time memory is 16 * 1024, is with and independently reads and writes pointer and empty zone bit, purgeable pushup storage.
7. a kind of novel multi-channel calculagraph according to claim 1 and 2, it is characterized in that: described signal storage is c position * 1024, band independent read-write pointer and empty zone bit, purgeable pushup storage, and the figure place c of described storer is consistent with the port number of calculagraph.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320829425.4U CN203587987U (en) | 2013-12-16 | 2013-12-16 | Novel multi-channel timing instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320829425.4U CN203587987U (en) | 2013-12-16 | 2013-12-16 | Novel multi-channel timing instrument |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203587987U true CN203587987U (en) | 2014-05-07 |
Family
ID=50585880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320829425.4U Expired - Fee Related CN203587987U (en) | 2013-12-16 | 2013-12-16 | Novel multi-channel timing instrument |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203587987U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107045278A (en) * | 2016-12-26 | 2017-08-15 | 河南思维信息技术有限公司 | A kind of multi channel timing device |
-
2013
- 2013-12-16 CN CN201320829425.4U patent/CN203587987U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107045278A (en) * | 2016-12-26 | 2017-08-15 | 河南思维信息技术有限公司 | A kind of multi channel timing device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101685135B (en) | Test device and test method for testing circuit board | |
| CN103676622B (en) | A kind of high-precision positive and negative time interval measurement method and device | |
| CN103954903B (en) | A kind of can real-time resolving multi-mode output circuit test system | |
| CN104991118B (en) | A kind of high-resolution alien frequencies signal frequency measuring system and measuring method | |
| CN102928677A (en) | Nano pulse signal acquiring method | |
| CN102916914A (en) | Data receiving and processing system of analog front end | |
| CN102368076B (en) | Card feeding speed testing method and device | |
| CN203587987U (en) | Novel multi-channel timing instrument | |
| CN1963551A (en) | High resolution time stamps for periodic samples | |
| CN103955255A (en) | Accurate measurement system based on FPG binary input event, and method thereof | |
| CN104111481B (en) | Synchronous clock phase difference measurements system and method | |
| CN203929885U (en) | Based on FPGA etc. precision frequency testing system | |
| CN106468733A (en) | A kind of monitoring system of extra-high voltage Lightning Incoming Wave and its monitoring method | |
| CN107621570A (en) | A kind of digital frequency meter | |
| CN103809001A (en) | Digital phosphor oscilloscope pretrigger device | |
| CN100458711C (en) | Data pickup processing method for logic analyzer and apparatus thereof | |
| CN103744094B (en) | Based on the navigational system difference of injection time measurement module of CPLD combination | |
| CN201107355Y (en) | Time synchronization error measuring circuit based on CPLD technology | |
| CN107643116B (en) | Water meter rotating speed calibration method, system and device | |
| CN106019395B (en) | A kind of electrical method receiving processing system and its method based on Correlation Identification | |
| CN103885716A (en) | Touch screen line-drawing testing method and line-drawing speed measurement device | |
| CN107491009A (en) | A kind of angular transducer signal synchronous collection method | |
| CN106019924A (en) | FPGA-based counting type high-precision time interval measuring system | |
| CN202771418U (en) | Highly precise recording device of network card and capable of recording receiving time | |
| CN206002858U (en) | A kind of attribute High-precision time interval measurement device based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140507 Termination date: 20161216 |