CN203563009U - Circuit for compensating nonlinear capacitance to reduce harmonic distortion as mush as possible - Google Patents
Circuit for compensating nonlinear capacitance to reduce harmonic distortion as mush as possible Download PDFInfo
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- CN203563009U CN203563009U CN201320761130.8U CN201320761130U CN203563009U CN 203563009 U CN203563009 U CN 203563009U CN 201320761130 U CN201320761130 U CN 201320761130U CN 203563009 U CN203563009 U CN 203563009U
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Abstract
Provided is a circuit for compensating nonlinear capacitance to reduce harmonic distortion as mush as possible. Stray capacitance of a transistor node can be improved, and the circuit is independent from the used process technology. Preferably, a pair of diodes with effect in inverse proportion is provided for a parasitic diode in an integrated circuit during operation, and accordingly the stray capacitance of a transistor in the circuit is linearized. If the diodes do not exist, different input signals can cause changing of the stray capacitance, so that harmonic distortion happens to the circuit. The utility model further provides a complementation transistor which forms another kind of stray capacitance which is basically opposite to the stray capacitance in the transistor. In addition, according to the proportion of different elements, the two methods can be combined, for example, the complementation transistor technology is used, and meanwhile an extra diode can be added.
Description
Technical field:
The present invention relates to transistorized parasitic capacitance, particularly following the tracks of and keep in (T/H) circuit or other circuit of combining with T/H circuit.More specifically, the present invention relates to minimize circuit and the method for nonlinear capacitance in T/H and other circuit.
Background technology:
T/H circuit for example, for keep the output of a constant amplitude according to input, in analogue-to-digital converters (ADC).Therefore, T/H circuit may be had relatively high expectations to system accuracy, comprises the precision of any data that created by ADC.This T/H circuit is usually operated in two kinds of different patterns, i.e. " tracing mode " and " Holdover mode ".Under tracing mode, T/H circuit is generally as following by inputting voltages device.Under Holdover mode, T/H circuit keeps this input signal as output signal when time Holdover mode starts.T/H circuit switches between pattern by simple trigger conventionally.When T/H circuit is triggered back tracing mode, the output of T/H circuit reverts to input voltage.
There are many known T/H circuit.For example, a simple T/H circuit can be by being used metal-oxide semiconductor (MOS) (MOS) transistor and an electric capacity to create.A shortcoming of this simple MOS transistor T/H circuit is: transistorized parasitic capacitance is along with the non-linear to voltage at transistor junction two ends changes.Parasitic capacitance is especially larger on circuit impact during tracing mode, and the now variation of transistor turns and input voltage causes capacitance variations.The remainder of the variation of parasitic capacitance and MOS transistor T/H circuit influences each other, and causes that the output of T/H circuit produces harmonic distortion.
The method of known solution parasitic capacitance problems is to provide an extra circuit, makes parasitic diode keep a constant reverse bias.Some T/H circuit adopt operational amplifier to prevent the voltage difference at transistor junction place, thereby make parasitic junction capacitance linear change.But this method not only needs more space, cost higher, and circuit that can be is in this way also restricted.
In view of the foregoing, need to provide a kind of simple, low cost particularly in simple T/H circuit, can make the linearizing circuit of transistorized parasitic capacitance.
Also needing to provide does not need to use special process technology and can make the linearizing circuit of transistorized parasitic capacitance.
In addition, also need to provide a kind of for compensating non-linear electric capacity to reduce the method for T/H circuit and the distortion of non-T/H circuit harmonizing wave as far as possible.
Summary of the invention:
Therefore, first object of the present invention is to provide a kind of simple, low cost and particularly in simple T/H circuit, can makes the linearizing circuit of transistorized parasitic capacitance.
Second object of the present invention is to provide one not to be needed to use special process technology and can make the linearizing circuit of transistorized parasitic capacitance.
The 3rd object of the present invention be to provide a kind of for compensating non-linear electric capacity to reduce the method for T/H circuit and the distortion of non-T/H circuit harmonizing wave as far as possible.
Technical solution of the present invention:
According to these and other objects of the present invention, provide a kind of simple to operate, cost is low and be independent of special process technology can make the linearizing circuit of transistorized parasitic capacitance.In an example of the present invention, diode is coupling in respectively between bias voltage and this transistorized source electrode, drain electrode.Additional diode makes parasitic capacitance linearisation, thereby makes total capacitance keep relatively constant.In another example, two complementary transistors are coupling in together (one is p raceway groove, and one is n raceway groove), and each transistorized parasitic capacitance makes another transistorized parasitic capacitance linearisation.
Contrast patent documentation: CN2101345U passive suppressor for source current harmonic distortion 091215965.0
Accompanying drawing explanation:
Fig. 1 is the rough schematic view of a kind of typical tracking and holding circuit;
Fig. 2 is a typical plot of circuit working parameter in Fig. 1;
Fig. 3 is the cutaway view of the integrated circuit structure of a traditional n channel mosfet;
Fig. 4 is the curve chart that in Fig. 1 circuit, parasitic capacitance changes with transistor junction both end voltage;
Fig. 5 is the linearizing tracking of a kind of parasitic capacitance that adopts operational amplifier to make transistor junction and holding circuit;
Fig. 6 is the example that principle according to the present invention makes the linearizing tracking of parasitic capacitance and holding circuit;
Fig. 7 is the curve chart of the electric capacity that obtains of the comprehensive transistor parasitic capacitance of principle according to the present invention and building-out capacitor with change in voltage;
Fig. 8 is the cutaway view of the n channel mosfet integrated circuit structure of a compensate for parasitic capacitance obtaining of principle according to the present invention;
Fig. 9 is another example that principle according to the present invention makes the linearizing tracking of parasitic capacitance and holding circuit.
Embodiment:
Fig. 1 is the rough schematic view of a kind of typical tracking and holding circuit.As shown in Figure 1, T/H circuit 100 adopts metal-oxide semiconductor (MOS) (MOS) transistor 102 and electric capacity 104.Resistance 106 represents input source impedance.MOS transistor 102 also comprises parasitic junction capacitance in drain electrode and source electrode, in figure, with PJC diode 112 and 114, represents respectively.In figure, PJC diode 112 and 114 use dashed rectangle illustrate, they have represented that the pn of MOS transistor 102 ties.
In ideal conditions, an input signal V
iNcause inputting the change in voltage at node 108 places.When the grid of MOS transistor 102 is coupled to the voltage that is greater than input node 108 place's voltages, MOS transistor 102 is just as a resistance--and allow electric capacity 104 to carry out charging and discharging, make the output V at output node 110 places
oUTwith input signal V
iNchange (being tracing mode).When the grid of MOS transistor 102 is coupled to the voltage that is less than input node 108 place's voltages, MOS transistor 102 is ended--by input signal V
iNisolate with electric capacity 104 and output node 110, therefore the output V at output node 110 places
oUTremain on switch mode V before
iNvalue (being Holdover mode).Therefore, the signal V of MOS transistor 102 grids
tRIGGERas a triggering signal, operating between tracing mode and Holdover mode of T/H circuit 100 switched.
Fig. 2 shows a desirable operation of T/H circuit 100.With reference to Fig. 2, input signal V
iN200 along with the time changes.Within the desirable time, triggering signal V
tRIGGER202 switch above-mentioned input signal V simply
iN200.As triggering signal V
tRIGGER202 excess input signal V
iN200 o'clock, output signal V
oUT204 follow input signal V
iN200 change, as triggering signal V
tRIGGER202 lower than input signal V
iN200 o'clock, output signal V
oUT204 keep input signal V
iN200 last value is constant.
But typical operation is undesirable, as mentioned above, due to the parasitic capacitance of MOS transistor 102, in Fig. 1, the output of T/H circuit 100 is subject to the impact of harmonic distortion.These problems more bother in integrated T/H circuit.
Fig. 3 shows the cutaway view 300 of a traditional n NMOS N-channel MOS N field-effect transistor (MOSFET), and it can be used as the MOS transistor 102 in Fig. 1.With reference to Fig. 3, n+ district 302 and 304 is diffused or is injected into p-type silicon substrate 306.Oxide skin(coating) 308 is on p-type substrate 306.Thin oxide skin(coating) 308 is separation with p-type silicon substrate 306 by the polysilicon gate of MOSFET300 320.Metal end 330 and 340 is coupled to respectively n+ district 302 and 304.
The terminal 330 or 340 that is connected to n+ district 302 or 304 provides the majority carrier of MOSFET300, thereby be conventionally designated as source electrode (S), and one end is designated as drain electrode (D) in addition, although 330 and 340 definite source electrode and drain electrodes in Fig. 3, the two can exchange.Between corresponding MOSFET300 source electrode and drain electrode n+ district 302 and 304, it is the passage 310 of p-type substrate 306
In normal operation, grid 320 produces electric field by the passage 310 between source electrode n+ district 302 and drain electrode n+ district 304, controls the electric current flowing through between source terminal 330 and drain terminal 340.This realizes by apply a voltage at grid 320.The common coupling grounding of substrate 306, with the pn knot of avoiding forming because of forward bias.
In Fig. 3, between parasitic capacitance n+ district 302 of MOSFET300 and the p-type substrate 306 of ground connection, form.Similarly, between another parasitic capacitance n+ district 304 and the p-type substrate 306 of ground connection, form.
Obviously, these parasitic capacitances change with the voltage at the two poles of the earth separately conventionally.Fig. 4 is a curve chart, and it illustrates that drain electrode-substrate or source electrode-substrate parasitic junction capacitance change with the variation of reverse bias voltage separately.
Turn back in Fig. 1, as mentioned above, the parasitic junction capacitance of voltage variable is represented by PJC diode 112 and 114.Referring again to the operation of T/H circuit 100 in Fig. 1, when MOS transistor 102(is as triggering signal V
tRIGGERexcess input signal V
iN) during conducting circuit in tracing mode, the input signal V at input node 108 places
iNmake the change in voltage at PJC diode 112 and 114 two ends, the parasitic junction capacitance being represented by PJC diode 112 and 114 causing changes.The change in voltage of parasitic junction capacitance interacts with the source impedance being represented by resistance 106, causes the output voltage V at output node 110 places
oUTthere is harmonic distortion.
In order to compensate the change in voltage of parasitic junction capacitance, some circuit adopt operational amplifier (amplifier) to prevent the change in voltage of drain electrode-substrate and source electrode-substrate crystal duct ligation.
Fig. 5 shows such T/H circuit 500, and operational amplifier 520 is by preventing the voltage official post parasitic junction capacitance linearisation of transistor junction.But the anode that in Fig. 5, T/H circuit 500 shortcoming is PJC diode 512 and 514 must be connected to amplifier 520.Such requirement has limited the application of sort circuit.There is the CMOS technique of two kinds of fundamental types, i.e. n trap and p trap.For a n channel transistor, the CMOS of n trap produces a p-type substrate being connected with whole integrated circuit (being other circuit element).P-type substrate is n channel transistor " anode ".Equally, p trap CMOS produces a p-type trap in N-shaped substrate.
N channel transistor by adding n+ district to form in p-type trap.P-type trap in n channel transistor is connected with whole integrated circuit.Therefore, being connected with " anode " of n channel transistor is everlasting in p trap CMOS realizes, rather than n trap CMOS.Similarly, for p channel transistor, being connected with its " anode " is everlasting in n trap CMOS realizes, rather than p trap CMOS.Another restriction of T/H circuit 500 in Fig. 5 is in an integrated circuit, and amplifier 520 needs a large amount of space and element, and this will increase cost.
With reference to Fig. 5, MOS transistor 502 is similar to the MOS transistor 102 in Fig. 1-3 with electric capacity 104 with electric capacity 504.Similarly, the input source impedance in resistance 506 presentation graphs 5.In the form of integrated circuit, the MOS transistor 502 in T/H circuit 500 does not need to be grounded to prevent transistor junction forward bias, and this point is different from the p-type substrate 306 in Fig. 3.On the contrary, in Fig. 5, the substrate of T/H circuit 500 (p trap) is coupled to output 524 and the negative input end 526 of amplifier 520.The positive input terminal 522 of amplifier 520 is coupled to input node 508.Similar with Fig. 1, in Fig. 5, the parasitic junction capacitance of MOS transistor 502 represents by PJC diode 512 and 514, and in Fig. 5, they are surrounded by dotted line frame, to illustrate that they are not actual circuit elements.
In the operation of T/H circuit 500, (triggering signal V during MOS transistor 502 conducting
tRIGGERexcess input signal V
iNtime), MOS transistor 502 and a resistance are similar, and amplifier 520 is for eliminating the voltage at PJC diode 512 and 514 two ends.Therefore, the variable parasitic capacitance of the source electrode-substrate of MOS transistor 502 and drain electrode-substrate junction voltage is linearized.
According to principle of the present invention, Fig. 6 provides the T/H circuit of a kind of low cost, parasitic junction capacitance compensation, and it does not need specific manufacturing process.
With reference to Fig. 6, T/H circuit 600 adopts MOS transistor 602 and an electric capacity 604.The variable voltage parasitic junction capacitance of MOS transistor 602 is represented by the PJC diode 612 and 614 of the drain electrode in MOS transistor 602 and source electrode.Similar with Fig. 1, PJC the diode 612 and 614 use dotted line frames in Fig. 6 go out, rather than occur as independent element, and they have represented that the pn of MOS transistor 602 ties.Similarly, the input source impedance in resistance 606 presentation graphs 6.The first and second compensation junction capacitance (CJC) diodes 622 and 624 are coupling in respectively between input node 608 and bias voltage node 620, output node 610 and bias voltage node 620.The anode of CJC diode 622 is coupled to input node 608, and the negative electrode of CJC diode 622 is coupled to bias voltage node 620.Equally, the anode of CJC diode 624 and negative electrode are coupled to output node 610 and voltage bias node 620.
In operation, an input signal V
iNcause inputting the change in voltage at node 608 places.When the grid of MOS transistor 602 is coupled to while being greater than the voltage of inputting node 608 places, MOS transistor 602 is just as a resistance--and allow electric capacity 604 to carry out charging and discharging, make the output V of output node 610
oUTfollow input signal V
iNchange (being tracing mode).When the grid of MOS transistor 602 is coupled to while being less than the voltage of inputting node 608 places, MOS transistor 602 is ended--Isolation input signal V
iNwith electric capacity 604 and output node 610, the therefore output V at output node 610 places
oUTremain constant (being Holdover mode).Therefore, the signal V of the grid of MOS transistor 602
tRIGGERas a triggering signal, T/H circuit 600 is changed between tracing mode and Holdover mode.
As MOS transistor 602 conductings (because triggering signal V
tRIGGERexcess input signal V
iNvoltage) time, input node 608 places input signal V
iNchange the voltage at PJC diode 612 and 614 two ends, cause the change in voltage of the parasitic junction capacitance of PJC diode 612 and 614 representatives.But according to principle of the present invention, the voltage at CJC diode 622 and 624 two ends is contrary with the variation of PJC diode 612 and 614.By selecting the suitably CJC diode 622 and 624 of size, total parasitic junction capacitance can linearisation.
Fig. 7 is the curve chart of the electric capacity that obtains of the comprehensive transistor parasitic capacitance of principle according to the present invention and building-out capacitor with change in voltage.
With reference to Fig. 7, curve 702 represents the curve that the parasitic junction capacitance of PJC diode 612 or 614 representatives changes with the variation of input node 608 place's voltages.Curve 704 represents the curve that the parasitic junction capacitance of CJC diode 622 or 624 representatives changes with the variation of input node 608 place's voltages.As can be seen from Figure 7, two voltage variable capacitance curves 702 and 704 combine and can obtain total capacitance curve 706, and it is relatively constant with respect to the variation of input node 608 place's voltages.
This linearizing method of institute's parasitic junction capacitance (being represented by PJC diode 612 and 614 in Fig. 6) that makes has been improved the harmonic distortion at output node 610 places when MOS transistor 602 is closed greatly.And this method is not limited to transistorized manufacturing process.
Fig. 8 is the cutaway view of the integrated circuit structure of the n-channel mosfet of parasitic junction capacitance compensation, according to principle of the present invention.
Fig. 8 is the cutaway view of the n channel mosfet 88 of a compensate for parasitic capacitance obtaining of principle according to the present invention, and it can be as the MOS transistor 602 in Fig. 6.Similar with Fig. 3, n+ district 802 and 804 is diffused or is injected into p-type silicon substrate 806.Oxide skin(coating) 808 is on p-type substrate 806.A thin part of oxide skin(coating) 808 is isolated the polysilicon gate of MOSFET800 820 and p-type silicon substrate 806. Metal terminal 830 and 840 is coupled to respectively n+ district 802 and 804.
For principle according to the present invention forms CJC diode 850, n-trap 851 is diffused or is injected into p-type silicon substrate 806.852He p+ district, N+ district 854 spreads or is injected into n-trap 850. Metal terminal 856 and 858 is coupled to respectively 852He p+ district, n+ district 854, thereby is connected to bias voltage.Correspondingly, another CJC diode can be by being used p channel transistor 860 to realize.If accomplish this point, p channel transistor 860 must cut-off.
Fig. 9 is the schematic diagram that principle according to the present invention makes the linearizing T/H circuit 900 of parasitic capacitance.
With reference to Fig. 9, MOS transistor 901 and 902 is by drain electrode and source-coupled.Electric capacity 904 is coupled to the drain electrode of MOS transistor 901 and 902.Resistance 906 represents the input signal source electrode impedance of T/H circuit 900.PJC diode 911 and 913,912 and 914 represents respectively the parasitic junction capacitance of MOS transistor 901 and 902.PJC diode 911,912,913 and 914 is drawn together in dotted line frame, rather than as independent element, they have represented that the pn of MOS transistor 901 and 902 ties.
As can be seen from Figure 9, T/H circuit 900 comprises two complementary PJC diode pairs (911 and 912,913 and 914), according to principle of the present invention, has complementary effect between them.According to the MOS transistor 901 and 902 of selecting, junction capacitance (CJC) diode 922 of one or more compensation also can join in T/H circuit 900, further to make parasitic junction capacitance linearisation.CJC diode 922 can add as required, for example: (1) is added between the source electrode and bias voltage node 920 of MOS transistor 902, (2) be added between the drain electrode and bias voltage node 920 of MOS transistor 902, (3) CJC diode pair 922 is added on respectively between the source electrode and bias voltage node 920 of MOS transistor 902, between drain electrode and bias voltage node 920.The anode of first CJC diode 922 can be coupled to the source electrode of MOS transistor 902, and the negative electrode of first CJC diode 922 can be coupled to bias voltage node 920.Similarly, the anode of second CJC diode 922 can be coupled to the drain electrode of MOS transistor 902, and the negative electrode of second CJC diode 922 can be coupled to bias voltage node 920.Or, one or two in CJC diode pair 922 be all coupling in and the drain electrode or source electrode of MOS transistor 901 between (in Fig. 9, not drawing).Therefore, the circuit of this linearisation parasitic junction capacitance has improved the harmonic distortion at output node 910 places.And the method for this linearisation parasitic junction capacitance is not limited to manufacturing process.
In operation, an input signal V
iNcause inputting the change in voltage at node 908 places.When being coupled to one, the grid of MOS transistor 902 is greater than the voltage of inputting node 908 places, and the grid of MOS transistor 901 is coupled to one while being less than the voltage of inputting node 908 places, the switch being comprised of MOS transistor 901 and 902 and a resistance are similar--and allow electric capacity 904 to carry out charging and discharging, thereby make the output V of output node 910
oUTalong with input signal V
iNchange (being tracing mode).When the grid of MOS transistor 902 is coupled to one, be less than the voltage of inputting node 908 places, or the grid of MOS transistor 901 is coupled to one while being greater than the voltage of inputting node 908 places, the switch being comprised of MOS transistor 901 and 902 is by input signal V
iNisolated with electric capacity 904 and output node 910, the therefore output V of output node 910
oUT(being Holdover mode) remains unchanged.Therefore, the signal V of the grid of MOS transistor 901 and 902
tRIGGER1and V
tRIGGER2as triggering signal, T/H circuit 900 is switched between tracing mode and Holdover mode.
When the switch being comprised of MOS transistor 901 and 902 is closed, the input signal V at input node 908 places
iNmake the change in voltage at PJC diode 912 and 914 two ends, thereby cause the parasitic junction capacitance being represented by PJC diode 912 and 914 to change.In addition, the voltage at PJC diode 911 and 913 two ends is contrary with the variation of PJC diode 912 and 914.Meanwhile, append to the change in voltage at CJC diode 922 two ends of T/H circuit 900.Parasitic junction capacitance by 911 and 913 representatives of PJC diode makes the parasitic junction capacitance linearisation by 912 and 914 representatives of PJC diode.In addition, select as required the suitably CJC diode 922 of size, can make the further linearisation of parasitic junction capacitance.
Obviously, although the present invention comes into question by Fig. 6-9, wherein the transistor in T/H circuit adopts mosfet transistor, and the present invention is also applicable to the input equipment of other Circnit Layouts and type.For example, can adopt JFET rather than MOSFET.In addition, can also use MOSFET or the JFET of any p raceway groove or n raceway groove.
In addition, other provides and follows the tracks of and keep the circuit of function can benefit from equally the method for the parasitic junction capacitance compensation that principle according to the present invention obtains.
Although the present invention embodies by concrete example, above-mentioned example just should not limit the present invention for the present invention is described.It should be pointed out that as long as no departing from essence of the present invention and meeting the definition in claim, on above-mentioned example, make suitable modification and still belong to category of the present invention.
Claims (5)
1. the circuit with the harmonic reduction distortion of trying one's best for compensating non-linear electric capacity, is characterized in that: in biased electrical pressure side, provide a bias voltage; Adopt a transistor, it has source electrode, drain and gate; A capacitive coupling is between drain electrode and ground; First diode-coupled is between transistorized drain electrode and biased electrical pressure side, for compensating the parasitic junction capacitance of drain terminal; Second diode-coupled is between transistorized source electrode and biased electrical pressure side, for the parasitic junction capacitance of compensating source electrode terminal.
According to claim 1 a kind of for compensating non-linear electric capacity with the circuit of harmonic reduction distortion as far as possible, it is characterized in that: at above-mentioned transistorized source electrode, receive the input voltage changing; At transistorized grid, receive triggering signal; In transistorized drain electrode, provide output.
According to claim 1 a kind of for compensating non-linear electric capacity with the circuit of harmonic reduction distortion as far as possible, it is characterized in that: the signal of (1) variation is substantially equal to input signal; (2), when receiving triggering signal, a constant signal is substantially equal to input signal.
According to claim 1 a kind of for compensating non-linear electric capacity with the circuit of harmonic reduction distortion as far as possible, it is characterized in that: above-mentioned biased electrical pressure side, transistor, electric capacity, a monolithic integrated circuit of first and second diodes compositions.
According to claim 1 a kind of for compensating non-linear electric capacity with the circuit of harmonic reduction distortion as far as possible, it is characterized in that: above-mentioned transistor can be n raceway groove or p channel transistor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113765481A (en) * | 2021-07-23 | 2021-12-07 | 华东师范大学 | Digital frequency multiplication method and injection locking frequency doubler circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113765481A (en) * | 2021-07-23 | 2021-12-07 | 华东师范大学 | Digital frequency multiplication method and injection locking frequency doubler circuit |
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Address after: 215000 Building 1, No. 150, Jici Road, science and Technology City, high tech Zone, Suzhou City, Jiangsu Province Patentee after: Suzhou Baker Microelectronics Co.,Ltd. Address before: Room 1404, building 3, No. 209, Zhuyuan Road, high tech Zone, Suzhou, Jiangsu 215011 Patentee before: SUZHOU BAKER MICROELECTRONICS Co.,Ltd. |
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