CN104052459A - Sampling circuit and sampling method - Google Patents
Sampling circuit and sampling method Download PDFInfo
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- CN104052459A CN104052459A CN201410248246.0A CN201410248246A CN104052459A CN 104052459 A CN104052459 A CN 104052459A CN 201410248246 A CN201410248246 A CN 201410248246A CN 104052459 A CN104052459 A CN 104052459A
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Abstract
The embodiment of the invention discloses a sampling circuit which comprises a sampling switch, a holding capacitor, a reference voltage switch and a control device. The sampling switch is connected with a signal source and is connected with a first electrode of the holding capacitor, and the sampling switch is used for being closed in a sampling phase so that the first electrode of the holding capacitor can change along with the signal source. The output end of the reference voltage switch is connected with a first reference voltage source, and the input end of the reference voltage switch is connected with the first electrode of the holding capacitor and used for being closed in a holding phase so that the voltage of the first electrode of the holding capacitor can be pulled to a first reference voltage. The holding capacitor is used for outputting sampling voltage from a second electrode of the holding capacitor in the holding phase. One end of the control device is connected with the polarization end of the reference voltage switch, connected with the input end of the reference voltage switch and used for enabling the polarization end of the reference voltage switch to be suspended according to control signals in the sampling phase. The sampling circuit has good linearity.
Description
Technical field
The present invention relates to electronic applications, particularly a kind of sample circuit and the method for sampling.
Background technology
In radio communication, no matter be receive path or feedback path, analog to digital converter (Analog-to-Digital Converter is called for short ADC) is all absolutely necessary.Along with the development of wireless communication technique, the inversion frequency to ADC and the requirement of the linearity are also more and more higher.
Sample circuit is the front end circuit of ADC, and its effect is to gather instantaneous value at a time of analog input voltage, and carries out the transition period at ADC and keep output voltage constant, carries out analog-to-digital conversion for ADC.Sample circuit is vital to ADC, and therefore the linearity of sample circuit can directly affect the linearity of ADC.
Sample circuit of the prior art generally includes sampling switch, keeps electric capacity, sole switching plate and reference voltage switch etc.Above-mentioned various switch adopts MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide half field effect transistor are called for short metal-oxide-semiconductor) conventionally.Metal-oxide-semiconductor comprises two types of NMOS and PMOS.NMOS pipe is to adopt a P type silicon semiconductor material to make substrate, on its face, spread Liao LianggeNXing district, cover again layer of silicon dioxide (SiO2) insulating barrier in the above, last above N district, make two holes by the method for corroding, on insulating barrier and in two holes, make respectively three electrode: G (grid), S (source electrode) and D (drain electrode) by metallized method.In like manner, PMOS pipe is on N-type silicon semiconductor material, to have spread two p type island regions.No matter be NMOS pipe or PMOS pipe, between its drain electrode and substrate, have a PN junction, between source electrode and substrate, also have a PN junction.
PN junction between drain electrode and the substrate of metal-oxide-semiconductor is equivalent to a diode.In the time of high-frequency work, diode there will be capacitance characteristic, and this electric capacity is called parasitic capacitance.Because diode is nonlinear device, its parasitic capacitance is also nonlinear, and in the time of sample circuit high-frequency work, this nonlinear parasitic capacitance can make the linearity of sample circuit worsen, and then affects the linearity of ADC.
Summary of the invention
A kind of sample circuit is provided in the embodiment of the present invention, has there is the good linearity.
In order to solve the problems of the technologies described above, the embodiment of the invention discloses following technical scheme:
On the one hand, a kind of sample circuit is provided, comprise: sampling switch, maintenance electric capacity and reference voltage switch, described sampling switch is connected with signal source, and be connected with the first electrode of described maintenance electric capacity, be used in sample phase closure, so that described maintenance electric capacity the first electrode is followed the variation of described signal source;
The output of described reference voltage switch is connected with the first reference voltage source, and input is connected with described maintenance electric capacity the first electrode, in maintenance stage closure, so that the voltage of described maintenance electric capacity the first electrode is pulled to the first reference voltage;
Described maintenance electric capacity, in the described maintenance stage, is exported sampled voltage from described maintenance electric capacity the second electrode;
Described sample circuit also comprises control device, one end of described control device is connected with the offset side of described reference voltage switch, and be connected with the input of described reference voltage switch, for making the offset side of described reference voltage switch unsettled in described sample phase according to control signal.
In conjunction with first aspect, in the first possibility implementation of first aspect, described reference voltage switch comprises the first metal-oxide-semiconductor, the source electrode of described the first metal-oxide-semiconductor is the output of described reference voltage switch, the drain electrode of described the first metal-oxide-semiconductor is the input of described reference voltage switch, and the substrate of described the first metal-oxide-semiconductor is the offset side of described reference voltage switch.
In conjunction with the first possibility implementation of first aspect, in the second possibility implementation of first aspect, described control device comprises the 2nd NMOS pipe, the grid of described the 2nd NMOS pipe is connected with control signal input, the drain electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd NMOS pipe, the source ground of described the 2nd NMOS pipe;
Wherein, described control signal is low level in described sample phase, is high level in the described maintenance stage.
In conjunction with the first possibility implementation of first aspect, in the third possibility implementation of first aspect, described control device comprises the 2nd PMOS pipe, the grid of described the 2nd PMOS pipe is connected with control signal input, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd PMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the second reference voltage source;
Wherein, described control signal is high level in described sample phase, is low level in the described maintenance stage.
In conjunction with the first possibility implementation of first aspect, in the 4th kind of possibility implementation of first aspect, described control device comprises NPN triode, the base stage of described NPN triode is connected with control signal input, the collector electrode of described NPN triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described NPN triode;
Wherein, described control signal is low level in described sample phase, is high level in the described maintenance stage.
In conjunction with the first possibility implementation of first aspect, in the 5th kind of possibility implementation of first aspect, described control device comprises PNP triode, the base stage of described PNP triode is connected with control signal input, the collector electrode of described PNP triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described PNP triode;
Wherein, described control signal is high level in described sample phase, is low level in the described maintenance stage.
Second aspect, a kind of method of sampling is provided, for sample circuit, described sample circuit comprises sampling switch, keeps electric capacity and reference voltage switch, described sampling switch is connected with signal source, and be connected with the first electrode of described maintenance electric capacity, the output of described reference voltage switch is connected with the first reference voltage source, and input is connected with described maintenance electric capacity the first electrode;
The described method of sampling comprises:
In sample phase, control described sampling switch closure, control described reference voltage switch and disconnect, so that following described signal source, described maintenance electric capacity the first electrode voltage changes; The offset side of controlling described reference voltage switch is unsettled;
In the maintenance stage, control described sampling switch and disconnect, control described reference voltage switch closure, so that the voltage of described maintenance electric capacity the first electrode is pulled to the first reference voltage; From described maintenance electric capacity the second electrode output sampled voltage.
In conjunction with second aspect, in the first possibility implementation of second aspect, described reference voltage switch comprises the first metal-oxide-semiconductor, the source electrode of described the first metal-oxide-semiconductor is the output of described reference voltage switch, the drain electrode of described the first metal-oxide-semiconductor is the input of described reference voltage switch, and the substrate of described the first metal-oxide-semiconductor is the offset side of described reference voltage switch.
In conjunction with the first possibility implementation of second aspect, in the second possibility implementation of second aspect, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control the 2nd NMOS pipe and make the substrate of described reference voltage switch unsettled;
Wherein, the grid of described the 2nd NMOS pipe is connected with control signal input, and the drain electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd NMOS pipe, the source ground of described the 2nd NMOS pipe;
Described control signal is low level in described sample phase, is high level in the described maintenance stage.
In conjunction with the first possibility implementation of second aspect, in the third possibility implementation of second aspect, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control the 2nd PMOS pipe and make the substrate of described reference voltage switch unsettled;
Wherein, the grid of described the 2nd PMOS pipe is connected with control signal input, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd PMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the second reference voltage source;
Described control signal is high level in described sample phase, is low level in the described maintenance stage.
In conjunction with the first possibility implementation of second aspect, in the 4th kind of possibility implementation of second aspect, the offset side of stating control reference voltage switch is unsettled, comprising:
According to control signal, control NPN triode and make the substrate of described reference voltage switch unsettled;
Wherein, the base stage of described NPN triode is connected with control signal input, and the collector electrode of described NPN triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described NPN triode;
Described control signal is low level in described sample phase, is high level in the described maintenance stage.
In conjunction with the first possibility implementation of second aspect, in the 5th kind of possibility implementation of second aspect, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control described PNP triode and make the substrate of described reference voltage switch unsettled;
Wherein, the base stage of described PNP triode is connected with control signal input, and the collector electrode of described PNP triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described PNP triode;
Described control signal is high level in described sample phase, is low level in the described maintenance stage.
A kind of sample circuit is disclosed in embodiments of the invention, comprise sampling switch, keep electric capacity, reference voltage switch and control device, one end of control device is connected with the offset side of reference voltage switch, and be connected with the output of reference voltage switch, for making the offset side of reference voltage switch unsettled in sample phase according to control signal.Sample circuit of the present invention, makes the offset side of reference voltage switch unsettled in sample phase, has reduced the nonlinear impact of equivalent diode of reference voltage switch, has the good linearity.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Figure 1 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention;
Figure 2 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention;
Figure 3 shows that the metal-oxide-semiconductor internal structure schematic diagram of the embodiment of the present invention;
Figure 4 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention;
Figure 5 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention;
Figure 6 shows that the schematic flow sheet of the method for sampling of the embodiment of the present invention.
Embodiment
The present invention following embodiment provide a kind of sample circuit, has the good linearity.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out to clear, complete description, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Figure 1 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention.As shown in Figure 1, sample circuit comprises sampling switch 101, keeps electric capacity 102, reference voltage switch 103 and control device 104.
Described sampling switch 101 is connected with signal source, and is connected with keeping the first electrode of electric capacity 102, in sample phase closure, so that described maintenance electric capacity the first electrode is followed the variation of described signal source.
The output out of described reference voltage switch 103 is connected with the first reference voltage source 201, and input in is connected with described maintenance electric capacity 102 first electrodes, in maintenance stage closure, so that the voltage of described maintenance electric capacity the first electrode is pulled to the first reference voltage.
Described maintenance electric capacity 102, in the described maintenance stage, is exported sampled voltage from the second electrode of described maintenance electric capacity 102.
One end of described control device 104 is connected with the offset side B of described reference voltage switch 103, and be connected with the input in of described reference voltage switch 103, for making the offset side B of described reference voltage switch 103 unsettled in described sample phase according to control signal.
In the present embodiment, keep two electrodes of electric capacity 102 to there is no polarity differentiation, just distinguish for convenience of description note and do the first electrode and the second electrode.In embodiments of the invention, the electrode that keeps electric capacity 102 to be connected with reference voltage switch 103 is called the first electrode, and another electrode is called the second electrode.
The sample circuit of the present embodiment, in sample phase, makes the offset side of reference voltage switch unsettled, has reduced the nonlinear impact of the equivalent diode of reference voltage switch, has the good linearity, and then has improved the linearity of ADC.
Figure 2 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention.As shown in Figure 2, sample circuit comprises sampling switch 101, keeps electric capacity 102 and reference voltage switch 103, also comprises control device 104.In sample circuit, connected mode and the function of sampling switch 101, maintenance electric capacity 102 and reference voltage switch 103 are same as the previously described embodiments, repeat no more herein.
Described reference voltage switch 103 comprises the first metal-oxide-semiconductor 100, the source electrode (the s utmost point) of described the first metal-oxide-semiconductor 100 is the output out of described reference voltage switch, the drain electrode (the d utmost point) of described the first metal-oxide-semiconductor 100 is the input in of described reference voltage switch, and the substrate of described the first metal-oxide-semiconductor 100 is the offset side B of described reference voltage switch.
Described control device 104 comprises the 2nd NMOS pipe 200, the grid (the g utmost point) of described the 2nd NMOS pipe 200 is connected with control signal input 203, the drain electrode (the d utmost point) of described the 2nd NMOS pipe is connected with the drain electrode (the d utmost point) of described the first metal-oxide-semiconductor, also be connected with the substrate of described the first metal-oxide-semiconductor 100, the substrate ground connection of described the 2nd NMOS pipe 200; Source electrode (the s utmost point) ground connection of the second metal-oxide-semiconductor 200.
Described the second metal-oxide-semiconductor 200 is from control signal input 203 reception control signals, and described control signal is low level in described sample phase, is high level in the described maintenance stage.
In the present embodiment, low and high level is relative concept, does not represent concrete magnitude of voltage.High and low level only need to meet the requirement of metal-oxide-semiconductor to cut-in voltage.In the present embodiment, the grid of sampling switch 101 and the grid of the first metal-oxide-semiconductor 100 are all connected with other clock circuit (not shown) conventionally, and closed and disconnection under the control of clock circuit.
In another embodiment, described control device comprises the 2nd PMOS pipe, the grid of described the 2nd PMOS pipe is connected in mutually with control signal input, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd PMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the second reference voltage source; Wherein, described control signal is high level in described sample phase, is low level in the described maintenance stage.The connected mode of the 2nd PMOS pipe is not shown in Fig. 2.
The second reference voltage source offers the required voltage of the normal work of PMOS, is generally the power supply of sample circuit.
Diode 105 in Fig. 2 is the equivalent diode of reference voltage switch 103.In sample phase, reference voltage switch 103 disconnects, but equivalent diode 105 still exists.In the sample circuit shown in Fig. 2, the equivalent diode 105 of reference voltage switch 103 is in parallel with maintenance electric capacity 102.
In the time of sample circuit high-frequency work, the parasitic capacitance of equivalent diode 105 can not be ignored the impact of sample circuit.In the time of high frequency, the parasitic capacitance that is equivalent to equivalent diode 105 is in parallel with maintenance electric capacity 102.In sample phase, sampling switch 101 closures, keep electric capacity 102 to be connected with signal source, and the parasitic capacitance of equivalent diode 105 is also connected with signal source, and signal source is simultaneously to keeping the parasitic capacitance charging of electric capacity 102 and equivalent diode 105.The parasitic capacitance of equivalent diode 105 is nonlinear, and the output of nonlinear parasitic capacitance and input are not directly proportional, and therefore cause keeping the input and output of electric capacity 102 not to be directly proportional, and have affected the linearity of sample circuit.
Figure 3 shows that the internal structure schematic diagram of NMOS pipe.As shown in Figure 3, NMOS pipe comprises P type substrate PSUB, the DNW that N-type is got deeply stuck in, P trap (Pwell), and Liang GeNXing district.Draw 6 ports from above each region, be respectively PSUB, DNW, B, S, G, D, wherein, B, S, G, D draws metal-oxide-semiconductor becomes external terminal, is respectively substrate B, source S, grid G and drain D; PSUB end and DNW port are not drawn metal-oxide-semiconductor outside.Between n type material and P-type material, be all equivalent to a diode, diode has parasitic capacitance, and the parasitic capacitance between drain D and substrate B is Cdb, and Pwell is Cpwdnw to the equivalent capacity between DNW.
Under normal circumstances, the external parasitic capacitance of metal-oxide-semiconductor is Cdb, in the time that substrate B is unsettled, is equivalent to parasitic capacitance Cdb in parallel with Cpwdnw, and the external parasitic capacitance of metal-oxide-semiconductor is diminished.In an embodiment of the present invention, when the substrate of the first metal-oxide-semiconductor 100 is unsettled, the parasitic capacitance of equivalent diode 105 diminishes, and has reduced the non-linear impact on sample circuit of the equivalent diode of reference voltage switch, makes sample circuit have the good linearity.
Internal structure and Fig. 3 of PMOS pipe are similar, do not repeat them here.
The sample circuit of the present embodiment, in sample phase, make the substrate of reference voltage switch unsettled by the shutoff of metal-oxide-semiconductor, reduce the nonlinear impact of the equivalent diode of reference voltage switch, make sample circuit there is the good linearity, and then improved the linearity of ADC.
Figure 4 shows that the schematic diagram of the sample circuit of one of the embodiment of the present invention.As shown in Figure 4, sample circuit comprises sampling switch 101, keeps electric capacity 102 and reference voltage switch 103, also comprises control device 104.In sample circuit, connected mode and the function of sampling switch 101, maintenance electric capacity 102 and reference voltage switch 103 are same as the previously described embodiments, repeat no more herein.
Described sample circuit also comprises that control signal accesses from control signal input 203, and control signal is low level in described sample phase, is high level in the described maintenance stage.
In another embodiment, described control device comprises PNP triode, the base stage of described PNP triode is connected with control signal input, the collector electrode of described PNP triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described PNP triode.Control signal enters through control signal termination, is high level in described sample phase, is low level in the described maintenance stage.The connected mode of PNP triode is not shown in Fig. 4.
In the present embodiment, low and high level is relative concept, does not represent concrete magnitude of voltage.High and low level only need to meet the requirement of triode to cut-in voltage.
Diode 105 in Fig. 4 is the equivalent diode of reference voltage switch 103.
The sample circuit of the present embodiment, in sample phase, make the substrate of reference voltage switch unsettled by the shutoff of triode, reduce the nonlinear impact of the equivalent diode of reference voltage switch, make sample circuit there is the good linearity, and then improved the linearity of ADC.
Figure 5 shows that the schematic diagram of a kind of sample circuit of the embodiment of the present invention.As shown in Figure 5, sample circuit comprises sampling switch 101, keeps electric capacity 102, reference voltage switch 103, and control device 104.In sample circuit, connected mode and the function of sampling switch 101, maintenance electric capacity 102, reference voltage switch 103 and control device 104 are same as the previously described embodiments, repeat no more herein.
Described sample circuit also comprises sole switching plate 106, and its drain electrode (the d utmost point) is connected with keeping electric capacity 102 second electrodes, source electrode (the s utmost point) ground connection.Sole switching plate 106, in sample phase closure, is pulled down to zero by the voltage of the second electrode that keeps electric capacity 102; Sole switching plate 106 disconnected in the maintenance stage.
Below taking the sample circuit shown in Fig. 5 as example, the operation principle of the sample circuit of brief description the present embodiment.As shown in Figure 5, sample circuit is from the second electrode output sampled voltage of described maintenance electric capacity 102.
In the present embodiment, described sample circuit comprises sample phase and maintenance stage in the time of sampling.
In sample phase, sampling switch 101 closures, reference voltage switch 103 disconnects, and keeps the voltage follow signal source of electric capacity 102 first electrodes to change; The 2nd NMOS pipe 200 disconnects, and the substrate of reference voltage switch 103 is unsettled; Sole switching plate 106 closures, are pulled down to zero by the voltage that keeps electric capacity 102 second electrodes.
In the maintenance stage, sampling switch 101 disconnects, and the voltage that keeps electric capacity 102 first electrodes is pulled to the first reference voltage by reference voltage switch 103 closures; The 2nd NMOS manages 200 closures, makes the substrate ground connection of described reference voltage switch 103; Sole switching plate 106 disconnects; From the second electrode output sampled voltage of described maintenance electric capacity 102.
In the maintenance stage, if keep the drop-down N volt of voltage of electric capacity 102 first electrodes to reference voltage, keep the voltage of the electric capacity 102 second electrodes N volt that also simultaneously declines, so that keep the voltage difference between the first electrode and second electrode of electric capacity 102 to keep constant.In like manner, on the voltage of electric capacity 102 first electrodes, draw N volt to reference voltage if keep, keep the voltage of the electric capacity 102 second electrodes N volt that also simultaneously rises, so that keep the voltage difference between the first electrode and second electrode of electric capacity 102 to keep constant.In the maintenance stage, keep electric capacity 102 first electrode voltages to equal reference voltage, from keeping the second electrode output sampled voltage of electric capacity 102.This sampled voltage offers ADC and carries out digital-to-analogue conversion.
The method of the present embodiment, from keeping the second electrode output sampled voltage of electric capacity 102, the interference of the each input voltage that has reduced sample circuit to sampled voltage, has further improved the linearity of sample circuit.
Corresponding with above-mentioned sample circuit, embodiments of the invention also provide a kind of method of sampling.Figure 6 shows that the flow chart of a method of sampling of the embodiment of the present invention, Fig. 6 need describe in conjunction with Fig. 1, Fig. 2, Fig. 4 and Fig. 5.
The method of sampling of the present embodiment is for sample circuit, and sample circuit comprises sampling switch 101, keeps electric capacity 102, reference voltage switch 103.Described sampling switch 101 is connected with signal source, is also connected with the first electrode that keeps electric capacity 102, and the output out of described reference voltage switch 103 is connected with the first reference voltage source 201, and input in is connected with described maintenance electric capacity 102 first electrodes.
In sample phase, described sampling switch 101 closures, described reference voltage switch 103 disconnects, following described signal source with described maintenance electric capacity 102 first electrode voltages changes, in the maintenance stage, described sampling switch 101 disconnects, and described reference voltage switch 103 closures, to be pulled to the first reference voltage by the voltage of described maintenance electric capacity 102 first electrodes.
The described method of sampling comprises:
Step 601, in sample phase, controls described sampling switch closure, controls described reference voltage switch and disconnects, and changes so that described maintenance electric capacity the first electrode voltage is followed described signal source; The offset side of controlling described reference voltage switch is unsettled.
Step 602, in the maintenance stage, controls described sampling switch and disconnects, and controls described reference voltage switch closure, so that the voltage of described maintenance electric capacity the first electrode is pulled to the first reference voltage; From described maintenance electric capacity the second electrode output sampled voltage.
The method of sampling of the present embodiment, in sample phase, make the offset side of reference voltage switch unsettled, reduce the non-linear impact on sample circuit of the equivalent diode of reference voltage switch, improve the linearity of sample circuit, and then also improved the linearity of ADC.
Described reference voltage switch 103 comprises the first metal-oxide-semiconductor 100, the source electrode (the s utmost point) of described the first metal-oxide-semiconductor 100 is the output out of described reference voltage switch, the drain electrode (the d utmost point) of described the first metal-oxide-semiconductor 100 is the input in of described reference voltage switch, and the substrate of described the first metal-oxide-semiconductor 100 is the offset side B of described reference voltage switch.
The offset side of the described reference voltage switch of described control is unsettled, comprising: according to control signal, control the 2nd NMOS pipe 200 and make the substrate of described reference voltage switch unsettled.
Shown in Fig. 2, the grid (the g utmost point) of described the 2nd NMOS pipe 200 is connected with control signal input 203, the drain electrode (the d utmost point) of described the 2nd NMOS pipe is connected with the drain electrode (the d utmost point) of described the first metal-oxide-semiconductor, also be connected with the substrate of described the first metal-oxide-semiconductor 100, the substrate ground connection of described the 2nd NMOS pipe 200; If described the second metal-oxide-semiconductor 200 is NMOS pipe, the source electrode of described the second metal-oxide-semiconductor 200 (the s utmost point) ground connection, the source ground of described the 2nd NMOS pipe.
Described the 2nd NMOS pipe 200 is from control signal input 203 reception control signals, and described control signal is low level in described sample phase, is high level in the described maintenance stage.
In another method of sampling of embodiments of the invention, the offset side of the described reference voltage switch of described control is unsettled, comprising: according to control signal, control the 2nd PMOS pipe and make the substrate of described reference voltage switch unsettled.
The grid of described the 2nd PMOS pipe is connected with control signal input, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd PMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the second reference voltage source; Described control signal is high level in described sample phase, is low level in the described maintenance stage.
The method of sampling of the embodiment of the present invention, in sample phase, make the substrate of reference voltage switch unsettled by controlling metal-oxide-semiconductor, reduce the non-linear impact on sample circuit of the equivalent diode of reference voltage switch, improve the linearity of sample circuit, and then improved the linearity of ADC.
Shown in Fig. 4, in a kind of method of sampling of the embodiment of the present invention, the offset side of the described reference voltage switch of described control is unsettled, comprising: according to control signal, control NPN triode 300 and make the substrate of described reference voltage switch unsettled.
Shown in Fig. 4, the base stage (the b utmost point) of described NPN triode 300 is connected with control signal input 203, the collector electrode (the c utmost point) of described NPN triode 300 is connected with the drain electrode (the d utmost point) of described the first metal-oxide-semiconductor 100, also be connected with the substrate of described the first metal-oxide-semiconductor 100, emitter (the e utmost point) ground connection of described NPN triode 300.
NPN triode 300 is from control signal input 203 reception control signals, and described control signal is low level in described sample phase, is high level in the described maintenance stage.
In a kind of method of sampling of the embodiment of the present invention, the offset side of the described reference voltage switch of described control is unsettled, comprising: according to control signal, control PNP triode and make the substrate of described reference voltage switch unsettled.
The base stage of described PNP triode is connected with control signal input, and the collector electrode of described PNP triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described PNP triode.
In the sample circuit of employing PNP triode, described control signal is high level in described sample phase, is low level in the described maintenance stage.
The method of sampling of the embodiment of the present invention, in sample phase, make the substrate of reference voltage switch unsettled by controlling triode, reduce the non-linear impact on sample circuit of the equivalent diode of reference voltage switch, improve the linearity of sample circuit, and then improved the linearity of ADC.
In embodiments of the invention, disclose a kind of sample circuit, made the offset side of reference voltage switch unsettled in sample phase according to control signal.Embodiments of the invention also provide a kind of method of sampling, and in sample phase, the offset side of controlling described reference voltage switch is unsettled.Sample circuit of the present invention and the method for sampling, reduced the nonlinear impact of the equivalent diode of reference voltage switch, makes sample circuit have the good linearity, and then the linearity of ADC is provided.
Those skilled in the art can be well understood to the mode that technology in the embodiment of the present invention can add essential common hardware by software and realize, common hardware comprises universal integrated circuit, universal cpu, general-purpose storage, universal elements etc., can certainly comprise that application-specific integrated circuit (ASIC), dedicated cpu, private memory, special components and parts etc. realize by specialized hardware, but in a lot of situation, the former is better execution mode.Based on such understanding, the part that technical scheme in the embodiment of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product can be stored in storage medium, as read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc, CD etc., comprise that some instructions (can be personal computers in order to make a computer equipment, server, or the network equipment etc.) carry out the method described in some part of each embodiment of the present invention or embodiment.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually referring to, what each embodiment stressed is and the difference of other embodiment.Especially,, for system embodiment, because it is substantially similar in appearance to embodiment of the method, so description is fairly simple, relevant part is referring to the part explanation of embodiment of the method.
Above-described embodiment of the present invention, does not form limiting the scope of the present invention.Any amendment of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (12)
1. a sample circuit, it is characterized in that, comprise: sampling switch, maintenance electric capacity and reference voltage switch, described sampling switch is connected with signal source, and be connected with the first electrode of described maintenance electric capacity, be used in sample phase closure, so that described maintenance electric capacity the first electrode is followed the variation of described signal source;
The output of described reference voltage switch is connected with the first reference voltage source, and input is connected with described maintenance electric capacity the first electrode, in maintenance stage closure, so that the voltage of described maintenance electric capacity the first electrode is pulled to the first reference voltage;
Described maintenance electric capacity, in the described maintenance stage, is exported sampled voltage from described maintenance electric capacity the second electrode;
Described sample circuit also comprises control device, one end of described control device is connected with the offset side of described reference voltage switch, and be connected with the input of described reference voltage switch, for making the offset side of described reference voltage switch unsettled in described sample phase according to control signal.
2. sample circuit as claimed in claim 1, it is characterized in that, described reference voltage switch comprises the first metal-oxide-semiconductor, the source electrode of described the first metal-oxide-semiconductor is the output of described reference voltage switch, the drain electrode of described the first metal-oxide-semiconductor is the input of described reference voltage switch, and the substrate of described the first metal-oxide-semiconductor is the offset side of described reference voltage switch.
3. sample circuit as claimed in claim 2, it is characterized in that, described control device comprises the 2nd NMOS pipe, the grid of described the 2nd NMOS pipe is connected with control signal input, the drain electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd NMOS pipe, the source ground of described the 2nd NMOS pipe;
Wherein, described control signal is low level in described sample phase, is high level in the described maintenance stage.
4. sample circuit as claimed in claim 2, it is characterized in that, described control device comprises the 2nd PMOS pipe, the grid of described the 2nd PMOS pipe is connected with control signal input, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd PMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the second reference voltage source;
Wherein, described control signal is high level in described sample phase, is low level in the described maintenance stage.
5. sample circuit as claimed in claim 2, it is characterized in that, described control device comprises NPN triode, the base stage of described NPN triode is connected with control signal input, the collector electrode of described NPN triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described NPN triode;
Wherein, described control signal is low level in described sample phase, is high level in the described maintenance stage.
6. sample circuit as claimed in claim 2, it is characterized in that, described control device comprises PNP triode, the base stage of described PNP triode is connected with control signal input, the collector electrode of described PNP triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described PNP triode;
Wherein, described control signal is high level in described sample phase, is low level in the described maintenance stage.
7. a method of sampling, it is characterized in that, for sample circuit, described sample circuit comprises sampling switch, keeps electric capacity and reference voltage switch, described sampling switch is connected with signal source, and be connected with the first electrode of described maintenance electric capacity, the output of described reference voltage switch is connected with the first reference voltage source, and input is connected with described maintenance electric capacity the first electrode;
The described method of sampling comprises:
In sample phase, control described sampling switch closure, control described reference voltage switch and disconnect, so that following described signal source, described maintenance electric capacity the first electrode voltage changes; The offset side of controlling described reference voltage switch is unsettled;
In the maintenance stage, control described sampling switch and disconnect, control described reference voltage switch closure, so that the voltage of described maintenance electric capacity the first electrode is pulled to the first reference voltage; From described maintenance electric capacity the second electrode output sampled voltage.
8. method as claimed in claim 7, it is characterized in that, described reference voltage switch comprises the first metal-oxide-semiconductor, the source electrode of described the first metal-oxide-semiconductor is the output of described reference voltage switch, the drain electrode of described the first metal-oxide-semiconductor is the input of described reference voltage switch, and the substrate of described the first metal-oxide-semiconductor is the offset side of described reference voltage switch.
9. method as claimed in claim 8, is characterized in that, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control the 2nd NMOS pipe and make the substrate of described reference voltage switch unsettled;
Wherein, the grid of described the 2nd NMOS pipe is connected with control signal input, and the drain electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd NMOS pipe, the source ground of described the 2nd NMOS pipe;
Described control signal is low level in described sample phase, is high level in the described maintenance stage.
10. method as claimed in claim 8, is characterized in that, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control the 2nd PMOS pipe and make the substrate of described reference voltage switch unsettled;
Wherein, the grid of described the 2nd PMOS pipe is connected with control signal input, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the first metal-oxide-semiconductor, and be connected with the substrate of described the first metal-oxide-semiconductor, the substrate ground connection of described the 2nd PMOS pipe, the source electrode of described the 2nd PMOS pipe is connected with the second reference voltage source;
Described control signal is high level in described sample phase, is low level in the described maintenance stage.
11. methods as claimed in claim 8, is characterized in that, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control NPN triode and make the substrate of described reference voltage switch unsettled;
Wherein, the base stage of described NPN triode is connected with control signal input, and the collector electrode of described NPN triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described NPN triode;
Described control signal is low level in described sample phase, is high level in the described maintenance stage.
12. methods as claimed in claim 8, is characterized in that, the offset side of described control reference voltage switch is unsettled, comprising:
According to control signal, control described PNP triode and make the substrate of described reference voltage switch unsettled;
Wherein, the base stage of described PNP triode is connected with control signal input, and the collector electrode of described PNP triode is connected with the drain electrode of described the first metal-oxide-semiconductor, and is connected with the substrate of described the first metal-oxide-semiconductor, the grounded emitter of described PNP triode;
Described control signal is high level in described sample phase, is low level in the described maintenance stage.
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| CN104052459B (en) | 2017-08-25 |
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