CN203455565U - Display panel - Google Patents
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- CN203455565U CN203455565U CN201320517395.3U CN201320517395U CN203455565U CN 203455565 U CN203455565 U CN 203455565U CN 201320517395 U CN201320517395 U CN 201320517395U CN 203455565 U CN203455565 U CN 203455565U
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- cabling
- data lines
- base plate
- integrated chip
- display panel
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Abstract
The utility model discloses a display panel. For a COF (chip on film) on one side of a display substrate, a first wire across a data line distribution sector is arranged on the display substrate, two second wires are arranged on the COF, one end of each of the two second wires is connected with the corresponding endpoint of the first wire, and the other end of each of the two second wires is connected with a corresponding first signal terminal; two third wires are also arranged on the COF, one end of each of the two third wires is connected with a source driver IC (integrated chip), and the other end of each of the two third wires is connected with a corresponding second signal terminal; the two second wires are positioned outside a first data line and a final data line respectively, and the two third wires are positioned on the inner sides of the two data lines; the two first signal terminals and the two second signal terminals are adjacent to two signal terminals connected with the first and final data lines. According to the display panel, the problem of poor display of pixels driven by the first and final data lines in a conventional display area can be solved.
Description
Technical field
The utility model relates to technical field of liquid crystal display, relates in particular to a kind of display panel.
Background technology
As shown in Figure 1, existing liquid crystal display generally comprises: film integrated chip (the Chip On Film of a side of display base plate (panel) 1, a plurality of panel1 of being arranged at (horizontal level of panel1) and opposite side (vertical position of panel1), COF) 2 with the assembled printed circuit boards being connected with described panel1 by described COF2 (PCB Assembly, PCBA) 3.
The partial enlarged drawing of COF and panel shown in Fig. 1 elliptic region and PCBA annexation as shown in Figure 2, the first data lines 5 (data line of the leftmost side in Fig. 2) and last data lines 6 (data line of the rightmost side in Fig. 2) of driving 1C4 to be connected with the source being arranged on the described COF2 of panel1 mono-side form a fan-shaped distributive province of data line (Fan-out area), the elliptic region shown in structural correspondence Fig. 3 of the fan-shaped distributive province of described data line.As shown in Figure 2, the region that described panel1 is connected with COF2 is band year footprint solder area (TCP bonding area) g, and the region that described PCBA3 is connected with COF2 is printed circuit board (PCB) welding region (PCB bonding area) l0.For PCB bonding arealO, as shown in Figure 4, spacing between the PIN8 PIN adjacent with both sides that the signal terminal (PIN) 7 being connected with PCBA3 due to described the first data lines 5 and last data lines 6 are connected with PCBA3 is very little, therefore, PIN7 and the data-signal that has high frequency in PIN8, exchange (with respect to public electrode voltages) characteristic are easily subject to the impact of adjacent PIN institute's signal transmission (or voltage), thereby affect the display effect of the pixel that the first data lines 5 described in viewing area and last data lines 6 drive, occur that line shows bad.
Utility model content
In view of this, fundamental purpose of the present utility model is to provide a kind of display panel, can solve described in existing viewing area the bad demonstration problem of the pixel that first and last data lines drive.
For achieving the above object, the technical solution of the utility model is achieved in that
A kind of display panel, comprise: display base plate, be arranged at the film integrated chip of display base plate one side and opposite side, and the assembled printed circuit boards being connected with described display base plate by described film integrated chip, each is arranged on the film integrated chip of display base plate one side active drive integrated circult is set, and the first data lines and last data lines are connected with described source drive integrated circult; For the film integrated chip that is arranged at display base plate one side, on described display base plate, be provided with the first cabling that crosses the fan-shaped distributive province of data line, on described film integrated chip, be provided with the second cabling that two one end are connected with two end points of described the first cabling respectively, the other end is connected with two first signal terminals that are arranged on printed circuit board (PCB) welding region respectively; On described film integrated chip, be also provided with the 3rd cabling that two one end are connected with described source drive integrated circult respectively, the other end is connected with two secondary signal terminals that are arranged on described printed circuit board (PCB) welding region respectively; Wherein, described two the second cablings lay respectively at the outside of described the first data lines and last data lines, and described two article of the 3rd cabling lays respectively at the inner side of the first data lines and last data lines; Described two first signal terminals and two secondary signal terminals are all adjacent with, two signal terminals being connected with described the first data lines and last data lines.
Further, described the first cabling is arranged at the gate metal layer of array base palte in described display base plate, with the same layer of described gate metal layer.Described the first cabling, the second cabling and the 3rd cabling are comprised of metal material.Described the first cabling is comprised of gate metal material.
Further, on the film integrated chip of described display base plate one side or be also provided with the test point being connected with described first signal terminal on assembled printed circuit boards.Film integrated chip for display base plate opposite side, on described display base plate, be also provided with the 4th cabling that crosses the fan-shaped distributive province of grid line, on film integrated chip, be also provided with the 5th cabling that two one end are connected with two end points of described the 4th cabling respectively, the other end is connected with two test points that are arranged on described film integrated chip respectively; Wherein, described two article of the 5th cabling lays respectively at the outside of first grid line and last root grid line.
Further, described the 4th cabling is arranged at source, the drain metal layer of array base palte in described display base plate, with described source, the same layer of drain metal layer.
Further, described the 4th cabling and the 5th cabling are comprised of metal material.Described the 4th cabling is comprised of source, drain metal material.
Further, the width of the width of described the first cabling and the data line of described source drive integrated circult in the fan-shaped distributive province of described data line is suitable; The width of the width of described the second cabling and the 3rd cabling and described film integrated chip upward wiring is suitable.
Further, the width of the width of described the 4th cabling and the grid-driving integrated circuit grid line in the fan-shaped distributive province of grid line is suitable; The width of the width of described the 5th cabling and film integrated chip upward wiring is suitable.
The display panel that the utility model provides, COF for display base plate one side, on display base plate, arrange and cross the first cabling of the fan-shaped distributive province of data line, and the second cabling that two one end are connected with two end points of described the first cabling respectively, the other end is connected with two first signal terminals that are arranged on printed circuit board (PCB) welding region is respectively set on COF; Two one end are set on described COF and are connected with source drive IC respectively, the 3rd cabling that the other end is connected with two secondary signal terminals that are arranged on printed circuit board (PCB) welding region respectively; Wherein, described two the second cablings lay respectively at the outside of the first data lines and last data lines, and described two article of the 3rd cabling lays respectively at the inner side of the first data lines and last data lines; Described two first signal terminals and two secondary signal terminals are all adjacent with, two signal terminals being connected with the first data lines and last data lines.In the utility model, owing to there is no signal in first, second and third cabling, so, isolation due to described first and second signal terminal, the described signal terminal connected with the first data lines and there is high frequency with the connected signal terminal of last data lines, the data-signal that exchanges (with respect to public electrode voltages) characteristic is difficult for being interfered again, guarantee the display effect of the pixel that described the first data lines and last data lines drive, avoided line to show bad.
In addition, the utility model also can be realized the measurement to signal in any data lines and grid line in the situation that not destroying viewing area; And can measure Panel and COF, and the electrical connection state between COF and PCBA.
Accompanying drawing explanation
Fig. 1 is the structural representation of available liquid crystal display;
Fig. 2 is the partial enlarged drawing of COF shown in Fig. 1 elliptic region and panel and PCBA annexation;
Fig. 3 is first and the fan-shaped distributive province of the data line structural representation of last data lines formation being connected with source drive IC;
Fig. 4 is the existing schematic diagram being disturbed because of the little data-signal causing of spacing between first and last data lines PIN adjacent with both sides;
Fig. 5 is display base plate one side arranges described in the utility model embodiment COF and the structural representation of panel and PCBA annexation;
Fig. 6 is the schematic diagram that the data-signal of first of the utility model embodiment and last data lines is no longer disturbed;
Fig. 7 is the schematic diagram that the utility model embodiment measures data-signal in data line;
Fig. 8 is that the utility model embodiment fills with the schematic diagram of data-signal at home and abroad to pixel;
Fig. 9 is the structural representation of the COF that display base plate opposite side arranges described in the utility model embodiment;
Figure 10 is the utility model examples measure Panel and COF, and the schematic diagram of the electrical connection state between COF and PCBA.
Description of reference numerals:
1 display base plate (panel); 2 film integrated chips (COF); The printed circuit board (PCB) (PCBA) of 3 assemblings; 4 source drive IC; 5 first data lines; 6 last data lines; The signal terminal that 7 first data lines are connected with PCBA; The signal terminal that 8 last data lines are connected with PCBA; 9TCP bonding area; 10PCB bonding area; 11 first cablings; 12 second cablings; 13 the 3rd cablings; 14 first signal terminals; 15 secondary signal terminals; The data line of 16 sources, drain metal layer; 17 test points; 18 the 4th cablings; 19 the 5th cablings; 20 grid drive IC.
Embodiment
The basic thought of the utility model embodiment is: for the COF of display base plate one side, on display base plate, arrange and cross the first cabling of the fan-shaped distributive province of data line, and the second cabling that two one end are connected with two end points of described the first cabling respectively, the other end is connected with two first signal terminals that are arranged on printed circuit board (PCB) welding region is respectively set on COF; Two one end are set on described COF and are connected with source drive IC respectively, the 3rd cabling that the other end is connected with two secondary signal terminals that are arranged on printed circuit board (PCB) welding region respectively; Wherein, described two the second cablings lay respectively at the outside of the first data lines and last data lines, and described two article of the 3rd cabling lays respectively at the inner side of the first data lines and last data lines; Described two first signal terminals and two secondary signal terminals are all adjacent with, two signal terminals being connected with the first data lines and last data lines.
Below in conjunction with drawings and the specific embodiments, the utility model is described in further detail.
Fig. 5 is display base plate one side arranges described in the utility model embodiment COF and the structural representation of panel and PCBA annexation, as shown in Figure 5, on described display base plate 1, be provided with the first cabling 11 that crosses the fan-shaped distributive province of data line, on described COF, be provided with the second cabling 12 that two one end are connected with two end points of described the first cabling 11 respectively, the other end is connected with two first signal terminals 14 that are arranged on PCB bonding area10 respectively; On described COF, be also provided with the 3rd cabling 13 that two one end are connected with described source drive IC 4 respectively, the other end is connected with two secondary signal terminals 15 that are arranged on described PCB bonding area10 respectively; Wherein, the outside that described two the second cablings 12 lay respectively at the first data lines 5 and last data lines 6 (is in Fig. 5, to be positioned at the left side of described the first data lines 5 and non-intersect, and be positioned at the right side of described last data lines 6 and non-intersect), article described two, the 3rd cabling 13 lays respectively at the inner side (be to be positioned at the right side of described the first data lines 5 and non-intersect in Fig. 5, and be positioned at the left side of described last data lines 6 and non-intersect) of the first data lines 5 and last data lines 6; Described two first signal terminals 14 and two secondary signal terminals 15 are all adjacent with signal terminal 8 with described signal terminal 7.As shown in Figure 5, the left side of a described signal terminal 7 of first signal terminal 14 next-door neighbour, the right side of the described signal terminal 8 of another first signal terminal 14 next-door neighbour; The right side of a described signal terminal 7 of secondary signal terminal 15 next-door neighbour, the left side of the described signal terminal 8 of another secondary signal terminal 15 next-door neighbour.
Preferably, described the first cabling, the second cabling and the 3rd cabling are comprised of metal material.
Preferably, the width of the width of described the first cabling and the data line of described source drive IC in the fan-shaped distributive province of described data line is suitable, the second cabling is suitable with the width of described COF2 upward wiring with the width of the 3rd cabling.Certainly, the width of the upper all cablings of COF is not identical, and when practical operation, described the second cabling and the 3rd cabling are more wide better, still, and because wiring space is limited; The width of described the second cabling and the 3rd cabling is suitable with the trace width on COF, meets integral layout.
Preferably, described the first cabling 11 is arranged at the gate metal layer of array base palte in described display base plate 1, and with layer, described the first cabling 11 is comprised of gate metal with gate metal layer.Described the first cabling 11 and source, drain metal layer are isolated by insulation course, and intersect in the horizontal direction (being positioned at different layers) with the data line 16 of source, drain metal layer, as shown in Figure 5.
In actual application, as shown in Figure 6, owing to being provided with described the first cabling 11, two the second cablings 12, two article of the 3rd cabling 13, and two first signal terminals 14 and two secondary signal terminals 15, therefore, described the first data lines 5 and last data lines 6 with described with PCBA3(Fig. 6 for illustrating) PIN of interval sky between signal terminal 7 PIN adjacent with both sides with signal terminal 8 that be connected, the PIN of described sky refers to there is no signal in described PIN, because there is no signal in first, second and third coupled cabling; The PIN of described sky is: described two first signal terminals 14 and two secondary signal terminals 15, because interval between PIN becomes large, so PIN7 is difficult for being interfered with the data-signal that has high frequency in PIN8, exchange (with respect to public electrode voltages) characteristic again, guarantee the display effect of the pixel that described the first data lines 5 and last data lines 6 drive, avoided line to show bad.
Preferably, on PCBA3 described in the utility model, be also provided with two test points 17 that are connected with described two first signal terminals 14 respectively, as shown in Figure 7, can realize the measurement to signal in any data lines in the situation that not destroying viewing area.
Concrete, if measure the signal in a certain data lines, cut off this data lines 16 of (as shown in FIG. *) corresponding source, drain metal layer; In addition, by solder technology such as laser, this data lines 16 after cut-out is connected with described the first cabling 11, the crossing position of data line 16 of corresponding described the first cabling 11 in described connected position (as shown in FIG. ●) and source, drain metal layer, and by described test point 17 measuring-signals.Here, the object of described cut-out is the interference of eliminating from the measurement of display base plate inside, thereby the output signal of source drive IC 4 described in Obtaining Accurate determines that whether output signal is abnormal.
Preferably, described test point 17 also can be arranged on described COF upper (in Fig. 7 for illustrating).
In addition, the embodiment shown in corresponding diagram 7, the utility model also can, by the outer filling data-signal of described test point 17 to any row or several row pixel, enrich analyst and resolve the bad means of line.Now, can fill with high and low frequency outward at selected pixel region, AC and DC signal, in implementation process, can the data line after cut-out be connected with described the first cabling by solder technology such as above-mentioned laser, as shown in Figure 8, provide the schematic diagram of filling with data-signal to three row pixels at home and abroad.
Preferably, the utility model embodiment also proposes following scheme to realize the measurement to signal in any grid line:
Each COF2 for display base plate opposite side, on display base plate, arrange and cross the 4th cabling 18 of the fan-shaped distributive province of grid line, and the 5th cabling 19 that two one end are connected with two end points of described the 4th cabling 18 respectively, the other end is connected with two test points 17 that are arranged on COF2 is respectively set on COF2; Wherein, described two article of the 5th cabling 19 lays respectively at the outside of first grid line and last root grid line, as shown in Figure 9.
Wherein, described the 4th cabling and the 5th cabling are comprised of metal material; The width of the width of described the 4th cabling and grid drive IC 20 grid line in the fan-shaped distributive province of grid line is suitable; The width of the width of described the 5th cabling and COF upward wiring is suitable.Described the 4th cabling is arranged at source, the drain metal layer of array base palte in described display base plate, with described source, the same layer of drain metal layer.The present embodiment can be used for the signal in any grid line to measure, approximate shown in implementation method and Fig. 7, no longer describes in detail herein.
Preferably, the utility model also can be by manual (carrying out manual measurement for a small amount of product) or automatically (by equipment, requirement equipment can Automatic-searching test point, automatically records resistance value etc.) mode measure Panel and COF, and the electrical connection state between COF and PCBA.Concrete, as shown in figure 10, resistance tester is connected between described two test points 17, the measurement result showing from resistance tester can judge Panel1 and COF2, and the electrical connection state between COF2 and PCBA3, as shown in figure 10, if resistance measurement result is less, the good connection of four oval positions shown in showing; Otherwise, if resistance measurement result is larger, show to have at least a place to connect in four positions bad.Can be with reference to different model product about determining of resistance size.
It should be noted that, because cabling described in this programme has two test points on PCBA, and the position that described cabling is connected with Panel with COF, COF through PCBA, if these positions have place's electrically conducting poor, the resistance value between two test points on PCBA is very large; Otherwise if point-to-point transmission resistance value is very little, this explanation PCBA and COF, COF and Panel electrically conducting situation are relatively good.
The above, be only preferred embodiment of the present utility model, is not intended to limit protection domain of the present utility model.
Claims (11)
1. a display panel, comprise: display base plate, be arranged at the film integrated chip of display base plate one side and opposite side, and the assembled printed circuit boards being connected with described display base plate by described film integrated chip, each is arranged on the film integrated chip of display base plate one side active drive integrated circult is set, and the first data lines and last data lines are connected with described source drive integrated circult; It is characterized in that,
For the film integrated chip that is arranged at display base plate one side, on described display base plate, be provided with the first cabling that crosses the fan-shaped distributive province of data line, on described film integrated chip, be provided with the second cabling that two one end are connected with two end points of described the first cabling respectively, the other end is connected with two first signal terminals that are arranged on printed circuit board (PCB) welding region respectively; On described film integrated chip, be also provided with the 3rd cabling that two one end are connected with described source drive integrated circult respectively, the other end is connected with two secondary signal terminals that are arranged on described printed circuit board (PCB) welding region respectively;
Wherein, described two the second cablings lay respectively at the outside of described the first data lines and last data lines, and described two article of the 3rd cabling lays respectively at the inner side of the first data lines and last data lines; Described two first signal terminals and two secondary signal terminals are all adjacent with, two signal terminals being connected with described the first data lines and last data lines.
2. display panel according to claim 1, is characterized in that, described the first cabling is arranged at the gate metal layer of array base palte in described display base plate, with the same layer of described gate metal layer.
3. display panel according to claim 1, is characterized in that, described the first cabling, the second cabling and the 3rd cabling are comprised of metal material.
4. display panel according to claim 3, is characterized in that, described the first cabling is comprised of gate metal material.
5. according to the display panel described in any one in claim 1-4, it is characterized in that, on the film integrated chip of described display base plate one side or on assembled printed circuit boards, be also provided with the test point being connected with described first signal terminal.
6. according to the display panel described in any one in claim 1-4, it is characterized in that, film integrated chip for display base plate opposite side, on described display base plate, be also provided with the 4th cabling that crosses the fan-shaped distributive province of grid line, on film integrated chip, be also provided with the 5th cabling that two one end are connected with two end points of described the 4th cabling respectively, the other end is connected with two test points that are arranged on described film integrated chip respectively; Wherein, described two article of the 5th cabling lays respectively at the outside of first grid line and last root grid line.
7. display panel according to claim 6, is characterized in that, described the 4th cabling is arranged at source, the drain metal layer of array base palte in described display base plate, with described source, the same layer of drain metal layer.
8. display panel according to claim 6, is characterized in that, described the 4th cabling and the 5th cabling are comprised of metal material.
9. display panel according to claim 8, is characterized in that, described the 4th cabling is comprised of source, drain metal material.
10. according to the display panel described in any one in claim 1-4, it is characterized in that, the width of the width of described the first cabling and the data line of described source drive integrated circult in the fan-shaped distributive province of described data line is suitable; The width of the width of described the second cabling and the 3rd cabling and described film integrated chip upward wiring is suitable.
11. display panels according to claim 6, is characterized in that, the width of the width of described the 4th cabling and the grid-driving integrated circuit grid line in the fan-shaped distributive province of grid line is suitable; The width of the width of described the 5th cabling and film integrated chip upward wiring is suitable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320517395.3U CN203455565U (en) | 2013-08-22 | 2013-08-22 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320517395.3U CN203455565U (en) | 2013-08-22 | 2013-08-22 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203455565U true CN203455565U (en) | 2014-02-26 |
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ID=50135429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320517395.3U Expired - Lifetime CN203455565U (en) | 2013-08-22 | 2013-08-22 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203455565U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831299A (en) * | 2018-06-07 | 2018-11-16 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel, display module and electronic device |
| CN109239999A (en) * | 2018-11-12 | 2019-01-18 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
-
2013
- 2013-08-22 CN CN201320517395.3U patent/CN203455565U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831299A (en) * | 2018-06-07 | 2018-11-16 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel, display module and electronic device |
| CN108831299B (en) * | 2018-06-07 | 2020-07-10 | 武汉华星光电半导体显示技术有限公司 | Display panel, display module and electronic device |
| CN109239999A (en) * | 2018-11-12 | 2019-01-18 | 惠科股份有限公司 | Flexible circuit board, display panel and display device |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140226 |
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| CX01 | Expiry of patent term |