CN203313044U - Full-bridge phase-shift driving circuit - Google Patents
Full-bridge phase-shift driving circuit Download PDFInfo
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- CN203313044U CN203313044U CN2013202184015U CN201320218401U CN203313044U CN 203313044 U CN203313044 U CN 203313044U CN 2013202184015 U CN2013202184015 U CN 2013202184015U CN 201320218401 U CN201320218401 U CN 201320218401U CN 203313044 U CN203313044 U CN 203313044U
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Abstract
The utility model provides a full-bridge phase-shift driving circuit comprising an SG3525 model PWM control chip, a first NOR gate, a second NOR gate, a third NOR gate and a D trigger. The reset end and the set end of the D trigger are grounded. The clock input end of the D trigger is connected with a pin 4 of the PWM control chip. The output end of the D trigger is connected with the data input end of the D trigger. The pin 11 and the pin 14 of the PWM control chip are connected to two input ends of the first NOR gate respectively. The output of the first NOR gate is divided into two paths, one path and the output end Q of the D trigger are respectively connected to the two input ends of the second NOR gate, and the other path and the output end of the D trigger are respectively connected to the two input ends of the third NOR gate. The output end Q and the output end of the D trigger, the output end of the second NOR gate and the output end of the third NOR gate are respectively used as driving signal output ends of driving signals needed by four power MOSFETs. According to the full-bridge phase-shift driving circuit, two groups of driving waveforms with different phases and frequency are generated through the shaping amplification and extraction of waveform, and the cost is low.
Description
Technical field
The utility model relates to Switching Power Supply, relates in particular to a kind of whole bridge phase-shift drive circuit that is applied to Switching Power Supply.
Background technology
Switching Power Supply is to utilize modern power electronics technology, and the time ratio that the control switch pipe turns on and off maintains a kind of power supply of regulated output voltage, and Switching Power Supply generally by pulse width modulation (PWM), controls IC and MOSFET forms.The UC3875 chip of Unitrode company is the control device of design phase-shifting zero-voltage resonance PWM Switching Power Supply, and it can carry out phase shifts to the phase place of full-bridge switch, realizes full bridge power level frequency pulse width modulation controlled surely.UC3875 has four and independently exports drive end and can directly drive four power MOSFET tubes, the single spin-echo of OUTA and OUTB wherein, the single spin-echo of OUTC and OUTD, drive respectively A/B, two half-bridges of D/C, can carry out separately the control of conducting time delay (being Dead Time), in this dead band, guarantee the output capacitance discharge off of next device for power switching in the time, for the switching device that is about to conducting provides the voltage turn-on condition, under full-bridge mode, the advantage of phase shifting control finds full expression, but UC3875's is expensive.So, how to provide a kind of can the realization just to become research topic of the present utility model with UC3875 identical function and whole bridge phase-shift drive circuit with low cost.
Summary of the invention
The purpose of this utility model is to provide a kind of and can realizes and UC3875 identical function and whole bridge phase-shift drive circuit with low cost.
For achieving the above object, the technical solution adopted in the utility model is: a kind of whole bridge phase-shift drive circuit comprises that a model is the pwm chip, the first NOR gate, second or non-, the 3rd NOR gate and a d type flip flop of SG3525; Wherein:
The reset terminal of described d type flip flop and set end ground connection, the input end of clock of d type flip flop is connected with the pin of described pwm chip 4, the output of d type flip flop
With the data input pin of d type flip flop, be connected;
The pin 11 of described pwm chip and pin 14 are connected to respectively two inputs of the first NOR gate, the output of described the first NOR gate is divided into two-way, the output Q of one road and d type flip flop is connected to respectively two inputs of the second NOR gate, the output of another road and d type flip flop
Be connected to respectively two inputs of the 3rd NOR gate;
Output Q and the output of described d type flip flop
, the second NOR gate output and the 3rd NOR gate output be respectively as the driving signal output part of four required driving signals of power MOSFET tube.
Related content in technique scheme is explained as follows:
1, in such scheme, described SG3525 is a very common pwm chip, and in the utility model, SG3525 adopts operated by rotary motion to get final product, by RC setpoint frequency, setting Dead Time.
2, in such scheme, what the pin 11 of described pwm chip and pin 14 were exported is two reverse waveforms, and pin 11 and pin 14 are input to the first NOR gate, the waveform that is Dead Time of the first NOR gate output; The pin 4 that the input end of clock CLK of d type flip flop is connected to SG3525, the data input pin of d type flip flop and output
Connect, export a two divided-frequency, frequency is half of pin 4 output frequencies of SG3525, like this output Q of d type flip flop with
Just become the driving signal of one group of output; The output Q of d type flip flop and the output of the first NOR gate are as the input of the second NOR gate, and the output waveform of the second NOR gate is that the shaping of pwm chip pin 14 output waveforms is amplified, the output of d type flip flop
With the output of the first NOR gate input as the 3rd NOR gate, the output waveform of the 3rd NOR gate is that the shaping of pwm chip pin 11 output waveforms is amplified, the output of the second NOR gate and the 3rd NOR gate becomes the driving signal of another group output, and the second NOR gate is different with the phase place of the 3rd NOR gate output waveform; SG3525 can only export one group of waveform originally, and the utility model amplifies and with the method for extracting the waveform that pwm chip pin 4OSCOUT produces, produced two groups phase place is different, frequency is identical, the drive waveforms of excellent performance by shaping.
The utility model operation principle and advantage:
What the pin 11 of pwm chip described in the utility model and pin 14 were exported is two reverse waveforms, and pin 11 and pin 14 are input to the first NOR gate, the waveform that is Dead Time of the first NOR gate output; The pin 4 that the input end of clock CLK of d type flip flop is connected to SG3525, the data input pin of d type flip flop and output
Connect, export a two divided-frequency, frequency is half of pin 4 output frequencies of SG3525, like this output Q of d type flip flop with
Just become the driving signal of one group of output; The output Q of d type flip flop and the output of the first NOR gate are as the input of the second NOR gate, and the output waveform of the second NOR gate is that the shaping of pwm chip pin 14 output waveforms is amplified, the output of d type flip flop
With the output of the first NOR gate input as the 3rd NOR gate, the output waveform of the 3rd NOR gate is that the shaping of pwm chip pin 11 output waveforms is amplified, the output of the second NOR gate and the 3rd NOR gate becomes the driving signal of another group output, and the second NOR gate is different with the phase place of the 3rd NOR gate output waveform; SG3525 can only export one group of waveform originally, the utility model amplifies and with the method for extracting the waveform that pwm chip pin 4OSCOUT produces, has produced two groups phase place is different, frequency is identical, the drive waveforms of excellent performance by shaping, and price is far below the price of SG3525 chip.
The accompanying drawing explanation
Accompanying drawing 1 is the utility model embodiment circuit diagram;
Accompanying drawing 2 is the utility model embodiment sequential chart.
In above accompanying drawing: U1, pwm chip; U2, d type flip flop; D, data input pin; CLK, input end of clock; RST, reset terminal; S, set end; A, the first NOR gate; B, the second NOR gate; C, the 3rd NOR gate; Q7, the 7th NPN type triode; R4, the 4th resistance; R5, the 5th resistance; R2, the second resistance; C1, the first electric capacity; Q1, a NPN type triode; Q2, the second N-channel MOS field effect transistor; Q3, the 3rd positive-negative-positive triode; Q4, the 4th NPN type triode; Q5, the 5th N-channel MOS field effect transistor; Q6, the 6th positive-negative-positive triode; Q9, the 9th NPN type triode; Q12, the 12 positive-negative-positive triode; Q14, the 14 NPN type triode; Q16, the 16 positive-negative-positive triode; C3, the 3rd electric capacity; C5, the 5th electric capacity; D1, the first diode; D2, the second diode; D3, the 3rd diode; D4, the 4th diode; C2, the second electric capacity; R7, the 7th resistance; Q8, the 8th NPN type triode; R6, the 6th resistance; Q11, the 11 positive-negative-positive triode; Q10, the tenth N-channel MOS field effect transistor; C4, the 4th electric capacity; R9, the 9th resistance; Q13, the 13 NPN type triode; R8, the 8th resistance; Q17, the 17 positive-negative-positive triode; Q15, the 15 N-channel MOS field effect transistor; TR, isolating transformer.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
Embodiment: a kind of whole bridge phase-shift drive circuit
Shown in accompanying drawing 1, comprise that a model is pwm chip U1, the first NOR gate A, second or non-B, the 3rd NOR gate C and a d type flip flop U2 of SG3525.
The reset terminal RST of described d type flip flop U2 and set end S ground connection, the input end of clock CLK of d type flip flop U2 is connected with the pin 4 of described pwm chip, the output of d type flip flop U2
With the data input pin D of d type flip flop U2, be connected, and output
By the 5th capacitor C 5 ground connection.
The pin 11 of described pwm chip U1 and pin 14 are connected to respectively two inputs of the first NOR gate A, the output of described the first NOR gate A is divided into two-way, the output Q of one road and d type flip flop U2 is connected to respectively two inputs of the second NOR gate B, the output of another road and d type flip flop U2
Be connected to respectively two inputs of the 3rd NOR gate C.
Output Q and the output of described d type flip flop U2
, the second NOR gate B output and the 3rd NOR gate C output be as the driving signal output part of four required driving signals of power MOSFET tube.
The pin 4 of described pwm chip U1 is connected with the input end of clock CLK of described d type flip flop U2 by one the 7th NPN type triode Q7, wherein: the base stage of described the 7th NPN type triode Q7 is connected with the pin 4 of pwm chip U1, the grounded emitter of the 7th NPN type triode Q7, the collector electrode of the 7th NPN type triode Q7 separates two-way, one tunnel is connected with the input end of clock CLK of d type flip flop U2, another road is connected with the pin 15 of pwm chip U1 by one second resistance R 2, the 7th NPN type triode Q7 amplifies for the shaping to pwm chip U1 pin 4 output waveforms.
The pin 13 of described pwm chip U1 and pin 15 short circuits, pin 13 is the collector electrode of SG3525 chip internal triode, sufficient power supply is provided for pin 11 and pin 14 by pin 15.
The pin 11 of described pwm chip U1 is by the 4th resistance R 4 ground connection, and pin 14, by the 5th resistance R 5 ground connection, its role is to anti-stop signal and disturbs.
The pin 12 of described pwm chip U1 is connected with pin 15 by the first capacitor C 1.
Described the 3rd NOR gate C output is provided with the first drive circuit, this first drive circuit is comprised of a NPN type triode Q1 and the 3rd positive-negative-positive triode Q3, the base stage of the one NPN type triode Q1 and the 3rd positive-negative-positive triode Q3 is connected with the output of the 3rd NOR gate C, the emitter of the one NPN type triode Q1 is connected with the emitter of the 3rd positive-negative-positive triode Q3, the collector electrode of the one NPN type triode Q1 is connected with pin 13 with the pin 15 of described pwm chip U1, the grounded collector of the 3rd positive-negative-positive triode, the emitter of the one NPN type triode Q1 and the 3rd positive-negative-positive triode Q3 is connected with the grid of the second N-channel MOS field effect transistor Q2 by after the first resistance R 1 and the first diode D1 parallel connection.
Described the second NOR gate B output is provided with the second drive circuit, this second drive circuit is comprised of the 4th NPN type triode Q4 and the 6th positive-negative-positive triode Q6, the base stage of the 4th NPN type triode Q4 and the 6th positive-negative-positive triode Q6 is connected with the output of the second NOR gate B, the emitter of the 4th NPN type triode Q4 is connected with the emitter of the 6th positive-negative-positive triode Q6, the collector electrode of the 4th NPN type triode Q4 is connected with pin 13 with the pin 15 of described pwm chip U1, the grounded collector of the 6th positive-negative-positive triode Q6, the emitter of the 4th NPN type triode Q4 and the 6th positive-negative-positive triode Q6 is connected with the grid of the 5th N-channel MOS field effect transistor Q5 by after the 3rd resistance R 3 and the second diode D2 parallel connection.
The output Q of described d type flip flop U2 is provided with the 3rd drive circuit, the 3rd drive circuit is comprised of the 9th NPN type triode Q9 and the 12 positive-negative-positive triode Q12, the base stage of the 9th NPN type triode Q9 and the 12 positive-negative-positive triode Q12 is connected with the output Q of d type flip flop U2, the emitter of the 9th NPN type triode Q9 is connected with the emitter of the 12 positive-negative-positive triode Q12, the collector electrode of the 9th NPN type triode Q9 is connected with pin 13 with the pin 15 of described pwm chip U1, the grounded collector of the 12 positive-negative-positive triode Q12, the emitter of the 9th NPN type triode Q9 and the emitter of the 12 positive-negative-positive triode Q12 are connected with an end of an isolating transformer TR armature winding by the 3rd capacitor C 3.
The output of described d type flip flop U2
Be provided with the moving circuit of 4 wheel driven, the moving circuit of this 4 wheel driven is comprised of the 14 NPN type triode Q14 and the 16 positive-negative-positive triode Q16, the 14 NPN type triode Q14 and the base stage of the 16 positive-negative-positive triode Q16 and the output of d type flip flop U2
Connect, the emitter of the 14 NPN type triode Q14 is connected with the emitter of the 16 positive-negative-positive triode Q16, the collector electrode of the 14 NPN type triode Q14 is connected with pin 13 with the pin 15 of described pwm chip U1, the grounded collector of the 16 positive-negative-positive triode Q16, the emitter of the 14 NPN type triode Q14 and the emitter of the 16 positive-negative-positive triode Q16 are connected with the other end of isolating transformer TR armature winding.
Above-mentioned each drive circuit is for strengthening driving force to adapt to powerful occasion, and described isolating transformer TR is for level conversion, and isolating transformer TR left side is low-voltage, and right side is high voltage.
Described isolating transformer TR has two secondary winding, is respectively equipped with a level shifting circuit corresponding to two secondary winding.
Corresponding to one of them secondary winding, be provided with the first level shifting circuit, this first level shifting circuit comprises the 8th NPN type triode Q8 and the 11 positive-negative-positive triode Q11, between the emitter of the 8th NPN type triode Q8 and the 11 positive-negative-positive triode Q11, connect by the 6th resistance R 6, the collector electrode of the 11 positive-negative-positive triode Q11 is connected with an end of this secondary winding, the base stage of the 8th NPN type triode Q8 and the 11 positive-negative-positive triode Q11 is connected and passes through and with the other end of secondary winding, is connected after the second capacitor C 2 and the 7th resistance R 7 parallel connections, the collector electrode of the 8th NPN type triode Q8 is connected with the other end of this secondary winding by the 3rd diode D3, the emitter of the 11 positive-negative-positive triode Q11 is connected with the grid of the tenth N-type metal-oxide-semiconductor field effect transistor.
Corresponding to another winding, be provided with the second electrical level change-over circuit, this second electrical level change-over circuit comprises the 13 NPN type triode Q13 and the 17 positive-negative-positive triode Q17, between the emitter of the 13 NPN type triode Q13 and the 17 positive-negative-positive triode Q17, connect by the 8th resistance R 8, the collector electrode of the 17 positive-negative-positive triode Q17 is connected with an end of this secondary winding, the base stage of the 13 NPN type triode Q13 and the 17 positive-negative-positive triode Q17 is connected and passes through and with the other end of this secondary winding, is connected after the 4th capacitor C 4 and the 9th resistance R 9 parallel connections, the collector electrode of the 13 NPN type triode Q13 is connected with the other end of this secondary winding by the 4th diode D4, the emitter of the 17 positive-negative-positive triode Q17 is connected with the grid of the 15 N-channel MOS field effect transistor.
Described SG3525 is a very common pwm chip, and in the utility model, SG3515 adopts operated by rotary motion to get final product, by RC setpoint frequency, setting Dead Time.
Shown in accompanying drawing 2, in accompanying drawing 2, OUTA is the output waveform of SG3525 pin 11, and OUTB is the output waveform of SG3525 pin 14, and A_OUT is the output waveform of the first NOR gate A,
Output for d type flip flop
Output waveform, Q is the output waveform of the output Q of d type flip flop, CLK is the d type flip flop input waveform of input CLK all the time, C_OUT is the output waveform of the 3rd NOR gate C, B_OUT is the output waveform of the second NOR gate B.
Visible by accompanying drawing 2, what the pin 11 of described pwm chip and pin 14 were exported is two reverse waveforms, and pin 11 and pin 14 are input to the first NOR gate, the waveform that is Dead Time of the first NOR gate output; The pin 4 that the input end of clock CLK of d type flip flop is connected to SG3525, the data input pin of d type flip flop and output
Connect, export a two divided-frequency, frequency is half of pin 4 output frequencies of SG3525, like this output Q of d type flip flop with
Just become the driving signal of one group of output; The output Q of d type flip flop and the output of the first NOR gate are as the input of the second NOR gate, and the output waveform of the second NOR gate is that the shaping of pwm chip pin 14 output waveforms is amplified, the output of d type flip flop
With the output of the first NOR gate input as the 3rd NOR gate, the output waveform of the 3rd NOR gate is that the shaping of pwm chip pin 11 output waveforms is amplified, the output of the second NOR gate and the 3rd NOR gate becomes the driving signal of another group output, and the second NOR gate is different with the phase place of the 3rd NOR gate output waveform; SG3525 can only export one group of waveform originally, the utility model amplifies by shaping and extract to extract waveform display method that pwm chip pin 4OSCOUT produces and produced two groups phase place is different, frequency is identical, the drive waveforms of excellent performance, and price is far below the price of SG3525 chip.
Above-described embodiment only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the person skilled in the art can understand content of the present utility model and implement according to this, can not limit protection range of the present utility model with this.All equivalences of doing according to the utility model Spirit Essence change or modify, within all should being encompassed in protection range of the present utility model.
Claims (5)
1. whole bridge phase-shift drive circuit is characterized in that: comprise that a model is the pwm chip (U1), the first NOR gate (A), second or non-(B), the 3rd NOR gate (C) and a d type flip flop (U2) of SG3525; Wherein:
The reset terminal (RST) of described d type flip flop (U2) and set end (S) ground connection, the input end of clock (CLK) of d type flip flop (U2) is connected with the pin 4 of described pwm chip, the output of d type flip flop (U2)
With the data input pin (D) of d type flip flop (U2), be connected;
The pin 11 of described pwm chip (U1) and pin 14 are connected to respectively two inputs of the first NOR gate (A), the output of described the first NOR gate (A) is divided into two-way, the output Q of one road and d type flip flop (U2) is connected to respectively two inputs of the second NOR gate (B), the output of another road and d type flip flop (U2)
Be connected to respectively two inputs of the 3rd NOR gate (C);
Output Q and the output of described d type flip flop (U2)
, the second NOR gate (B) output and the 3rd NOR gate (C) output be as the driving signal output part of four required driving signals of power MOSFET tube.
2. whole bridge phase-shift drive circuit according to claim 1, it is characterized in that: the pin 4 of described pwm chip (U1) is connected with the input end of clock (CLK) of described d type flip flop (U2) by one the 7th NPN type triode (Q7), wherein: the base stage of described the 7th NPN type triode (Q7) is connected with the pin 4 of pwm chip (U1), the grounded emitter of the 7th NPN type triode (Q7), the collector electrode of the 7th NPN type triode (Q7) separates two-way, one tunnel is connected with the input end of clock (CLK) of d type flip flop (U2), another road is connected with the pin 15 of pwm chip (U1) by one second resistance (R2).
3. whole bridge phase-shift drive circuit according to claim 1, is characterized in that: corresponding to output Q and the output of described d type flip flop (U2)
, four of the second NOR gate (B) output and the 3rd NOR gate (C) outputs drive signal output part and are respectively equipped with one drive circuit, described drive circuit is comprised of a NPN type triode and a positive-negative-positive triode, described NPN type triode is connected with the emitter of positive-negative-positive triode, the collector electrode of NPN type triode is connected with pin 13 with the pin 15 of described pwm chip (U1), the grounded collector of positive-negative-positive triode, each drives the base stage of NPN type triode and positive-negative-positive triode in the drive circuit that signal output part is corresponding and with this driving signal output part, is connected simultaneously.
4. whole bridge phase-shift drive circuit according to claim 1, is characterized in that: the pin 13 of described pwm chip (U1) and pin 15 short circuits.
5. whole bridge phase-shift drive circuit according to claim 1 is characterized in that: the pin 11 of described pwm chip (U1) and pin 14 are respectively by a grounding through resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013202184015U CN203313044U (en) | 2013-04-25 | 2013-04-25 | Full-bridge phase-shift driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013202184015U CN203313044U (en) | 2013-04-25 | 2013-04-25 | Full-bridge phase-shift driving circuit |
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| Publication Number | Publication Date |
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| CN203313044U true CN203313044U (en) | 2013-11-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013202184015U Expired - Fee Related CN203313044U (en) | 2013-04-25 | 2013-04-25 | Full-bridge phase-shift driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450002A (en) * | 2015-12-01 | 2016-03-30 | 许继电源有限公司 | Full-soft switch drive circuit of switching power supply |
-
2013
- 2013-04-25 CN CN2013202184015U patent/CN203313044U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450002A (en) * | 2015-12-01 | 2016-03-30 | 许继电源有限公司 | Full-soft switch drive circuit of switching power supply |
| CN105450002B (en) * | 2015-12-01 | 2018-05-29 | 许继电源有限公司 | A kind of ully-soft switchingr driving circuit of Switching Power Supply |
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Granted publication date: 20131127 Termination date: 20160425 |