CN203312299U - Super barrier rectifying device - Google Patents
Super barrier rectifying device Download PDFInfo
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- CN203312299U CN203312299U CN2013203735797U CN201320373579U CN203312299U CN 203312299 U CN203312299 U CN 203312299U CN 2013203735797 U CN2013203735797 U CN 2013203735797U CN 201320373579 U CN201320373579 U CN 201320373579U CN 203312299 U CN203312299 U CN 203312299U
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Abstract
The utility model discloses a super barrier rectifying device. The rectifying device retains the characteristics of conventional Schottky barrier rectifying devices and has an MOS structure; and a first conductive-type drift region under grids is provided with second conductive-type shallow injection regions. When the rectifying device is connected with a forward voltage, second conductive-type injection regions do not influence conduction of the current, so that forward voltage drop Vf is not influenced; and when the rectifying device is connected with a backward voltage, the second conductive-type injection regions can pinch the current off rapidly, so that Ir is smaller and reverse recovery is both rapid and soft.
Description
Technical field
The utility model relates to a kind of power semiconductor, refers to especially a kind of superpotential base rectifying device.
Background technology
The power semiconductor rectifying device includes Schottky diode, and Schottky diode is to contact with semiconductor with noble metal (as gold, silver, platinum, titanium, nickel, molybdenum etc.), the semiconductor device of making to form potential barrier of heterogenous junction.This device has following problem:
1) the forward voltage drop Vf of device depends mainly on metal and contacts potential barrier with semiconductor, for regulating Vf to meet the demand of different application occasion, needs to regulate the constitution and formation of barrier metal, and this causes the adjusting process complexity of Vf and is difficult to meet the multifarious requirement of Vf.
2) reverse leakage current causes more greatly reverse power dissipation higher, and this problem can aggravate with the rising of temperature, and its reliability in application is reduced.
3) use precious metal material, cost is high, and because heavy metal stains, its manufacturing process and CMOS standard technology are difficult to compatibility.
The above weak point of Schottky diode has increased its technology difficulty and manufacturing cost, has reduced its reliability in application.
At present Chinese patent ZL01143693.X and Chinese patent ZL01800833.X disclose respectively a kind of " manufacturing power rectifier device to change improving one's methods and obtained device of running parameter " and a kind of " preparing power rectifier device with the method for change operating parameter and the device made thereof ", these two kinds of semiconductor rectifier devices are not used Schottky barrier, the metal level of its practical novel employing and CMOS process compatible, by the MOS structure of PN junction, realize the function of device, increased the device manufacture compatibility, improved the controllability of device Vf parameter.
Several important parameters of power semiconductor rectifier comprise that forward voltage drop Vf(is hereinafter to be referred as Vf), reverse leakage Ir, reverse recovery time Trr and the softness oppositely recovered.Wherein Vf, Ir and Trr have determined power consumption size and the efficiency of power semiconductor rectifier, and Vf is lower, and Ir and Trr are less, and the power consumption of device is less, and efficiency is just higher; And the softness of Ir, Trr and oppositely recovery has determined reliability and the range of application of device when application, Ir and reverse recovery time are less, and the reliability of oppositely recovering softer device is just higher, and range of application is also just wider.
By upper two pieces of Chinese patents, can find that still there is following problem in it;
1) the P type trap of this type of rectifying device (is dark P district in patent ZL01143693.X, the dark boron of patent ZL01800833.X cave) its Vf and two parameters of Ir have been determined, the wide Vf of P type trap becomes large, Ir diminishes, the narrow Vf of P type trap diminishes, and it is large that Ir becomes, and namely there are the seesaw effect in Vf parameter and Ir parameter, and Ir requires, in the scope of 10uA, to have limited the space that the Vf value is further dwindled during practical application;
2) this device channel length short (0.25um is to 0.1um), for obtaining Ir characteristic preferably, need denseer channel doping density, must bring the further increase of Vf value, and because raceway groove is shorter, the Ir performance worsens sharply when high temperature, cause device power consumption further to increase, reliability reduces; Because this device channel length is short, channel doping density is denseer, cause that its long reverse recovery time, oppositely to recover softness hard, large, the reliability of device power consumption reduces, is of limited application;
3) in Chinese patent ZL01143693.X, the formation of device lateral channel is through the oxide layer deposit, the oxide layer isotropic etch forms the ion implantation mask of inclination, by it, injects the horizontal gradual PN junction that ion forms channel region, as Figure 14 A, Figure 14 B in patent ZL01143693.X; In patent ZL01800833.X, the device lateral channel determined by the photoresist mask, and wherein the photoresist mask is through twice etching, and etching is used oxygen gas plasma etc. to etching, as Fig. 2 I in ZL01800833.X for the second time; These two kinds of method techniques are all more complicated, the length of these two kinds of device channel (0.25um is to 0.1um) depends on size and the pattern of the rear mask layer of corrosion in addition, and the condition of lithography registration precision and corrosion on etching after size and the pattern of mask layer affect seriously, the process window of its channel length is less and cause the process window of Vf young.Because the minimum widith to mask layer there are certain requirements, it has limited the further increase of device density, and the technique manufacture difficulty is large, and window is little, easily causes the problems such as the device parameters fluctuation is large, consistency is poor, has reduced device reliability in actual applications.
The utility model content
Technical problem to be solved in the utility model is: provide a kind of superpotential to build rectifying device, this rectifying device is under the prerequisite that guarantees device Ir performance, further reduced the forward voltage drop Vf of rectifying device, reduced Trr reverse recovery time of device, improved the softness that device oppositely recovers, improve the hot properties of device, increased the process window that device is manufactured.
For solving the problems of the technologies described above, the technical solution of the utility model is: a kind of superpotential is built rectifying device, on the cross section of rectifying device, comprise the semiconductor substrate, the bottom of this semiconductor substrate is heavily doped the first conductivity type substrate, the top of semiconductor substrate is lightly doped the first conduction type drift region, the upper surface of described semiconductor substrate is defined as first surface, the lower surface of semiconductor substrate is defined as second surface, described first surface interval is coated with several insulated gate oxide layers, all is coated with the first electrode on each insulated gate oxide layer; Described first surface does not cover several grooves of region division of described insulated gate oxide layer, and this groove extends into the first conduction type drift region by first surface; Described the first conduction type drift region is provided with the first conduction type injection region at the lateral sulcus of groove along place, described the first top, conduction type drift region is provided with the second conduction type injection region corresponding and separate with number of grooves, each second groove of conduction type injection region parcel and first corresponding conduction type injection region; Between described the second conduction type injection region, be provided with the second shallow injection region of conduction type, this shallow injection region of the second conduction type is positioned at the first top, conduction type drift region with the bottom contact of described insulated gate oxide layer and is connected with described the second conduction type injection region, on described first surface and in groove, be provided with the first metal, the first metal and the first electrode, the equal ohmic contact of first surface, be provided with the second metal with the second surface ohmic contact on described second surface.
As a kind of preferred scheme, described the first conduction type injection region forms by injecting horizontal proliferation.
As a kind of preferred scheme, the implantation dosage of described the second conduction type injection region and the second shallow injection region of conduction type is less than first conduction type injection region at least one order of magnitude of implantation dosage.
As a kind of preferred scheme, described the first electrode is conductive polycrystalline silicon.
As a kind of preferred scheme, described the first metal is provided with anode tap, and described the second metal is provided with cathode terminal.
A kind of method of manufacturing superpotential base rectifying device in claim 1, it comprises
A., the first conductive type semiconductor substrate with two apparent surfaces is provided, this the first conductive type semiconductor substrate comprises heavily doped the first conductivity type substrate and lightly doped the first conduction type drift region, and described two apparent surfaces comprise the first surface that is positioned at semiconductor substrate top and the second surface of semiconductor substrate bottom;
B. on the first surface of described semiconductor substrate, form the insulated gate oxide layer;
C. on described insulated gate oxide layer, form the first electrode;
D. on described the first electrode, cover photoresist layer;
E. optionally the described photoresist of etching forms spaced apart photoresist masking body;
F. take in e the photoresist masking body that forms as stopping etching the first electrode and insulated gate oxide layer until the first surface of semiconductor substrate;
G. with the photoresist masking body, inject first conductive type impurity formation the first conduction type injection region for stopping, these both sides, the first conduction type injection region diffuse laterally under the insulated gate oxide layer;
H. with the photoresist masking body for stopping etching groove, this groove vertically runs through the first conduction type injection region until in the first conduction type drift region;
I. with the photoresist masking body, inject second conductive type impurity formation the second conduction type injection region, this second conduction type injection region parcel groove and first conduction type injection region for stopping;
J. remove the photoresist masking body;
K. first surface injection the second conductive type impurity in described semiconductor substrate forms the second shallow injection region of conduction type under the insulated gate oxide layer;
L. in first surface deposit first metal of described semiconductor substrate;
M. in second surface deposit second metal of described semiconductor substrate.
Concrete, in step b, the generation type of insulated gate oxide layer is that the heat growth forms.The first electrode in described step c is that deposit forms.
After having adopted technique scheme, the effect of the rectifying device in the utility model is: this rectifying device is provided with the second shallow injection region of conduction type under the insulated gate oxide layer, while oppositely switching on, the existence of the second shallow injection region of conduction type is pinch off fast, in the situation that it is less not affect Vf Ir; In equal Ir situation, can regulate the width of the second conduction type injection region, Vf is descended, oppositely recover not only fast but also soft, improve range of application and the reliability of device.The method technical process is simple, and the formation of raceway groove is not subject to photoresist or oxide layer maskant size and the pattern impact after corrosion, and therefore, its process window is large, manufactures easier.
The accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is further illustrated.
Fig. 1 to Fig. 9 is the profile of each operation of the utility model embodiment;
Figure 10 is the rectifying device profile that the utility model embodiment manufacture obtains;
Figure 11 is the reverse recovery curve comparison diagram of the utility model embodiment and existing rectifier;
In accompanying drawing: 1. the first conductivity type substrate; 2. the first conduction type drift region; 3. insulated gate oxide layer; 4. the first electrode; 5. photoresist masking body; 6. the first conduction type injection region; 7. groove; 8. the second conduction type injection region; 9. the second shallow injection region of conduction type; 10. the first metal; 11. the second metal.
Embodiment
Below by specific embodiment, the utility model is described in further detail.
As shown in figure 10, a kind of superpotential is built rectifying device, on the cross section of rectifying device, comprise the semiconductor substrate, the bottom of this semiconductor substrate is heavily doped the first conductivity type substrate 1, and the top of semiconductor substrate is lightly doped the first conduction type drift region 2, and this first conductive type impurity can be N-type impurity, so corresponding the second conductive type impurity of hereinafter mentioning is the impurity of P type, vice versa, and the first conduction type that the present embodiment is selected is N-type, and the second conduction type is the P type.The upper surface of described semiconductor substrate is defined as first surface, lower surface is defined as second surface, described first surface interval is coated with several insulated gate oxide layers 3, on each insulated gate oxide layer 3, all be coated with the first electrode 4, this first electrode 4 is conductive polycrystalline silicon, and its generation type is that deposit forms.Described first surface does not cover several grooves 7 of region division of described insulated gate oxide layer 3, namely this groove 7 is between adjacent insulated gate oxide layer 3, this groove 7 extends into the first conduction type drift region 2 by first surface, and the bottom land of this groove 7 is in the first conduction type drift region 2; Described the first conduction type drift region 2 is provided with the first conduction type injection region 6 at the lateral sulcus of groove 7 along place, this the first conduction type injection region 6 is positioned at the below of insulated gate oxide layer 3, the top of described the first conduction type drift region 2 is provided with the second conduction type injection region 8 corresponding and separate with groove 7 numbers, each 8 groove 7 of parcel and corresponding first conduction type injection region 6, the second conduction type injection region; Between described the second conduction type injection region 8, be provided with the second shallow injection region 9 of conduction type, the shallow injection region 9 of this second conduction type is positioned at that 2 tops, the first conduction type drift region contact with described insulated gate oxide layer 3 bottoms and is electrically connected with described the second conduction type injection region 8, on described first surface, be provided with the first metal 10,, the first metal 10 and described the first electrode 4, the equal ohmic contact of first surface.On described second surface, be provided with the second metal 11 of second surface ohmic contact wherein, described the first conduction type injection region 6 is that horizontal proliferation forms after injecting the first conductive type impurity heat treatment.The implantation dosage of wherein said the second conduction type injection region 8 and the shallow injection region 9 of the second conduction type is less than first conduction type injection region at least one order of magnitude of 6 implantation dosages, avoid changing when forming the second conduction type injection region 8 and the second shallow injection region 9 of conduction type the first conduction type injection region 6 character.Wherein, because the first conduction type is N-type, the second conduction type is the P type, thereby described the first metal 10 is provided with anode tap, and described the second metal 11 is provided with cathode terminal.
A kind of method of manufacturing superpotential base rectifying device in claim 1, it comprises
A. as shown in Figure 1, the first conductive type semiconductor substrate with two apparent surfaces is provided, this the first conductive type semiconductor substrate comprises heavily doped the first conductivity type substrate 1 and lightly doped the first conduction type drift region 2, this first conduction type selects N, and described two apparent surfaces comprise the first surface that is positioned at semiconductor substrate top and the second surface of semiconductor substrate bottom;
B. as shown in Figure 2, on the first surface of described semiconductor substrate, form insulated gate oxide layer 3, this insulated gate oxide layer 3 is as the gate oxide of MOS structure, and this insulated gate oxide layer 3 is generally the silicon dioxide oxide layer; Its generation type is hot growth pattern;
C. on described insulated gate oxide layer 3, form the first electrode 4; The generation type of this first electrode 4 is that deposit forms;
D. as shown in Figure 3, on described the first electrode 4, cover photoresist layer; This photoresist layer integral body covers on the first electrode 4;
E. optionally the described photoresist of etching forms spaced apart photoresist masking body 5, and like this, photoresist masking body 5 namely can be used as stopping of subsequent step;
F. as shown in Figure 4, take in e the photoresist masking body 5 that forms as stopping that etching the first electrode 4 and insulated gate oxide layer 3 are until the first surface of semiconductor substrate; The below of photoresist masking body 5 is retaining the insulated gate oxide layer 3 identical with photoresist masking body 5 shapes and the first electrode 4.
G. as shown in Figure 5, with photoresist masking body 5, inject first conductive type impurity formation the first conduction type injection region 6 for stopping, these 6 both sides, the first conduction type injection region diffuse laterally into the insulated gate oxide layer 3 times, and this first conductive type impurity is N-type impurity, as phosphorus or arsenic;
H. as shown in Figure 6, with photoresist masking body 5 for stopping etching groove 7, this groove 7 vertically runs through the first conduction type injection region 6 until in the first conduction type drift region 2, the etching of this groove 7 is anisotropic etching, the sidewall of the groove 7 that its etching obtains is concordant with photoresist masking body 5, like this, a part is removed by groove 7 in the first 6 of conduction type injection regions, and the first conduction type injection region 6 below insulated gate oxide layer 3 retains the source/drain as the MOS structure;
I. as shown in Figure 7, for stopping that injecting the second conductive type impurity forms the second conduction type injection region 8, groove 7 and first conduction type injection regions 6 are wrapped up in this second conduction type injection region 8 with photoresist masking body 5; The second conductive type impurity selects p type impurity boron, the implantation dosage of p type impurity boron should be less than at least one order of magnitude of implantation dosage of the first conductive type impurity N-type phosphorus or arsenic, when injecting p type impurity boron, just can not change the type of the first conduction type injection region like this.
J. as shown in Figure 8, selective removal photoresist masking body 5, make the first electrode 4 exposed;
K. as shown in Figure 9, first surface at described semiconductor substrate injects the second conductive type impurity in 3 times formation the second shallow injection regions 9 of conduction type of insulated gate oxide layer, this second conductive type impurity is also boron, the implantation dosage of boron also should be less than order of magnitude of implantation dosage of the first conductive type impurity N-type phosphorus or arsenic herein, the integral body in the device function district that is infused in is now injected the second conductive type impurity, like this, penetrable the first electrode 4 of the second conductive type impurity and insulated gate oxide layer 3, thereby the first conduction type drift region 2 that enters into insulated gate oxide layer 3 belows forms the second shallow injection region 9 of conduction type,
L. as shown in figure 10, in first surface deposit first metal 10 of described semiconductor substrate;
M. in second surface deposit second metal 11 of described semiconductor substrate.The first metal 10 is provided with anode tap, and the second metal 11 is provided with cathode terminal.
In above-mentioned manufacture method, the first conduction type injection region 6, the second conduction type injection region 8 and the shallow injection region 9 of the second conduction type are to form after after injecting corresponding conductive type impurity, heat-treating activator impurity, it can be that last processing hot in nature activates that this heat treatment activates step, also can inject after-baking at each conductive type impurity and activate.
In sum, this rectifying device has the MOS structure, its the first conduction type injection region 6 is source/drain, insulated gate oxide layer 3 is grid, and the second conduction type injection region 8 parts and the shallow injection region of the second conduction type 9 parts that are in insulated gate oxide layer 3 belows are raceway groove, semiconductor substrate is drain/source, when rectifying device passes into forward voltage, because the voltage of the first electrode 4 is high, therefore, electrons in the second conduction type injection region 8 gathers the raceway groove place, thereby raceway groove is opened, like this, electric current is from first metal 10 → the first conduction type injection region 6 → raceway grooves → first conduction type drift region 2 → the first conductivity type substrate 1 → the second metals 11, thereby rectifying device is connected, now, flow behavior due to electric current, under normal circumstances, the second shallow injection region 9 of conduction type does not affect forward voltage drop Vf, and when rectifying device passes into reverse voltage, grid is closed, now, the second shallow injection region 9 of conduction type is pinch-off current fast, make Ir less, and oppositely recover not only fast but also soft, as shown in figure 11.Certainly, if in the situation that equal Ir, this rectifying device can further reduce forward voltage drop Vf, has reduced the reverse recovery time of device, has improved the softness that device oppositely recovers, and has improved the hot properties of device, has increased the process window that device is manufactured.
The manufacture method of this device can save the MOS channel region formation method of above-mentioned complexity, and flow process is oversimplified, and process window increases, and saves cost.This device has retained the characteristics of existing Schottky barrier rectifier spare, has simultaneously the forward fast conducting, reverse leakage current is low, forward voltage drop Vf is low and can be by ion implantation dosage and energy free adjustment, oppositely recover not only fast but also soft, improved device range of application and reliability, reduced the power consumption of device.This device does not need to use the potential barrier noble metal, manufacturing process and CMOS standard technology compatibility.
Claims (3)
1. a superpotential is built rectifying device, on the cross section of rectifying device, comprise the semiconductor substrate, the bottom of this semiconductor substrate is heavily doped the first conductivity type substrate, the top of semiconductor substrate is lightly doped the first conduction type drift region, the upper surface of described semiconductor substrate is defined as first surface, the lower surface of semiconductor substrate is defined as second surface, it is characterized in that: described first surface interval is coated with several insulated gate oxide layers, all is coated with the first electrode on each insulated gate oxide layer; Described first surface does not cover several grooves of region division of described insulated gate oxide layer, and this groove extends into the first conduction type drift region by first surface; Described the first conduction type drift region is provided with the first conduction type injection region at the lateral sulcus of groove along place, described the first top, conduction type drift region is provided with the second conduction type injection region corresponding and separate with number of grooves, each second groove of conduction type injection region parcel and first corresponding conduction type injection region; Between described the second conduction type injection region, be provided with the second shallow injection region of conduction type, this shallow injection region of the second conduction type is positioned at the first top, conduction type drift region with the bottom contact of described insulated gate oxide layer and is connected with described the second conduction type injection region, on described first surface and in groove, be provided with the first metal, the first metal and the first electrode, the equal ohmic contact of first surface, be provided with the second metal with the second surface ohmic contact on described second surface.
2. a kind of superpotential as claimed in claim 1 is built rectifying device, and it is characterized in that: described the first electrode is conductive polycrystalline silicon floor.
3. a kind of superpotential as claimed in claim 2 is built rectifying device, and it is characterized in that: described the first metal is provided with anode tap, and described the second metal is provided with cathode terminal.
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| CN2013203735797U CN203312299U (en) | 2013-06-26 | 2013-06-26 | Super barrier rectifying device |
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| CN2013203735797U CN203312299U (en) | 2013-06-26 | 2013-06-26 | Super barrier rectifying device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346155A (en) * | 2013-06-26 | 2013-10-09 | 张家港凯思半导体有限公司 | Superpotential barrier rectification device and manufacturing method thereof |
| CN105977308A (en) * | 2016-06-21 | 2016-09-28 | 中航（重庆）微电子有限公司 | Super barrier rectifier device and preparation method thereof |
| CN106098686A (en) * | 2016-07-11 | 2016-11-09 | 中航（重庆）微电子有限公司 | A kind of super barrier rectifier and preparation method thereof |
| CN107204336A (en) * | 2016-03-16 | 2017-09-26 | 重庆中科渝芯电子有限公司 | A kind of high efficiency rectifier and its manufacture method |
-
2013
- 2013-06-26 CN CN2013203735797U patent/CN203312299U/en not_active Withdrawn - After Issue
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346155A (en) * | 2013-06-26 | 2013-10-09 | 张家港凯思半导体有限公司 | Superpotential barrier rectification device and manufacturing method thereof |
| CN103346155B (en) * | 2013-06-26 | 2016-03-30 | 张家港凯思半导体有限公司 | A kind of Superpotential barrier rectification device and manufacture method thereof |
| CN107204336A (en) * | 2016-03-16 | 2017-09-26 | 重庆中科渝芯电子有限公司 | A kind of high efficiency rectifier and its manufacture method |
| CN107204336B (en) * | 2016-03-16 | 2023-10-20 | 重庆中科渝芯电子有限公司 | High-efficiency rectifier and manufacturing method thereof |
| CN105977308A (en) * | 2016-06-21 | 2016-09-28 | 中航（重庆）微电子有限公司 | Super barrier rectifier device and preparation method thereof |
| CN106098686A (en) * | 2016-07-11 | 2016-11-09 | 中航（重庆）微电子有限公司 | A kind of super barrier rectifier and preparation method thereof |
| CN106098686B (en) * | 2016-07-11 | 2019-05-21 | 华润微电子（重庆）有限公司 | A kind of super barrier rectifier and preparation method thereof |
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Granted publication date: 20131127 Effective date of abandoning: 20160330 |
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