CN203250308U - USB JTAG conversion debugging device internally embedded in chip - Google Patents
USB JTAG conversion debugging device internally embedded in chip Download PDFInfo
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- CN203250308U CN203250308U CN 201320229564 CN201320229564U CN203250308U CN 203250308 U CN203250308 U CN 203250308U CN 201320229564 CN201320229564 CN 201320229564 CN 201320229564 U CN201320229564 U CN 201320229564U CN 203250308 U CN203250308 U CN 203250308U
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Abstract
The utility model provides a USB JTAG conversion debugging device internally embedded in a chip. A circuit module is arranged in a multi-core chip, one end of the circuit module is connected with a coprocessor in the chip to be used as a control processor, and the other end of the circuit module is connected with a JTAG interface gathering module of debugging processors. Meanwhile, the control processor is connected with a USB receiving and emitting device, and converts commands sent by the USB receiving and emitting device into JTAG signals to debug all the processors through a control processing module. Therefore, a USB JTAG conversion debugging device body arranged between a peripheral PC terminal and a development board is eliminated in the debugging process, and meanwhile online synchronous debugging of a plurality of CPUs in the multi-core chip is supported through software. Development board cost is lowered, and debugging flexibility is improved.
Description
Technical field
The utility model relates to SOC integrated circuit (IC) design field, relates in particular to a kind of USB that is embedded in chip and turns the JTAG debugging apparatus.
Background technology
The interface of present all kinds of development board debugging usefulness is jtag interface, has all used the USB R-T unit and be connected to PC (Personal Computer, personal computer).Therefore must turn the JTAG debugger with USB connects main frame and development board, to finish connection and the debugging to master chip CPU in the development board.
Development along with multi-core technology, there is various types of other CPU(Central Processing Unit in the multinuclear integrated circuit, central processing unit), because the debug processor that different CPU uses all is that different manufacturers provides, function is all not identical with model, need to purchase the debugger that USB corresponding to debug processor separately turns JTAG when like this each different CPU being debugged, and PC needs USB corresponding to a plurality of USB R-T unit accesses to turn the debugger of JTAG, and chip also needs to provide a plurality of jtag interfaces to realize by the debugging of debug processor to different CPU.
Traditional Technology origin is in the structure of monokaryon integrated circuit, Fig. 1 is the structural representation of prior art chips debug process, as shown in Figure 1, debug processor 28 in needing control chip 20 is debugged when processing, need to there be debug processor 28 corresponding production firms to provide corresponding USB to turn JTAG debugger 30 extraneous peripheral PCs 10 and finish debugging work, then not only need a plurality of USB to turn the JTAG debugger, and need to reserve a plurality of USB R-T units and jtag interface for its debugging work.Therefore, the multinuclear integrated circuit has been difficult to be difficult to especially be developed the plate user and accept for the user accepts.
The utility model content
The purpose of this utility model is to provide a kind of USB that is embedded in chip to turn the JTAG debugging apparatus.
For solving the problems of the technologies described above, the utility model provides a kind of USB that is embedded in chip to turn the JTAG debugging apparatus, comprising: USB R-T unit, control processor, jtag interface summarizing module and some debug processor,
Described USB R-T unit receives the call instruction of described peripheral PC output;
Described control processor receives described call instruction, and described call instruction is transferred to described jtag interface summarizing module is configured;
Described jtag interface summarizing module receives the call instruction of described control processor transmission, and the different extremely corresponding debug processor of JTAG sequential instruction of conversion output;
Described debug processor receives the instruction of corresponding described JTAG sequential and debugs, and exports debug results to described peripheral PC with this through described jtag interface summarizing module, control processor and USB R-T unit feedback.
Further, described control processor comprises some I/O ports, and described control processor receives the call instruction of described USB R-T unit transmission by described I/O port, and exports the control command of jtag interface by described I/O port.
Further, described control processor comprises the control processing module, described control processing module receives, sends the discernible data transmission bag of USB R-T unit, described control processing module is resolved the data transmission bag with order and parameter information that described peripheral PC sends over, and described debug processor feeds back to peripheral PC with debug results with the form of data transmission bag.
Further, described control processor is that described chip carries a coprocessor in the multi-core central processing unit.
Further, described USB R-T unit adopts the USB R-T unit that described chip carries.
Further, described jtag interface summarizing module also comprises the JTAG pin, and described JTAG pin is drawn by described chip pin.
In sum, the USB that is embedded in chip described in the utility model turns the JTAG debugging apparatus and passes through at circuit module of multi core chip indoor design, one of this circuit module connects in the chip coprocessor as control processor, an other jtag interface summarizing module that connects each debug processor.Control processor connects the USB R-T unit simultaneously, and the mode by software control will change into from the order that the USB R-T unit is come the JTAG signal each processor is debugged.Therefore, the USB when having saved debugging between peripheral PC end and development board turns the JTAG debugger, simultaneously can be by the on-line synchronous debugging of a plurality of CPU in the software support multi core chip.Lower the development board cost, improved the debugging dirigibility.
Simultaneously, USB R-T unit example in chip turns to device (Device) pattern, every road JTAG control signal is used in the USB R-T unit independently endpoint number, can see a plurality of debug processor at peripheral PC end like this, thereby realize that a USB line realization is to the debugging of all processors in the multi core chip.
End points number in the USB R-T unit then can be selected the processor of needs debugging by the mode of software configuration less than the processor number of needs debugging, and the processor JTAG control ability that needs are debugged is tied on the corresponding end points of USB.
In addition, in order to improve dirigibility, described jtag interface summarizing module also comprises the JTAG pin, and described JTAG pin is drawn by described chip pin, be drawn out to simultaneously on the chip pin by the JTAG pin with processor, circumscribed USB turns the JTAG debugger and debugs in the conventional mode.Provide selectable toggle switch or software control at chip.
Description of drawings
Fig. 1 is the structural representation of prior art chips debug process;
Fig. 2 is that the USB that is embedded in chip among the utility model one embodiment turns the JTAG debugging apparatus.
Embodiment
For making content of the present utility model more clear understandable, below in conjunction with Figure of description, content of the present utility model is described further.Certainly the utility model is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in the protection domain of the present utility model.
Secondly, the utility model utilizes schematic diagram to carry out detailed statement, and when the utility model example was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as to restriction of the present utility model.
The utility model is by relying on the resource of multi core chip, a built-in USB turns the JTAG debugger, be used for finishing the debugging to other central processing units (CPU), the alternative circumscribed USB of device after finishing turns the debugger of JTAG, change into by chip USB R-T unit and directly linking to each other with debug host, and then reduce the cost of the development board that this class multi core chip produces.
Fig. 2 is that the USB that is embedded in chip among the utility model one embodiment turns the JTAG debugging apparatus.As shown in Figure 2, in conjunction with above-mentioned thought, the utility model provides a kind of USB that is embedded in chip to turn the JTAG debugging apparatus, comprise, USB R-T unit 202, control processor 204, jtag interface summarizing module 206 and some debug processor 208, wherein said control processor 204 provides call instruction according to receiving peripheral PC 100 by USB R-T unit 202, and control the different JTAG sequential instruction of described jtag interface summarizing module 206 conversion outputs to corresponding debug processor 208, the debug results of described debug processor 208 is through described jtag interface summarizing module 206, control processor 204 and USB R-T unit 202 feedbacks export described peripheral PC 100 to, to finish debug process.
Further, described USB R-T unit 202 receives the call instruction of described peripheral PC 100 outputs, and is transferred to described control processor 202; Described control processor 202 is configured described jtag interface summarizing module 206 according to call instruction; Described jtag interface summarizing module 206 is according to the extremely corresponding debug processor 208 of configuration output JTAG sequential of described control processor 204.
Further, 204 pairs of described jtag interface summarizing module 206 of described control processor are configured process and comprise: debug processor 208 numberings that selection is set; The data that need read/write are set; The JTAG clock frequency is set; And when read-write can signal.
Further, described control processor 204 comprises some I/O ports, and described control processor 204 receives the call instruction of described USB R-T unit 202 transmission by described I/O port, and exports the control command of jtag interface by described I/O port.
Further, described control processor 204 carries the control processing module, described control processing module is by receiving, sending USB R-T unit 202 discernible data transmission bags realizes with peripheral PC mutual, described control processing module 204 is resolved the data transmission bag with order and parameter information that peripheral PC 100 sends over, and adopt programme controlled mode to control jtag interface summarizing module 206 and finish debug process to debug processor, the debug results that gets access to from debug processor the most at last, form with the data transmission bag feeds back to peripheral PC 100 again, to finish the process of whole debugging.
In preferred embodiment, described control processor 204 is that described chip 200 carries a coprocessor in the multi-core central processing unit.Described USB R-T unit 202 is described chip 100 self-carried USB Device/OTG controllers.Described control processor 204 is a coprocessor in the multi-core CPU in the described chip 200; Described USB R-T unit 202 is USB Device/OTG controller in the described chip 200.As control processor 204, use the USB Device/OTG controller of multinuclear in the chip 200 as USB R-T unit 202 by a coprocessor in the multi-core CPU in the use chip 200.
The USB that is embedded in chip described in the utility model turns the JTAG debugging apparatus jtag interface of other debug processor that need to debug in the multi core chip is connected on the control processor by the jtag interface summarizing module, and the mode that is combined with software is supported the debug function of control processor and jtag interface summarizing module.When normal operation, be connected in the chip USB Device/OTG controller as the USB R-T unit by the USB Host of peripheral PC, control processor receives the debug command that peripheral PC sends by the mode of software control from the USB R-T unit, return in the jtag interface summarizing module kind and the version of the CPU that supports that several JTAG debug port and each JTAG debug port connect, will call corresponding driving and debugging acid behind the kind that recognizes debugging CPU when peripheral PC and the version and set up with corresponding USB R-T unit and communicate by letter.
Control processor is accepted the control command that peripheral PC sends to the call instruction of corresponding USB R-T unit and converts thereof into corresponding jtag port, I/O mouth by control processor sends to the JTAG interconnecting module, the debug results of simultaneously JTAG being returned is read back by the I/O mouth of control processor, converts the USB transmission package to and returns to PC.So just finished the debugging of PC debugged program to processor in the chip.
Further, the debug command of described peripheral PC comprise reset, obtain state, read debug processor information, breakpoint is set, read-write debug processor and read-write debug processor content.
In addition, in order to improve dirigibility, described jtag interface summarizing module also comprises the JTAG pin, and described JTAG pin is drawn by described chip pin, be drawn out to simultaneously on the chip pin by the JTAG pin with processor, circumscribed USB turns the JTAG debugger and debugs in the conventional mode.Provide selectable toggle switch or software control at chip.
The USB that is embedded in chip described in the utility model turns the debug process of JTAG debugging apparatus, comprising:
Peripheral PC sends debug command;
Described USB R-T unit receives described debug command, and passes to described control processor;
Described control processor is converted to the call instruction of described USB R-T unit transmission control command and the output of jtag interface;
Described jtag interface summarizing module receives the control command of described jtag interface, and is converted into JTAG sequential instruction output;
Described debug processor receives the instruction of described JTAG sequential, and to resolve the instruction of described JTAG sequential be corresponding debug signal, debugs;
The debug results of described debug processor exports described peripheral PC to through described jtag interface summarizing module, control processor and USB R-T unit feedback, to finish debug process.
Peripheral PC is by sending call instruction to debug processor, the retaking of a year or grade data are finished the debugging to debug processor, wherein call instruction is a cover command set, comprise and resetting, obtain state, read debug processor information, breakpoint is set, read-write debug processor register, read-write debug processor internal memory etc.Although order morely, the workflow of these orders is identical for debugging apparatus.
Below, the debug process that the USB that is embedded in chip turns the JTAG debugging apparatus is described to obtain state as example:
1) peripheral PC sends the call instruction Get_Status, parameter of the state that obtains and which debug processor the information such as is debugged to the USB R-T unit.Data transmission bag (BULK) transmission that this call instruction is packaged on the USB R-T unit sends.
2) the data transmission bag passes to the USB R-T unit of chip by the USB cable, is received by the USB R-T unit that carries as chip, and particularly, the USB Device/OTG controller that chip carries can be finished the reception task.
3) receive described data transmission bag after, described USB Device/OTG controller sends a look-at-me to described control processor.
4) have no progeny during control processor receives, calling corresponding interruption processing function processes the data transmission bag that receives, content in the resolution data transmission package is analyzed and out to be order and the relevant parameter of Get_Status and to send to the information such as which debug processor.
5) for call instruction and the parameter of Get_Status, described control processor calls in the corresponding control processing module corresponding program the jtag interface summarizing module is controlled.By opening the debug processor jtag port of response, and the call instruction of Get_Status and parameter be converted into JTAG sequential instruction output, and send to the jtag interface summarizing module by the mode of writing register, by the jtag interface summarizing module these information are converted to the JTAG sequential thereafter.
6) after debug processor receives the instruction of JTAG sequential, can resolve the instruction of JTAG sequential, with Get_Status order and parameter identification wherein, call corresponding processing unit and obtain the processor state information that it needs, and convert these status informations to the JTAG sequential and return to the jtag interface summarizing module.
7) the jtag interface summarizing module status information that can receive passback is kept at the FIFO(First Input First Output of its inside modules, First Input First Output) in, transmission interrupt notification control processor after status information finishes receiving.
8) have no progeny during control processor receives and read the status information of passback, wait for the BULK In bag that PC sends over, the DATA zone that the status information that returns is put into BULK In bag feeds back to peripheral PC.
9) just can parse the state of debug processor after the status information that PC obtains feeding back, upgrade the state of debugged program according to state.
Whole like this debug process just is through with.The debug process of other call instruction is identical with above-mentioned flow process.Just the process software of its order need to be finished according to the requirement of reality.
The USB that is embedded in chip described in the utility model turns the JTAG debugging apparatus and passes through at circuit module of multi core chip indoor design, one of this circuit module connects in the chip coprocessor as control processor, an other jtag interface summarizing module that connects each debug processor.Control processor connects the USB R-T unit simultaneously, and the mode by software control will change into from the order that the USB R-T unit is come the JTAG signal each processor is debugged.Therefore, the USB when having saved debugging between peripheral PC end and development board turns the JTAG debugger, simultaneously can be by the on-line synchronous debugging of a plurality of CPU in the software support multi core chip.Lower the development board cost, improved the debugging dirigibility.
Simultaneously, USB R-T unit example in chip turns to device (Device) pattern, every road JTAG control signal is used in the USB R-T unit independently endpoint number, can see a plurality of debug processor at peripheral PC end like this, thereby realize that a USB line realization is to the debugging of all processors in the multi core chip.
End points number in the USB R-T unit then can be selected the processor of needs debugging by the mode of software configuration less than the processor number of needs debugging, and the processor JTAG control ability that needs are debugged is tied on the corresponding end points of USB.
In addition, in order to improve dirigibility, described jtag interface summarizing module also comprises the JTAG pin, and described JTAG pin is drawn by described chip pin, be drawn out to simultaneously on the chip pin by the JTAG pin with processor, circumscribed USB turns the JTAG debugger and debugs in the conventional mode.Provide selectable toggle switch or software control at chip.
Foregoing description only is the description to the utility model preferred embodiment; it is not any restriction to the utility model scope; any change, modification that the those of ordinary skill in the utility model field is done according to above-mentioned disclosure all belong to the protection domain of claims.
Claims (6)
1. a USB who is embedded in chip turns the JTAG debugging apparatus, comprising: USB R-T unit, control processor, jtag interface summarizing module and some debug processor,
Described USB R-T unit receives the call instruction of described peripheral PC output;
Described control processor receives described call instruction, and described call instruction is transferred to described jtag interface summarizing module is configured;
Described jtag interface summarizing module receives the call instruction of described control processor transmission, and the different extremely corresponding debug processor of JTAG sequential instruction of conversion output;
Described debug processor receives the instruction of corresponding described JTAG sequential and debugs, and exports debug results to described peripheral PC with this through described jtag interface summarizing module, control processor and USB R-T unit feedback.
2. the USB that is embedded in chip as claimed in claim 1 turns the JTAG debugging apparatus, it is characterized in that, described control processor comprises some I/O ports, described control processor receives the call instruction of described USB R-T unit transmission by described I/O port, and exports the control command of jtag interface by described I/O port.
3. the USB that is embedded in chip as claimed in claim 1 turns the JTAG debugging apparatus, it is characterized in that, described control processor comprises the control processing module, described control processing module receives, sends the discernible data transmission bag of USB R-T unit, described control processing module is resolved the data transmission bag with order and parameter information that described peripheral PC sends over, and described debug processor feeds back to peripheral PC with debug results with the form of data transmission bag.
4. the USB that is embedded in chip as claimed in claim 1 turns the JTAG debugging apparatus, it is characterized in that, described control processor is that described chip carries a coprocessor in the multi-core central processing unit.
5. the USB that is embedded in chip as claimed in claim 1 turns the JTAG debugging apparatus, it is characterized in that, the USB R-T unit that described USB R-T unit adopts described chip to carry.
6. turn the JTAG debugging apparatus such as the described USB that is embedded in chip of any one in the claim 1 to 5, it is characterized in that, described jtag interface summarizing module also comprises the JTAG pin, and described JTAG pin is drawn by described chip pin.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320229564 CN203250308U (en) | 2013-04-28 | 2013-04-28 | USB JTAG conversion debugging device internally embedded in chip |
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| CN 201320229564 CN203250308U (en) | 2013-04-28 | 2013-04-28 | USB JTAG conversion debugging device internally embedded in chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226506A (en) * | 2013-04-28 | 2013-07-31 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| CN104239176A (en) * | 2014-10-16 | 2014-12-24 | 成都傅立叶电子科技有限公司 | Multi-user multi-target remote JTAG debugging system based on Internet |
| CN107145464A (en) * | 2017-05-25 | 2017-09-08 | 郑州云海信息技术有限公司 | A kind of Multi-serial port adjustment method, apparatus and system |
| CN108107351A (en) * | 2017-12-06 | 2018-06-01 | 西安智多晶微电子有限公司 | Adjustment method, debugger and the system of JTAG debuggers |
| CN109977042A (en) * | 2019-02-28 | 2019-07-05 | 珠海海奇半导体有限公司 | A kind of USB on-line debugging system and method |
-
2013
- 2013-04-28 CN CN 201320229564 patent/CN203250308U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226506A (en) * | 2013-04-28 | 2013-07-31 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| CN104239176A (en) * | 2014-10-16 | 2014-12-24 | 成都傅立叶电子科技有限公司 | Multi-user multi-target remote JTAG debugging system based on Internet |
| CN107145464A (en) * | 2017-05-25 | 2017-09-08 | 郑州云海信息技术有限公司 | A kind of Multi-serial port adjustment method, apparatus and system |
| CN108107351A (en) * | 2017-12-06 | 2018-06-01 | 西安智多晶微电子有限公司 | Adjustment method, debugger and the system of JTAG debuggers |
| CN109977042A (en) * | 2019-02-28 | 2019-07-05 | 珠海海奇半导体有限公司 | A kind of USB on-line debugging system and method |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131023 Termination date: 20190428 |