CN203118416U - Shifting register and display device - Google Patents
Shifting register and display device Download PDFInfo
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- CN203118416U CN203118416U CN 201320090139 CN201320090139U CN203118416U CN 203118416 U CN203118416 U CN 203118416U CN 201320090139 CN201320090139 CN 201320090139 CN 201320090139 U CN201320090139 U CN 201320090139U CN 203118416 U CN203118416 U CN 203118416U
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Abstract
The utility model discloses a shifting register and a display device. The shifting register comprises an input module, a pull-down module, an opposite-phase module and a first pull-up module. The input module is in response to a first clock signal so as to supply the voltage of an input signal to a pull-down node, wherein the pull-down node is served as the output node of the input module. The pull-down module is used for storing the voltage of the input signal and then supplying a second clock signal to an output terminal in response to the pull-down node. The opposite-phase module is in response to the pull-down node to supply the voltage of the positive or negative electrode of a power supply to a first pull-up node. The first pull-up module is in response to the first pull-up node to supply the voltage of the positive electrode of the power supply to the output terminal. According to the technical scheme of the utility model, one part or all of the dangling nodes of the shifting register are improved to be not dangled any more. Or, the source and drain electrodes of a thin-film transistor, which are influenced by the dangling nodes of the shifting register, are controlled to improve the output stability of the shifting register.
Description
Technical field
The utility model relates to liquid crystal display Driving technique field, relates in particular to a kind of shift register and display device.
Background technology
Flat-panel monitor is because of its ultra-thin energy-conservation being widelyd popularize.To use shift register in most flat pannel display, by gate drive apparatus being integrated in liquid crystal panel (gate on array, GOA) shift register of method realization, namely can save the grid drive IC, can also reduce production process one, therefore not only reduce the cost of manufacture of flat-panel monitor, also shortened fabrication cycle to a certain extent.So the GOA technology was widely used in the flat pannel display manufacturing in recent years.The output stability of GOA is the problem of relatively paying close attention in the GOA design always.
The utility model content
The purpose of this utility model provides a kind of shift register and display device, and this shift register improves the unsettled node in the operational process, solves shift register output problem of unstable.
The purpose of this utility model is achieved through the following technical solutions:
The utility model embodiment provides a kind of shift register, and this shift register comprises: drawing-die piece on load module, drop-down module, the anti-phase module and first; Wherein,
Described load module in response to first clock signal, offers pull-down node with applied signal voltage, and wherein pull-down node is the output node of described load module;
Described drop-down module is stored described applied signal voltage and in response to the output voltage of described pull-down node the second clock signal is offered lead-out terminal;
Described anti-phase module in response to the output voltage of described pull-down node, offers positive source voltage or power cathode voltage and draws node on first;
Drawing-die piece on described first draws the output voltage of node that described positive source voltage is offered described lead-out terminal on described first.
Preferably, described load module comprises:
The first film transistor, its grid connects first clock signal terminal, and source electrode connects the input signal end, and drain electrode is as the described output node of described load module, i.e. described pull-down node.
Preferably, described drop-down module comprises:
Second thin film transistor (TFT), its grid connects described pull-down node, and source electrode connects the second clock signal end, and drain electrode connects described lead-out terminal;
Electric capacity is connected between the drain electrode of described pull-down node and described second thin film transistor (TFT).
Preferably, described anti-phase module comprises:
The 3rd thin film transistor (TFT), its grid connects described pull-down node, and source electrode connects the positive source voltage end, and drain electrode connects on described first draws node;
The 4th thin film transistor (TFT), its grid is connected the power cathode voltage end with drain electrode, and source electrode connects on described first and draws node.
Preferably, drawing-die piece on described first comprises:
The 5th thin film transistor (TFT), its grid connect on described first and draw node, and source electrode connects the positive source voltage end, and drain electrode connects described lead-out terminal.
Preferably, also comprise drawing-die piece on second, output voltage and described input signal in response to described pull-down node offer described lead-out terminal with described positive source voltage.
Preferably, drawing-die piece on described second comprises:
The 6th thin film transistor (TFT), its grid connects described pull-down node, and source electrode connects the input signal end, and drain electrode connects on second draws node;
The 7th thin film transistor (TFT), its grid connect on described second and draw node, and source electrode connects the positive source voltage end, and drain electrode connects described lead-out terminal.
The utility model embodiment provides a kind of display device, comprise cascade as above-mentioned shift register.
The utility model embodiment beneficial effect is as follows: this shift register improvement part or whole unsettled node make it no longer unsettled; Perhaps, the source-drain electrode of the thin film transistor (TFT) that unsettled node is influenced is controlled; Thereby improved the stability of shift register output.
Description of drawings
Fig. 1 is the structural representation of prior art elementary cell shift register;
Fig. 2 is the structural representation of the utility model embodiment one described shift register;
Fig. 3 is the described control signals of shift registers sequential chart of the utility model embodiment;
Fig. 4 is the structural representation of the utility model embodiment two described shift registers;
Fig. 5 is the structural representation of the cascade shift register of the utility model embodiment three described display device;
Fig. 6 is the utility model embodiment three described cascade control signals of shift registers sequential charts.
Accompanying drawing 2 description of reference numerals to the accompanying drawing 4 is as follows:
101, load module 101; M29 the first film transistor;
102, drop-down module 102; M28 second thin film transistor (TFT);
103, anti-phase module 103; M24 the 3rd thin film transistor (TFT);
104, drawing-die piece 104 on first; M26 the 4th thin film transistor (TFT);
105, drawing-die piece 105 on second; M27 the 5th thin film transistor (TFT);
M25 the 6th thin film transistor (TFT); M30 the 7th thin film transistor (TFT).
Embodiment
Be elaborated below in conjunction with the implementation procedure of Figure of description to the utility model embodiment.
The utility model embodiment one provides a kind of shift register, and as shown in Figure 2, this shift register comprises: drawing-die piece 104 on load module 101, drop-down module 102, the anti-phase module 103 and first; Wherein,
Drop-down module 102, storage input signal STV and the output voltage of ordering in response to pull-down node B, CLKB offers lead-out terminal OUTPUT with the second clock signal;
Drawing-die piece 104 on first, in response to the output voltage that draws node A to order on first, VGH offers lead-out terminal OUTPUT with positive source voltage.
Preferably, load module 101 comprises:
The first film transistor M29, its grid connect the first clock signal clk end, and source electrode connects input signal STV end, and drain electrode is as the output node of load module 101, i.e. pull-down node B point.
Preferably, drop-down module 102 comprises:
The second thin film transistor (TFT) M28, its grid connect pull-down node B point, and source electrode connects second clock signal CLKB end, and drain electrode connects lead-out terminal OUTPUT;
Preferably, anti-phase module 103 comprises:
The 3rd thin film transistor (TFT) M24, its grid connect pull-down node B point, and source electrode connects positive source voltage end VGH, and drain electrode connects on first draws node A point;
The 4th thin film transistor (TFT) M26, its grid are connected power cathode voltage VGL end with drain electrode, draw node A point in the source electrode connection first.
Preferably, drawing-die piece 104 on first comprises:
The 5th thin film transistor (TFT) M27 draws node A point in its grid connection first, and source electrode connects positive source voltage VGH end, and drain electrode connects lead-out terminal OUTPUT.
With reference to control sequential chart shown in Figure 3, the driving method of the shift register that the utility model embodiment one provides is as follows, comprising:
Phase one t1, first clock signal clk are low level, second clock signal CLKB high level, and input signal STV is low level.Because first clock signal clk is low level, the first film transistor M29 conducting is input to pull-down node B point with the low level signal of input signal STV, and the low level that pull-down node B is ordered makes the second thin film transistor (TFT) M28 and the 3rd thin film transistor (TFT) M24 conducting; The 3rd thin film transistor (TFT) M24 of conducting outputs to the high level of positive source voltage VGH and draws node A on first, draws the high level of node A to make the 5th thin film transistor (TFT) M27 close on first; The second thin film transistor (TFT) M28 of conducting outputs to the high level signal of second clock signal CLKB the lead-out terminal OUTPUT of shift register.
Subordinate phase t2, first clock signal clk are high level, and second clock signal CLKB is low level, and input signal STV is high level; The low level that pull-down node B is ordered keeps by capacitor C 2, and makes the second thin film transistor (TFT) M28 conducting; The second thin film transistor (TFT) M28 of conducting outputs to lead-out terminal OUTPUT with the low level of second clock signal CLKB, plays the current potential pulldown function that pull-down node B is ordered simultaneously.
The low level that this moment, pull-down node B was ordered, make the 3rd thin film transistor (TFT) M24 be in conducting state, and with positive source voltage VGH output first on draw node A, make the 5th thin film transistor (TFT) M27 turn-off, guaranteed that lead-out terminal OUTPUT receives the stabilization signal of the second thin film transistor (TFT) M28.
Three phases t3, first clock signal clk are low level, and second clock signal CLKB is high level, and input signal STV is high level; Because first clock signal clk is low level, the first film transistor M29 conducting, the first film transistor M29 of conducting outputs to pull-down node B point with the high level of input signal STV, and pull-down node B point high level turn-offs the second thin film transistor (TFT) M28 and the 3rd thin film transistor (TFT) M24.The 4th thin film transistor (TFT) M26 receives the low level of power supply low-voltage signal VGL and outputs to and draws node A point on first, make the 5th thin film transistor (TFT) M27 conducting, the 5th thin film transistor (TFT) M27 of conducting outputs to lead-out terminal OUTPUT with the high level of power supply high-voltage signal VGH.
Quadravalence section t4, first clock signal clk are high level, and second clock signal CLKB is low level, and input signal STV is high level; Pull-down node B point still keeps the high level of phase III t3 by capacitor C 2, makes the second thin film transistor (TFT) M28 and the 3rd thin film transistor (TFT) M24 be in off state.Second clock signal CLKB low level can't output to lead-out terminal OUTPUT by the second thin film transistor (TFT) M28, thereby can not influence the stability of output signal.
Meanwhile, the 4th thin film transistor (TFT) M26 receives the low level of power supply low-voltage signal VGL and outputs to and draws node A point on first, make the 5th thin film transistor (TFT) M27 conducting, the 5th thin film transistor (TFT) M27 of conducting outputs to lead-out terminal OUTPUT with the high level of power supply high-voltage signal VGH.
Five-stage t5, first clock signal clk are low level, and second clock signal CLKB is high level, and input signal STV is high level; Identical with the phase III situation.
Later on each stage will repeat phase III and quadravalence section, and export high level always, up to the low level that receives input signal STV again, and export according to the low level sequential at that time that receives input signal STV.
The utility model embodiment beneficial effect is as follows: this shift register improvement part or whole unsettled node make it no longer unsettled; Perhaps, the source-drain electrode of the thin film transistor (TFT) that unsettled node is influenced is controlled; Thereby improved the stability of shift register output.
The utility model embodiment two provides a kind of shift register, and as shown in Figure 4, this shift register comprises: drawing-die piece 105 on the drawing-die piece 104 and second on load module 101, drop-down module 102, the anti-phase module 103, first; Wherein,
Drop-down module 102, storage input signal STV and the output voltage of ordering in response to pull-down node B, CLKB offers lead-out terminal OUTPUT with the second clock signal;
Drawing-die piece 104 on first, in response to the output voltage that draws node A to order on first, VGH offers lead-out terminal OUTPUT with positive source voltage;
Drawing-die piece 105 on second, in response to output voltage and input signal STV that pull-down node B is ordered, VGH offers lead-out terminal OUTPUT with positive source voltage.
Preferably, load module 101 comprises:
The first film transistor M29, its grid connects first clock signal clk, and source electrode connects input signal STV end, and drain electrode is as the output node of load module 101, i.e. pull-down node B point.
Preferably, drop-down module 102 comprises:
The second thin film transistor (TFT) M28, its grid connect pull-down node B point, and source electrode connects second clock signal CLKB end, and drain electrode connects lead-out terminal OUTPUT;
Preferably, anti-phase module 103 comprises:
The 3rd thin film transistor (TFT) M24, its grid connect pull-down node B point, and source electrode connects positive source voltage end VGH, and drain electrode connects on first draws node A point;
The 4th thin film transistor (TFT) M26, its grid are connected power cathode voltage VGL end with drain electrode, draw node A point in the source electrode connection first.
Preferably, drawing-die piece 104 on first comprises:
The 5th thin film transistor (TFT) M27 draws node A point in its grid connection first, and source electrode connects positive source voltage VGH end, and drain electrode connects lead-out terminal OUTPUT.
Preferably, drawing-die piece 105 on second comprises:
The 6th thin film transistor (TFT) M25, its grid connect pull-down node B point, and source electrode connects input signal STV end, and drain electrode connects on second draws node C point;
The 7th thin film transistor (TFT) M30 draws node C point in its grid connection second, and source electrode connects positive source voltage VGH end, and drain electrode connects lead-out terminal OUTPUT.
With reference to control sequential chart shown in Figure 3, the driving method of the shift register that the utility model embodiment two provides is as follows, comprising:
Phase one t1, first clock signal clk are low level, second clock signal CLKB high level, and input signal STV is low level.Because first clock signal clk is low level, the first film transistor M29 conducting is input to pull-down node B point with the low level signal of input signal STV, and the low level that pull-down node B is ordered makes the second thin film transistor (TFT) M28 and the 3rd thin film transistor (TFT) M24 conducting; The 3rd thin film transistor (TFT) M24 of conducting outputs to the high level of positive source voltage VGH and draws node A on first, draws the high level of node A to make the 5th thin film transistor (TFT) M27 turn-off on first; The second thin film transistor (TFT) M28 of conducting outputs to the high level signal of second clock signal CLKB the lead-out terminal OUTPUT of shift register.
Simultaneously, the low level that pull-down node B is ordered makes the 6th thin film transistor (TFT) M25 conducting, the 6th thin film transistor (TFT) M25 of conducting outputs to the low level of input signal STV and draws node C point on second, the low level of drawing node C to order on second makes the 7th thin film transistor (TFT) M30 conducting, the 7th thin film transistor (TFT) M30 of conducting outputs to lead-out terminal OUTPUT with the high level of positive source voltage VGH, guarantees output end signal stability.
Subordinate phase t2, first clock signal clk are high level, and second clock signal CLKB is low level, and input signal STV is high level; The low level that pull-down node B is ordered keeps by capacitor C 2, and makes the second thin film transistor (TFT) M28 conducting; The second thin film transistor (TFT) M28 of conducting outputs to lead-out terminal OUTPUT with the low level of second clock signal CLKB, plays the current potential pulldown function that pull-down node B is ordered simultaneously.
The low level that this moment, pull-down node B was ordered, make the 3rd thin film transistor (TFT) M24 be in conducting state, and positive source voltage VGH outputed to draw node A point on first, make the 5th thin film transistor (TFT) M27 turn-off, guaranteed that lead-out terminal OUTPUT receives the stabilization signal of the second thin film transistor (TFT) M28.
Simultaneously, the low level that pull-down node B is ordered makes the 6th thin film transistor (TFT) M25 conducting, the 6th thin film transistor (TFT) M25 of conducting outputs to the high level of input signal STV and draws node C point on second, the high level that draws node C to order on second makes the 7th thin film transistor (TFT) M30 turn-off, and can not influence the operate as normal of shift register.
Three phases t3, first clock signal clk are low level, and second clock signal CLKB is high level, and input signal STV is high level; Because first clock signal clk is low level, the first film transistor M29 conducting, the first film transistor M29 of conducting outputs to pull-down node B point with the high level of input signal STV, and pull-down node B point high level turn-offs the second thin film transistor (TFT) M28, the 3rd thin film transistor (TFT) M24 and the 6th thin film transistor (TFT) M25.The 4th thin film transistor (TFT) M26 receives the low level of power supply low-voltage signal VGL and outputs to and draws node A point on first, make the 5th thin film transistor (TFT) M27 conducting, the 5th thin film transistor (TFT) M27 of conducting outputs to lead-out terminal OUTPUT with the high level of power supply high-voltage signal VGH.
It should be noted that, because the 6th thin film transistor (TFT) M25 turn-offs, draw node C point to be in vacant state on second, but owing to draw the source-drain electrode signal of the 7th thin film transistor (TFT) M30 of node C point control to be high level on second, therefore do not influence the operation of shift register, can not influence the output signal of lead-out terminal OUTPUT yet.
Quadravalence section t4, first clock signal clk are high level, and second clock signal CLKB is low level, and input signal STV is high level; Pull-down node B still keeps the high level of phase III t3 by capacitor C 2, makes the second thin film transistor (TFT) M28, the 3rd thin film transistor (TFT) M24 and the 6th thin film transistor (TFT) M25 turn-off.Second clock signal CLKB low level can't output to lead-out terminal OUTPUT by the second thin film transistor (TFT) M28, thereby can not influence the stability of output signal.
Meanwhile, the 4th thin film transistor (TFT) M26 receives the low level of power supply low-voltage signal VGL and outputs to and draws node A point on first, make the 5th thin film transistor (TFT) M27 conducting, the 5th thin film transistor (TFT) M27 of conducting outputs to lead-out terminal OUTPUT with the high level of power supply high-voltage signal VGH.
The source-drain electrode signal of the 7th thin film transistor (TFT) M30 is high level, does not therefore influence the operation of shift register, also can not influence the output signal of lead-out terminal OUTPUT.
Five-stage t5, first clock signal clk are low level, and second clock signal CLKB is high level, and input signal STV is high level; Identical with the phase III situation.
Later on each stage will repeat phase III and quadravalence section, and export high level always, up to the low level that receives input signal STV again, and export according to the low level sequential at that time that receives input signal STV.
The utility model embodiment beneficial effect is as follows: this shift register improvement part or whole unsettled node make it no longer unsettled; Perhaps, the source-drain electrode of the thin film transistor (TFT) that unsettled node is influenced is controlled; Thereby improved the stability of shift register output.
Need to prove that it is that example describes that the above embodiment of the utility model is applied to the simple scanning structure with shift register.Wherein, all thin film transistor (TFT) TFT are P type TFT, and all TFT conducting when low level, disconnect during high level.But, the technical solution of the utility model can be applied to thin film transistor (TFT) TFT and be in N-type TFT or the shift register for N-type and P type Mixed Design, when being N-type TFT, only needing will be reverse as the high electronegative potential of each signal of Fig. 2 or shift register structure shown in Figure 4, and positive source voltage VGH and power cathode voltage VGL location swap can be realized; The principle of the shift register of N-type and P type Mixed Design is similar with it, no longer is repeated in this description at this.
The utility model embodiment provides a kind of display device, comprise cascade as above-mentioned shift register, the cascade shift register as shown in Figure 5, comprise n cascade as embodiment one or embodiment two described shift registers (having shown a part at this); For each shift register all provides first clock signal clk, second clock signal CLKB, positive source voltage VGH and power cathode voltage VGL; The lead-out terminal OUTPUT of previous stage shift register is connected with the input signal STV end of back one-level shift register simultaneously.
The sequential of cascade shift register (only illustrates the sequential chart of part cascade shift register) as shown in Figure 6, and in t1 to the t6 stage, back one-level is moved the output signal sequential that the output signal sequential of register is moved register than previous stage, and low level postpones backward.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (8)
1. a shift register is characterized in that, this shift register comprises: drawing-die piece on load module, drop-down module, the anti-phase module and first; Wherein,
Described load module in response to first clock signal, offers pull-down node with applied signal voltage, and wherein pull-down node is the output node of described load module;
Described drop-down module is stored described applied signal voltage and in response to the output voltage of described pull-down node the second clock signal is offered lead-out terminal;
Described anti-phase module in response to the output voltage of described pull-down node, offers positive source voltage or power cathode voltage and draws node on first;
Drawing-die piece on described first draws the output voltage of node that described positive source voltage is offered described lead-out terminal on described first.
2. shift register as claimed in claim 1 is characterized in that, described load module comprises:
The first film transistor, its grid connects first clock signal terminal, and source electrode connects the input signal end, and drain electrode is as the described output node of described load module, i.e. described pull-down node.
3. shift register as claimed in claim 1 is characterized in that, described drop-down module comprises:
Second thin film transistor (TFT), its grid connects described pull-down node, and source electrode connects the second clock signal end, and drain electrode connects described lead-out terminal;
Electric capacity is connected between the drain electrode of described pull-down node and described second thin film transistor (TFT).
4. shift register as claimed in claim 1 is characterized in that, described anti-phase module comprises:
The 3rd thin film transistor (TFT), its grid connects described pull-down node, and source electrode connects the positive source voltage end, and drain electrode connects on described first draws node;
The 4th thin film transistor (TFT), its grid is connected the power cathode voltage end with drain electrode, and source electrode connects on described first and draws node.
5. shift register as claimed in claim 1 is characterized in that, drawing-die piece on described first comprises:
The 5th thin film transistor (TFT), its grid connect on described first and draw node, and source electrode connects the positive source voltage end, and drain electrode connects described lead-out terminal.
6. as each described shift register of claim 1 to 5, it is characterized in that, also comprise drawing-die piece on second, output voltage and described input signal in response to described pull-down node offer described lead-out terminal with described positive source voltage.
7. shift register as claimed in claim 6 is characterized in that, drawing-die piece on described second comprises:
The 6th thin film transistor (TFT), its grid connects described pull-down node, and source electrode connects the input signal end, and drain electrode connects on second draws node;
The 7th thin film transistor (TFT), its grid connect on described second and draw node, and source electrode connects the positive source voltage end, and drain electrode connects described lead-out terminal.
8. a display device is characterized in that, comprise cascade as the described shift register of the arbitrary claim of claim 1 ~ 7.
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|---|---|---|---|
| CN 201320090139 CN203118416U (en) | 2013-02-27 | 2013-02-27 | Shifting register and display device |
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| CN 201320090139 CN203118416U (en) | 2013-02-27 | 2013-02-27 | Shifting register and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151010A (en) * | 2013-02-27 | 2013-06-12 | 京东方科技集团股份有限公司 | Shift register and display device |
| CN104332137A (en) * | 2014-11-28 | 2015-02-04 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
-
2013
- 2013-02-27 CN CN 201320090139 patent/CN203118416U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151010A (en) * | 2013-02-27 | 2013-06-12 | 京东方科技集团股份有限公司 | Shift register and display device |
| CN103151010B (en) * | 2013-02-27 | 2014-12-10 | 京东方科技集团股份有限公司 | Shift register and display device |
| US9767916B2 (en) | 2013-02-27 | 2017-09-19 | Boe Technology Group Co., Ltd. | Shift register and display apparatus |
| CN104332137A (en) * | 2014-11-28 | 2015-02-04 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
| CN104332137B (en) * | 2014-11-28 | 2016-11-16 | 京东方科技集团股份有限公司 | Gate driver circuit and display device |
| US9881559B2 (en) | 2014-11-28 | 2018-01-30 | Boe Technology Group Co., Ltd. | Gate drive circuit and display device |
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