CN103093825A - Shifting register and alloy substrate electrode driving device - Google Patents
Shifting register and alloy substrate electrode driving device Download PDFInfo
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- CN103093825A CN103093825A CN2013100127084A CN201310012708A CN103093825A CN 103093825 A CN103093825 A CN 103093825A CN 2013100127084 A CN2013100127084 A CN 2013100127084A CN 201310012708 A CN201310012708 A CN 201310012708A CN 103093825 A CN103093825 A CN 103093825A
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Abstract
The embodiment of the invention provides a shifting register and an alloy substrate electrode driving device, and aims at shortening the operation time of a part of thin film transistors, improving the stability of the shifting register and also reducing the energy consumption of the shifting register. The shifting register comprises a pull-up node charging unit, an output unit, a pull-down control unit, a pull-up node discharging unit and an output discharging unit, wherein the output discharging control unit is used for responding to an input signal, used for providing a second voltage signal to the pull-up node discharging unit through a fourth node of the output discharging control unit, and used for responding to a reset signal to provide a first voltage signal to the pull-up node discharging unit through the fourth node of the output discharging control unit.
Description
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to a kind of shift register and array base palte gate drive apparatus.
Background technology
Thin Film Transistor-LCD TFT-LCD driver mainly comprises gate drivers and data driver, and wherein, gate drivers is added on the grid line of display panels after the clock signal of input is changed by shift register.Gate driver circuit has same process with the formation of TFT and is formed on simultaneously on the LCD panel together with TFT.Gate driver circuit comprises having multistage shift register.Every grade all is connected to corresponding gate line with the output gate drive signal.The at different levels of gate driver circuit are connected with each other, what start signal inputed to the first order at different levels and order exports gate drive signal to gate line, wherein the input end of prime is connected to the output terminal of upper level, and the output terminal of next stage is connected to the control end of prime.
The gate driver circuit of said structure is set on the right side of LCD panel, and its every one-level comprises structure as shown in Figure 1.Yet in gate driver circuit, the interference of the drift of transistor self threshold voltage and adjacent transistor may cause the shift register poor work stability and degradation problem under self life-span; Simultaneously, because the dutycycle of clock signal clk B is 50%, namely approximately there is time of 50% to be in the state of unlatching in response to the thin film transistor (TFT) of CLKB always, causes the power consumption of shift register larger.
Summary of the invention
The embodiment of the present invention provides a kind of shift register and array base palte gate drive apparatus, in order to shorten the working time of part thin film transistor (TFT), improves the stability of shift register, reduces simultaneously the power consumption of shift register.
A kind of shift register that the embodiment of the present invention provides comprises: on draw node charhing unit, output unit, drop-down control module, on draw node discharge unit and output discharge cell, described shift register also comprises output control of discharge unit, wherein,
Draw the node charhing unit on described, connect the input signal end, be used in response to input signal, the first voltage signal is offered lead-out terminal;
Described output unit, be connected to be arranged in draw the node charhing unit as on draw the first node of node charhing unit output terminal, be used for the voltage in response to first node, the first clock signal is offered lead-out terminal;
Described drop-down control module is used in response to the second clock signal, and the second clock signal is exported by the Section Point that is positioned at drop-down control module; The second clock signal that provides in response to Section Point is simultaneously exported the second clock signal by the 3rd node that is positioned at drop-down control module; And in response to the voltage of first node, with power cathode voltage by the 3rd node output;
Draw the node discharge unit on described, be used for the voltage in response to reset signal and the 3rd node, the second voltage signal is offered first node, and in response to the voltage of the 4th node, power cathode voltage is offered lead-out terminal;
Described output control of discharge unit, be used in response to input signal, the second voltage signal is offered by the 4th node that is positioned at this output control of discharge unit draw the node discharge unit, and in response to reset signal, the first voltage signal is offered by the 4th node that is positioned at this output control of discharge unit draw the node discharge unit;
Described output discharge cell is used for the voltage in response to the 3rd node, and power cathode voltage is exported by the output discharge cell.
A kind of array base palte gate drive apparatus that the embodiment of the present invention provides comprises the shift registers at different levels of cascade, wherein,
The input signal end of first order shift register connects the start signal end, and the reset signal end of first order shift register connects the lead-out terminal of second level shift register; The input signal end of afterbody shift register connects the lead-out terminal of previous stage shift register, and the reset signal end of afterbody shift register connects the start signal end;
Except the first order and afterbody shift register, the input signal end of all the other shift registers at different levels connects the lead-out terminal of upper level shift register, and the reset signal end connects the lead-out terminal of next stage shift register;
The shift register of all above-mentioned cascades is shift register provided by the invention.
The embodiment of the present invention provides a kind of shift register and array base palte gate drive apparatus, has further promoted stability and the transistorized serviceable life of the work of shift register, has reduced simultaneously the power consumption of shift register.
Description of drawings
Fig. 1 is the structural representation of shift register elementary cell in prior art;
The structural representation of a kind of shift register that Fig. 2 provides for the embodiment of the present invention;
The structural representation of a kind of array base palte gate drive apparatus that Fig. 3 provides for the embodiment of the present invention;
The clock signal figure of each signal end of a kind of shift register that Fig. 4 provides for the embodiment of the present invention.
Embodiment
The embodiment of the present invention provides a kind of shift register and array base palte gate drive apparatus, in order to shorten the working time of part thin film transistor (TFT), improves the stability of shift register, reduces simultaneously the power consumption of shift register.
Below in conjunction with accompanying drawing, the present invention will be described.
A kind of shift register that the embodiment of the present invention provides, its structure as shown in Figure 2, as can be seen from Figure 2, described register comprises: on draw node charhing unit 101, output unit 102, drop-down control module 103, on draw node discharge unit 104, output control of discharge unit 105 and output discharge cell 106, wherein
Draw node charhing unit 101 on described, connect the input signal end, be used in response to input signal, the first voltage signal is offered lead-out terminal;
Described output unit 102, be connected to be arranged in draw the node charhing unit as on draw the first node of node charhing unit output terminal, be used for the voltage in response to first node, the first clock signal is offered lead-out terminal;
Described drop-down control module 103 is used in response to the second clock signal, and the second clock signal is exported by the Section Point that is positioned at drop-down control module; The second clock signal that provides in response to Section Point is simultaneously exported the second clock signal by the 3rd node that is positioned at drop-down control module; And in response to the voltage of first node, with power cathode voltage by the 3rd node output;
Draw node discharge unit 104 on described, be used for the voltage in response to reset signal, the second voltage signal is offered first node, and in response to the voltage of the 4th node, just the second voltage signal offers lead-out terminal;
Described output control of discharge unit 105, be used in response to input signal, the second voltage signal is offered by the 4th node that is positioned at this output control of discharge unit draw the node discharge unit, and in response to reset signal, the first voltage signal is offered by the 4th node that is positioned at this output control of discharge unit draw the node discharge unit;
Described output discharge cell 106 is used for the voltage in response to the 3rd node, and power cathode voltage is exported by the output discharge cell.
Below in conjunction with specific embodiment, the present invention is described in detail.Need to prove, be for better explanation the present invention in the present embodiment, but do not limit the present invention.
Shift register as shown in Figure 2, comprise draw node charhing unit 101, output unit 102, drop-down control module 103, on draw node discharge unit 104, output control of discharge unit 105 and output discharge cell 106, wherein each module comprises each element accordingly, particularly
Draw node charhing unit 101 on described, comprising:
The first film transistor M1, its grid connects input end signal INPUT, and drain electrode connects the first voltage signal VDD, and source electrode connects first node P1.
Described output unit 102 comprises:
The second thin film transistor (TFT) M2, its drain electrode connects the first clock signal terminal CLK, and grid connects first node P1, and source electrode connects lead-out terminal OUTPUT;
Capacitor C, its first end connects first node P1, and the second end connects lead-out terminal OUTPUT.
Described drop-down control module 103 comprises:
The 3rd thin film transistor (TFT) M3, its drain and gate connect second clock signal end CLKB, and source electrode is as Section Point P2;
The 4th thin film transistor (TFT) M4, its drain electrode connects second clock signal end CLKB, and grid connects Section Point P2, and source electrode is as the 3rd node P3;
The 5th thin film transistor (TFT) M5, its drain electrode connects the 3rd node P3, and grid connects first node P1, and source electrode connects power cathode voltage end VGL;
The 6th thin film transistor (TFT) M6, its drain electrode connects Section Point P2, and grid connects first node P1, and source electrode connects power cathode voltage end VGL.
Draw node discharge unit 104 on described, comprising:
The 7th thin film transistor (TFT) M7, its grid connect reset signal end RESET, and the drain electrode utmost point connects first node P1, and source electrode connects second voltage signal VSS;
The 8th thin film transistor (TFT) M8, its grid connects the 4th node P4, and drain electrode connects lead-out terminal OUTPUT, and source electrode connects power cathode voltage end VGL.
Described output control of discharge unit 105 comprises:
The 9th thin film transistor (TFT) M9, its grid connects input end signal INPUT, and drain electrode connects second voltage signal VSS, and source electrode connects the 4th node P4;
The tenth thin film transistor (TFT) M10, its grid connects reset signal RESET, and source electrode connects the first voltage signal VDD, and drain electrode connects the 4th node P4.
Described output discharge cell 106 comprises:
The 11 thin film transistor (TFT) M11, its grid connects the 3rd node P3, and drain electrode connects first node P1, and source electrode connects power cathode voltage end VGL;
The 12 thin film transistor (TFT) M12, its grid connects the 3rd node P3, and drain electrode connects lead-out terminal OUTPUT, and source electrode connects power cathode voltage end VGL.
Preferably, above-mentioned all thin film transistor (TFT)s are P type thin film transistor (TFT) TFT.
Preferably, above-mentioned all thin film transistor (TFT)s are amorphous silicon film transistor.
In addition, the working time of thin film transistor (TFT) M11, (thin film transistor (TFT) M11 was connected on the CLKB signal by original 50%, the dutycycle of second clock signal CLKB is 50%) become a frame and only need delegation to open (be connected in the output of next line, just open when only having next line to open); And have, in prior art, the analog current of register is 2.2 * 10
-3A, and the shift register that the embodiment of the present invention provides, its analog current are 2.0 * 10
-3A descends approximately 10% compared to existing technology, effectively reduces the power consumption of shift register.
The above-mentioned shift register that the embodiment of the present invention provides on the basis of existing technology, has increased output control of discharge Unit Design, has shortened the working time of thin film transistor (TFT) M11, improves the stability of shift register, reduces simultaneously the power consumption of shift register.
Above-mentioned shift register cascade forms the array base palte gate driver circuit, a kind of array base palte gate drive apparatus that the embodiment of the present invention provides, the shift registers at different levels that comprise cascade, wherein, the input signal end of first order shift register connects the start signal end, and the reset signal end of first order shift register connects the lead-out terminal of second level shift register; The input signal end of afterbody shift register connects the lead-out terminal of previous stage shift register, and the reset signal end of afterbody shift register connects the start signal end;
Except the first order and afterbody shift register, the input signal end of all the other shift registers at different levels connects the lead-out terminal of upper level shift register, and the reset signal end connects the lead-out terminal of next stage shift register;
The shift register of all above-mentioned cascades is above-mentioned shift register.
particularly, this array base palte gate driver circuit comprises the N level, wherein N is grid line quantity, referring to Fig. 3, start signal STV is input to first order shift register as input signal, and the order export gate drive signal to gate line, the input signal of n level is provided by the output signal of n-1 level, n＜N wherein, reset signal is provided by the output signal of n+1 level, the reset signal of N level is that start signal STV provides by the input signal of the first order, that is to say that start signal STV one side is as the input signal of the first order, on the other hand as the reset signal of N level.
The sequential chart of each signal end that Fig. 4 is, the n(n in the array base palte gate driver circuit that the embodiment of the present invention is provided below in conjunction with Fig. 4＜N, N is the progression of array base palte grid circuit) level shift register method of work describe, wherein, all TFT are the high level conducting, the low level cut-off.
Phase one S1: the first clock signal clk is low level, second clock signal CLKB is high level, prime output signal G(n-1 as input signal) be high level, the output signal G(n+1 of subordinate as reset signal) be low level, VDD is high level signal, and VSS is low level signal.The input signal G (n-1) of high level makes transistor M1 conducting and capacitor C is charged, making first node P1 is high level, this moment, thin film transistor (TFT) M2 gate switch was opened, but due to this moment clock signal clk be low level, not conducting of thin film transistor (TFT) M2, output terminal G(n at this moment) output low level;
Subordinate phase S2: the first clock signal clk is high level, second clock signal CLKB is low level, input signal G(n-1) be low level, reset signal G(n+1) be low level, thin film transistor (TFT) M2 conducting this moment, output terminal G(n at this moment) the output high level;
Phase III S3: the first clock signal clk is low level, and second clock signal CLKB is high level, input signal G(n-1) be low level, reset signal G(n+1) be high level.This moment thin film transistor (TFT) M7 and thin film transistor (TFT) M10 conducting, the 4th node P4 is high level signal, thin film transistor (TFT) M8 conducting, capacitor C makes rapidly the P1 point reduce to low level by thin film transistor (TFT) M7 discharge, thin film transistor (TFT) M2 cut-off, the high level signal that the 4th node P4 provides for VDD, transistor M8 conducting, to output terminal G(n) carry out rapid discharge and make and be output as low level, realized reset function.
Perhaps,
Phase one S1: the first clock signal clk is low level, second clock signal CLKB is high level, prime output signal G(n+1 as input signal) be high level, the output signal G(n-1 of subordinate as reset signal) be low level, VDD is low level signal, and VSS is high level signal.The reset signal G of high level (n+1) makes thin film transistor (TFT) M7 conducting and capacitor C is charged, making first node P1 is high level, this moment, thin film transistor (TFT) M2 gate switch was opened, but due to this moment clock signal clk be low level, not conducting of thin film transistor (TFT) M2, output terminal G(n at this moment) output low level;
Subordinate phase S2: the first clock signal clk is high level, second clock signal CLKB is low level, input signal G(n+1) be low level, reset signal G(n-1) be low level, thin film transistor (TFT) M2 conducting this moment, output terminal G(n at this moment) the output high level;
Phase III S3: the first clock signal clk is low level, and second clock signal CLKB is high level, input signal G(n+1) be low level, reset signal G(n-1) be high level; This moment thin film transistor (TFT) M1 and thin film transistor (TFT) M9 conducting, capacitor C makes rapidly first node P1 point reduce to low level by thin film transistor (TFT) M1 discharge, the high level signal that the 4th node P4 provides for VSS, make thin film transistor (TFT) M8 conducting, to output terminal G(n) carry out rapid discharge and make and be output as low level, realized reset function.
In sum, the embodiment of the present invention provides a kind of shift register and array base palte gate driver circuit, this shift register has increased output control of discharge unit on the basis of existing technology, effectively shorten the working time of part thin film transistor (TFT), improve the stability of shift register, reduce simultaneously the power consumption of shift register.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. shift register, it is characterized in that, described shift register comprises: on draw node charhing unit, output unit, drop-down control module, on draw node discharge unit and output discharge cell, described shift register also comprises output control of discharge unit, wherein
Draw the node charhing unit on described, connect the input signal end, be used in response to input signal, the first voltage signal is offered lead-out terminal;
Described output unit, be connected to be arranged in draw the node charhing unit as on draw the first node of node charhing unit output terminal, be used for the voltage in response to first node, the first clock signal is offered lead-out terminal;
Described drop-down control module is used in response to the second clock signal, and the second clock signal is exported by the Section Point that is positioned at drop-down control module; The second clock signal that provides in response to Section Point is simultaneously exported the second clock signal by the 3rd node that is positioned at drop-down control module; And in response to the voltage of first node, with power cathode voltage by the 3rd node output;
Draw the node discharge unit on described, be used in response to reset signal, the second voltage signal is offered first node, and in response to the voltage of the 4th node, the second voltage signal is offered lead-out terminal;
Described output control of discharge unit, be used in response to input signal, the second voltage signal is offered by the 4th node that is positioned at this output control of discharge unit draw the node discharge unit, and in response to reset signal, the first voltage signal is offered by the 4th node that is positioned at this output control of discharge unit draw the node discharge unit;
Described output discharge cell is used for the voltage in response to the 3rd node, and power cathode voltage is exported by the output discharge cell.
2. shift register as claimed in claim 1, is characterized in that, draws the node charhing unit to comprise on described:
The first film transistor, its grid connects input end signal, and drain electrode connects the first voltage signal, and source electrode connects first node.
3. shift register as claimed in claim 1, is characterized in that, described output unit comprises:
The second thin film transistor (TFT), its drain electrode connects the first clock signal terminal, and grid connects first node, and source electrode connects lead-out terminal;
Electric capacity, its first end connects first node, and the second end connects lead-out terminal.
4. shift register as claimed in claim 1, is characterized in that, described drop-down control module comprises:
The 3rd thin film transistor (TFT), its drain and gate connects the second clock signal end, and source electrode is as Section Point;
The 4th thin film transistor (TFT), its drain electrode connects the second clock signal end, and grid connects Section Point, and source electrode is as the 3rd node;
The 5th thin film transistor (TFT), its drain electrode connects the 3rd node, and grid connects first node, and source electrode connects the power cathode voltage end;
The 6th thin film transistor (TFT), its drain electrode connects Section Point, and grid connects first node, and source electrode connects the power cathode voltage end.
5. shift register as claimed in claim 1, is characterized in that, draws on described the node discharge unit to comprise:
The 7th thin film transistor (TFT), its grid connects the reset signal end, and the drain electrode utmost point connects first node, and source electrode connects the second voltage signal;
The 8th thin film transistor (TFT), its grid connects the 4th node, and drain electrode connects lead-out terminal, and source electrode connects the power cathode voltage end.
6. shift register as claimed in claim 1, is characterized in that, described output control of discharge unit comprises:
The 9th thin film transistor (TFT), its grid connects input end signal, and drain electrode connects the second voltage signal, and source electrode connects the 4th node;
The tenth thin film transistor (TFT), its grid connects reset signal, and source electrode connects the first voltage signal, and drain electrode connects the 4th node.
7. shift register as claimed in claim 1, is characterized in that, described output discharge cell comprises:
The 11 thin film transistor (TFT), its grid connects the 3rd node, and drain electrode connects first node, and source electrode connects the power cathode voltage end;
The 12 thin film transistor (TFT), its grid connects the 3rd node, and drain electrode connects lead-out terminal, and source electrode connects the power cathode voltage end.
8. shift register as described in claim as arbitrary in claim 1～7, is characterized in that, all thin film transistor (TFT)s are P type thin film transistor (TFT) TFT.
9. shift register as claimed in claim 8, is characterized in that, all thin film transistor (TFT)s are amorphous silicon film transistor.
10. array base palte gate drive apparatus, the shift registers at different levels that comprise cascade, wherein, the input signal end of first order shift register connects the start signal end, and the reset signal end of first order shift register connects the lead-out terminal of second level shift register; The input signal end of afterbody shift register connects the lead-out terminal of previous stage shift register, and the reset signal end of afterbody shift register connects the start signal end;
Except the first order and afterbody shift register, the input signal end of all the other shift registers at different levels connects the lead-out terminal of upper level shift register, and the reset signal end connects the lead-out terminal of next stage shift register;
It is characterized in that, the shift register of all cascades is the described shift register of claim as arbitrary in claim 1-9.
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| CN104867439A (en) * | 2015-06-24 | 2015-08-26 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit and display device |
| CN105405387A (en) * | 2016-01-05 | 2016-03-16 | 京东方科技集团股份有限公司 | Shifting register unit, driving method thereof, gate drive circuit and display device |
| WO2017219585A1 (en) * | 2016-06-24 | 2017-12-28 | Boe Technology Group Co., Ltd. | Shift register unit, gate drive circuit having the same, and driving method thereof |
| US10204696B2 (en) | 2016-06-24 | 2019-02-12 | Boe Technology Group Co., Ltd. | Shift register unit, gate drive circuit having the same, and driving method thereof |
| WO2018126716A1 (en) * | 2017-01-04 | 2018-07-12 | 京东方科技集团股份有限公司 | Shift register unit, driving method thereof, gate driving device, and display device |
| CN106504720A (en) * | 2017-01-04 | 2017-03-15 | 合肥鑫晟光电科技有限公司 | Shift register cell and its driving method, gate drive apparatus and display device |
| US10650904B2 (en) | 2017-01-04 | 2020-05-12 | Boe Technology Group Co., Ltd. | Shift register unit and driving method thereof, gate driving apparatus and display apparatus |
| CN106920519A (en) * | 2017-05-10 | 2017-07-04 | 京东方科技集团股份有限公司 | A kind of shift register cell and shift register |
| WO2020147689A1 (en) * | 2019-01-18 | 2020-07-23 | 京东方科技集团股份有限公司 | Shift register and driving method therefor, gate driving circuit and display apparatus |
| CN109817153A (en) * | 2019-04-15 | 2019-05-28 | 合肥鑫晟光电科技有限公司 | Drive element of the grid, grid drive method, gate driving circuit and display device |
| CN109817153B (en) * | 2019-04-15 | 2022-04-29 | 合肥鑫晟光电科技有限公司 | Gate driving unit, gate driving method, gate driving circuit and display device |
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