CN203086410U - Zero-output large dynamic wide-band amplifier circuit - Google Patents
Zero-output large dynamic wide-band amplifier circuit Download PDFInfo
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- CN203086410U CN203086410U CN 201320066541 CN201320066541U CN203086410U CN 203086410 U CN203086410 U CN 203086410U CN 201320066541 CN201320066541 CN 201320066541 CN 201320066541 U CN201320066541 U CN 201320066541U CN 203086410 U CN203086410 U CN 203086410U
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Abstract
The utility model discloses a zero-output large dynamic wide-band amplifier circuit. A reverse input wiring terminal to a first output end and a positive input wiring terminal to a second output end are symmetrically arranged, so that the reverse symmetric output is realized; and besides, a zero-adjusting wiring terminal is arranged, so that the double output signal function which takes a zero level as a midpoint is realized. In conclusion, the zero-output large dynamic wide-band amplifier circuit disclosed by the utility model can realize the high-magnification symmetric reverse-phase double output and the double output signal function which takes the zero level as the midpoint.
Description
Technical field
The utility model relates to a kind of amplifier, is specifically related to the big dynamically wide-band amplifier circuit of a kind of zero output.
Background technology
Amplifier is to have the very circuit unit of high-amplification-factor, in side circuit, forms certain functional module jointly in conjunction with feedback network usually.Owing to be applied in the simulation computer in early days, in order to realize mathematical operation, so gain the name " operational amplifier ".Amplifier is a circuit unit from the view of function name, can be realized by discrete device, also can be implemented in the middle of the semiconductor chip.Along with development of semiconductor, most amplifier is that the form with single-chip exists.Amplifier of a great variety is widely used in the middle of the electron trade.
And the current amplifier that is present in the amplifier of industry for high-amplification-factor is difficult to realize fully symmetrical anti-phase dual output and is the dual output semiotic function of mid point with the zero level.
The utility model content
At the problem that prior art exists, the purpose of this utility model is to provide a kind of zero output big dynamically wide-band amplifier circuit, and it can be realized the high-amplification-factor anti-phase dual output of symmetry and be the dual output semiotic function of mid point with the zero level.
The big dynamically wide-band amplifier circuit of a kind of zero output that the utility model provides, it comprises input circuit, middle amplifying circuit and output driving circuit, wherein,
Described input circuit comprises the forward input terminal, reverse input terminal, the first order differential amplifier circuit and first rectification circuit, described first order differential amplifier circuit comprises first triode (T1) and second triode (T2), and first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5) and the 6th resistance (R6), wherein, described first resistance (R1), described the 3rd resistance (R3), described the 4th resistance (R4) and described second resistance (R2) are located between the emitter of described first triode (T1) and described second triode (T2) in turn, and described the 5th resistance (R5) and described the 6th resistance (R6) are located between the collector electrode of described first triode (T1) and described second triode (T2) in turn;
Amplifying circuit comprises first amplifying circuit in the middle of described, second amplifying circuit, the zeroing terminals, second rectification circuit, the 3rd rectification circuit and the 4th rectification circuit, wherein, described first amplifying circuit comprises and is symmetrically arranged the 3rd triode (T3) and the 4th triode (T4), described second amplifying circuit comprises and is symmetrically arranged the 5th triode (T5) and the 6th triode (T6), and the 8th resistance (R8) and the 9th resistance (R9) that connect the collector electrode of described the 5th triode (T5) and described the 6th triode (T6), the base stage of described the 3rd triode (T3) directly is connected with the collector electrode of described first triode (T1), the base stage of described the 4th triode (T4) directly is connected with the collector electrode of described second triode (T2), the base stage of described the 6th triode (T6) is connected via the emitter of the 11 resistance (R11) with described the 3rd triode (T3), the base stage of described the 5th triode (T5) is connected via the emitter of the 12 resistance (R12) with described the 4th triode (T4), and described zeroing terminals are connected with the common port of described the 8th resistance (R8) with described the 9th resistance (R9);
Described output driving circuit comprises the positive voltage terminals, first output, second output, the negative pressure terminals, amplitude modulation terminals and fourth stage amplifying circuit, described the 4th amplifying circuit comprises and is symmetrically arranged the 7th triode (T7) and the 8th triode (T8), the base stage of described the 7th triode (T7) is connected via the emitter of described the 11 resistance (R11) with described the 3rd triode (T3), the base stage of described the 8th triode (T8) is connected via the emitter of described the 12 resistance (R12) with described the 4th triode (T4), described first output is connected with the emitter of described the 8th triode (T8), and described second output is connected with the emitter of described the 7th triode (T7).
Based on disclosing of above technical scheme, the utility model possesses following beneficial effect:
In the big dynamically wide-band amplifier circuit of a kind of zero output that the utility model provides, described reverse input terminal is to described first output and described forward input terminal to described second output and is symmetrical arranged, thereby, the output of realization reverse symmetry, in addition, be provided with described zeroing terminals, and realize with the zero level being the dual output semiotic function of mid point, in summary, the big dynamically wide-band amplifier circuit of the zero output that the utility model provides, it can be realized the high-amplification-factor anti-phase dual output of symmetry and be the dual output semiotic function of mid point with the zero level.
Description of drawings
The big dynamically structure chart of wide-band amplifier circuit of a kind of zero output that Fig. 1 provides for the utility model.
The drawing reference numeral explanation
Middle amplifying circuit 200
Reverse input terminal 2
Embodiment
Further specify the technical solution of the utility model below in conjunction with accompanying drawing and by embodiment:
At the problem that prior art exists, the purpose of this utility model is to provide a kind of zero output big dynamically wide-band amplifier circuit, and it can be realized the high-amplification-factor anti-phase dual output of symmetry and be the dual output semiotic function of mid point with the zero level.
See also Fig. 1, the big dynamically wide-band amplifier circuit of a kind of zero output that the utility model provides, it comprises input circuit 100, middle amplifying circuit 200 and output driving circuit 300.
See also Fig. 1, described input circuit 100 comprises forward input terminal 1, reverse input terminal 2, first order differential amplifier circuit (not label) and first rectification circuit (not label), described first order differential amplifier circuit comprises the first triode T1 and the second triode T2, and first resistance R 1, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5 and the 6th resistance R 6, wherein, described first resistance R 1, described the 3rd resistance R 3, described the 4th resistance R 4 and described second resistance R 2 are located between the emitter of described first triode T1 and the described second triode T2 in turn, described the 5th resistance R 5 and described the 6th resistance R 6 are located between the collector electrode of described first triode T1 and the described second triode T2 in turn, described first rectification circuit comprises the 9th triode T9 and the 7th resistance R 7, the collector electrode of described the 9th triode T9 is connected with the common port of described the 3rd resistance R 3 and described the 4th resistance R 4, and the emitter of described the 9th triode T9 is connected with an end of described the 7th resistance R 7.
See also Fig. 1, amplifying circuit 200 comprises first amplifying circuit (not label) in the middle of described, second amplifying circuit (not label), zeroing terminals 3, second rectification circuit (not label), the 3rd rectification circuit (not label) and the 4th rectification circuit (not label), wherein, described first amplifying circuit comprises and is symmetrically arranged the 3rd triode T3 and the 4th triode T4, described second amplifying circuit comprises and is symmetrically arranged the 5th triode T5 and the 6th triode T6, and the 8th resistance R 8 and the 9th resistance R 9 that connect the collector electrode of described the 5th triode T5 and described the 6th triode T6, the base stage of described the 3rd triode T3 directly is connected with the collector electrode of the described first triode T1, the base stage of described the 4th triode T4 directly is connected with the collector electrode of the described second triode T2, the base stage of described the 6th triode T6 is connected with the emitter of described the 3rd triode T3 via the 11 resistance R 11, the base stage of described the 5th triode T5 is connected with the emitter of described the 4th triode T4 via the 12 resistance R 12, described zeroing terminals 3 are connected with the common port of described the 8th resistance R 8 and described the 9th resistance R 9, described second rectification circuit comprises the tenth triode T10 and the tenth resistance R 10, the collector electrode of described the tenth triode T10 is connected with the common port of described the 8th resistance R 8 and described the 9th resistance R 9, the emitter of described the tenth triode T10 is connected with an end of described the tenth resistance R 10, the base stage of described the tenth triode T10 is connected with the base stage of described the 9th triode T9, described the 3rd rectification circuit comprises the 11 triode T11 and the 13 resistance R 13, the collector electrode of described the 11 triode T11 is connected with the emitter of described the 3rd triode T3 via described the 11 resistance R 11, the emitter of described 11 triode T11 is connected with an end of described the 13 resistance R 13, the base stage of described 11 triode T11 is connected with the base stage of described the tenth triode T10, described the 4th rectification circuit comprises the 12 triode T12 and the 14 resistance R 14, the collector electrode of described the 12 triode T12 is connected with the emitter of described four triode T4 via described the 12 resistance R 12, the emitter of described the 12 triode T12 is connected with an end of described the 14 resistance R 14, and the base stage of described the 12 triode T12 is connected with the base stage of described the 11 triode T11.
See also Fig. 1, described output driving circuit 300 comprises positive voltage terminals 4, first output 5, second output 6, negative pressure terminals 7, amplitude modulation terminals 8 and fourth stage amplifying circuit (not label), described the 4th amplifying circuit comprises and is symmetrically arranged the 7th triode T7 and the 8th triode T8, the base stage of described the 7th triode T7 is connected with the emitter of described the 3rd triode T3 via described the 11 resistance R 11, the base stage of described the 8th triode T8 is connected with the emitter of described the 4th triode T4 via described the 12 resistance R 12, described first output 5 is connected with the emitter of described the 8th triode T8, described second output 6 is connected with the emitter of described the 7th triode T7, described the 5th rectification circuit comprises the 13 triode T13 and the 15 resistance R 15, the collector electrode of described the 13 triode T13 is connected with the emitter of described the 7th triode T7, the emitter of described the 13 triode T13 is connected with an end of described the 15 resistance R 15, the base stage of described the 13 triode T13 is connected with the base stage of described the 12 triode T12, described the 6th rectification circuit comprises the 14 triode T14 and the 16 resistance R 16, the collector electrode of described the 14 triode T14 is connected with the emitter of described the 8th triode T8, the emitter of described the 14 triode T14 is connected with an end of described the 16 resistance R 16, the base stage of described the 14 triode T14 is connected with the base stage of described the 13 triode T13, and described amplitude modulation terminals 8 are connected with the emitter of described the 13 triode T13 and described the 14 triode T14 respectively with the 18 resistance R 18 by the 17 resistance R 17.
Based on disclosing of above technical scheme, the utility model possesses following beneficial effect:
In the big dynamically wide-band amplifier circuit of a kind of zero output that the utility model provides, described reverse input terminal 2 to described first output 5 and described forward input terminal 1 is to described second output 6 and is symmetrical arranged, thereby, the output of realization reverse symmetry, in addition, be provided with described zeroing terminals 3, and realize with the zero level being the dual output semiotic function of mid point, in summary, the big dynamically wide-band amplifier circuit of the zero output that the utility model provides, it can be realized the high-amplification-factor anti-phase dual output of symmetry and be the dual output semiotic function of mid point with the zero level.
In conjunction with the accompanying drawings the utility model has been carried out exemplary description above; obvious realization of the present utility model is not subjected to the restriction of aforesaid way; as long as the various improvement of having adopted method design of the present utility model and technical scheme to carry out; or design of the present utility model and technical scheme are directly applied to other occasion without improving, all in protection range of the present utility model.
Claims (1)
1. the big dynamically wide-band amplifier circuit of a zero output, it comprises input circuit, middle amplifying circuit and output driving circuit, wherein,
Described input circuit comprises the forward input terminal, reverse input terminal, the first order differential amplifier circuit and first rectification circuit, described first order differential amplifier circuit comprises first triode (T1) and second triode (T2), and first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5) and the 6th resistance (R6), wherein, described first resistance (R1), described the 3rd resistance (R3), described the 4th resistance (R4) and described second resistance (R2) are located between the emitter of described first triode (T1) and described second triode (T2) in turn, and described the 5th resistance (R5) and described the 6th resistance (R6) are located between the collector electrode of described first triode (T1) and described second triode (T2) in turn;
Amplifying circuit comprises first amplifying circuit in the middle of described, second amplifying circuit, the zeroing terminals, second rectification circuit, the 3rd rectification circuit and the 4th rectification circuit, wherein, described first amplifying circuit comprises and is symmetrically arranged the 3rd triode (T3) and the 4th triode (T4), described second amplifying circuit comprises and is symmetrically arranged the 5th triode (T5) and the 6th triode (T6), and the 8th resistance (R8) and the 9th resistance (R9) that connect the collector electrode of described the 5th triode (T5) and described the 6th triode (T6), the base stage of described the 3rd triode (T3) directly is connected with the collector electrode of described first triode (T1), the base stage of described the 4th triode (T4) directly is connected with the collector electrode of described second triode (T2), the base stage of described the 6th triode (T6) is connected via the emitter of the 11 resistance (R11) with described the 3rd triode (T3), the base stage of described the 5th triode (T5) is connected via the emitter of the 12 resistance (R12) with described the 4th triode (T4), and described zeroing terminals are connected with the common port of described the 8th resistance (R8) with described the 9th resistance (R9);
Described output driving circuit comprises the positive voltage terminals, first output, second output, the negative pressure terminals, amplitude modulation terminals and fourth stage amplifying circuit, described the 4th amplifying circuit comprises and is symmetrically arranged the 7th triode (T7) and the 8th triode (T8), the base stage of described the 7th triode (T7) is connected via the emitter of described the 11 resistance (R11) with described the 3rd triode (T3), the base stage of described the 8th triode (T8) is connected via the emitter of described the 12 resistance (R12) with described the 4th triode (T4), described first output is connected with the emitter of described the 8th triode (T8), and described second output is connected with the emitter of described the 7th triode (T7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320066541 CN203086410U (en) | 2013-02-05 | 2013-02-05 | Zero-output large dynamic wide-band amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320066541 CN203086410U (en) | 2013-02-05 | 2013-02-05 | Zero-output large dynamic wide-band amplifier circuit |
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| Publication Number | Publication Date |
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| CN203086410U true CN203086410U (en) | 2013-07-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320066541 Expired - Fee Related CN203086410U (en) | 2013-02-05 | 2013-02-05 | Zero-output large dynamic wide-band amplifier circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211744A (en) * | 2020-01-09 | 2020-05-29 | 苏州大学 | Amplifier for inertial stick-slip drive circuit |
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2013
- 2013-02-05 CN CN 201320066541 patent/CN203086410U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211744A (en) * | 2020-01-09 | 2020-05-29 | 苏州大学 | Amplifier for inertial stick-slip drive circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130724 Termination date: 20190205 |