CN202996456U - Double-insulating-layer chip type resistor - Google Patents
Double-insulating-layer chip type resistor Download PDFInfo
- Publication number
- CN202996456U CN202996456U CN 201220453451 CN201220453451U CN202996456U CN 202996456 U CN202996456 U CN 202996456U CN 201220453451 CN201220453451 CN 201220453451 CN 201220453451 U CN201220453451 U CN 201220453451U CN 202996456 U CN202996456 U CN 202996456U
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating
- insulating substrate
- insulating barrier
- resistive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Non-Adjustable Resistors (AREA)
Abstract
The utility model discloses a double-insulating-layer chip type resistor comprising an insulating substrate, a bottom insulating layer, surface electrodes, a resistive layer, end electrodes and a surface insulating layer, wherein the bottom insulating layer is arranged on the upper surface of the insulating substrate, the surface electrodes are respectively arranged on the upper surface of the bottom insulating layer and the upper surface of the insulating substrate, the resistive layer is arranged on the upper surface of a bottom layer protective layer and is connected with the two surface electrodes, the end electrodes are respectively arranged at two ends of the insulating substrate and connected with the corresponding surface electrodes, the surface insulating layer is arranged on the upper surface of the resistive layer, and the resistive layer is disposed between the bottom insulating layer and the surface insulating layer. The resistive layer does not directly contact the insulating substrate, the phenomenon that materials of the resistive layer permeate in the insulating substrate due to a part of gaps of the insulating substrate is avoided, and stability of products is improved.
Description
Technical field
The utility model relates to a kind of resistor, particularly relates to a kind of double insulating layer chip resistor.
Background technology
Along with electronic technology develops rapidly, the integrated level of electronic product is more and more higher, and is also more and more higher to the requirement of electronic devices and components.Existing chip resistor is divided into two kinds, thick-film type rear film type by production technology.Thick-film type adopts silk screen printing resistive material to be deposited on insulating body, sintering forms, film-type is to adopt in a vacuum the techniques such as evaporation and sputter that resistive material is deposited in to make on insulating body, characteristics are low-temperature coefficient (± 5PPM/ ℃), high accuracy (± 0.01% ~ ± 1%).The miniaturization of device is had higher requirement to stability and the reliability of its characteristic, therefore, also requires higher to the material of its use and the characteristic of product structure.Use device reliability higher than the requirement of general electronic products for the high-precision electronic product to it, use the small parameter fluctuation of device just can affect the reliability of this electronic product.Resistive layer is the key components of chip resistor, and its characteristic directly affects the performance of resistor.At present, adopt printing or sputter with the resistive layer Direct precipitation on insulating substrate, if sintering film forming after the printing of resistive layer employing conductive paste, be prone to the situation that conductive paste infiltrates insulating substrate after sintering, cause that the inhomogeneous and conductive particle of resistive layer enters insulating material, thereby affect the performance of product.
Therefore, infiltrating insulating substrate for avoiding conductive paste, further improve stability and the reliability of resistor, is a problem that can not be ignored of these technical field research and development to the relevant treatment of insulating substrate.
The utility model content
The purpose of this utility model is the resistor that a kind of simple in structure and stable performance is provided in order to address the above problem.
For achieving the above object, the utility model has adopted following technical scheme:
a kind of double insulating layer chip resistor described in the utility model, comprise insulating substrate, the bottom insulating barrier, the table electrode, resistive layer, termination electrode and surface insulation layer, described bottom insulating barrier is arranged on the upper surface of described insulating substrate, described table electrode is separately positioned on the upper surface of described bottom insulating barrier and described insulating substrate, described resistive layer is arranged on the upper surface of described bottom insulating barrier and connects two described table electrodes, described termination electrode is separately positioned on the two ends of described insulating substrate and connects corresponding table electrode, described top layer insulating barrier is arranged on the upper surface of described resistive layer, described resistive layer is arranged between described bottom insulating barrier and described top layer protective layer.
Print in advance a layer insulating on insulating substrate, this insulating layer material has namely been filled the fine and close and minim gap that produces of insulating substrate part, also provide a smooth adhesion layer to resistive layer, make resistive layer that a better cling matrix better be arranged and avoided resistive layer under ooze situation, make more all even densifications of resistive layer, strengthen the characteristic of resistor.
As preferred plan, described bottom insulating barrier is the glass medium insulating barrier.
Particularly, described table electrode is metallic conduction cream, and described top layer insulating barrier is the glass medium insulating barrier, adopts silk screen printing to form conductive pattern and protective layer figure.
Further, described termination electrode comprises metallic conduction cream and the coat of metal, and it is surperficial that the described coat of metal is arranged at described metallic conduction cream.The described coat of metal adopts electroplating technology to realize, also can adopt other mode.
The beneficial effects of the utility model are:
Resistive layer of the present utility model and insulating substrate directly contacts, have avoided the resistive layer material infiltration insulating substrate inside that causes because of the insulating substrate not fine and close generation of part space, have improved the stability of product.
Description of drawings
Fig. 1 is the stereogram of the utility model double insulating layer chip resistor;
Fig. 2 is the view in transverse section of Fig. 1;
Fig. 3 is the vertical view after Fig. 1 removes surface insulation layer.
In figure: the 1-insulating substrate, 2-bottom insulating barrier, the 3-resistive layer, 4-shows electrode, 5-termination electrode, 6-surface insulation layer.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, embodiment of the present utility model is described in further detail:
As depicted in figs. 1 and 2, a kind of resistor described in the utility model, comprise insulating substrate 1, upper surface at insulating substrate 1 arranges one deck bottom insulating barrier 2, upper surface at the two ends of insulating substrate 1 bottom insulating barrier 2 arranges the lower surface of showing electrode 4 and extending to insulating substrate 1, resistive layer 3 arranges the upper surface of bottom insulating barrier 2 and connects the table electrode 4 at two ends, termination electrode 5 is separately positioned on the two ends of insulating substrate 1 and is arranged on the surface of corresponding table electrode 4, and surface insulation layer 6 is arranged on the surface of resistive layer 3 and insulating substrate 1.As shown in Figure 3, the width of bottom insulating barrier 2 is less than the width of insulating substrate 1, and the width of resistive layer 3 is less than the width of bottom insulating barrier 2.In resistor structure, increase one deck bottom insulating barrier 2, strengthened evenness and the density of resistive layer carrier contact-making surface, avoid resistive layer to infiltrate insulating substrate 1, to reach the purpose that improves the resistor performance.
Above-described embodiment is only a kind of embodiment of the present utility model; illustrative and not restrictive; also have many variations all to belong to the technical solution of the utility model; can two-layer or multilayer as the bottom insulating barrier; the material of each layer can be the same or different; therefore, be change and revise not breaking away under the utility model design that institute makes, all within protection range of the present utility model.
Claims (6)
1. double insulating layer chip resistor, comprise insulating substrate, the table electrode, resistive layer, termination electrode and top layer superficial layer, described table electrode is separately positioned on the two ends of described insulating substrate carrier, described resistive layer is arranged on described insulating substrate carrier and connects two described table electrodes, described termination electrode is separately positioned on the two ends of described insulating substrate and connects corresponding table electrode, described top layer insulating barrier is arranged on the upper surface of described resistive layer, it is characterized in that: also comprise the bottom insulating barrier, described bottom insulating barrier is arranged on the upper surface of described insulating substrate, described resistive layer is arranged between described bottom insulating barrier and described top layer insulating barrier.
2. a kind of double insulating layer chip resistor according to claim 1, it is characterized in that: described bottom insulating barrier is the glass medium insulating barrier.
3. a kind of double insulating layer chip resistor according to claim 1, it is characterized in that: described resistive layer is the conductive paste resistive layer.
4. a kind of double insulating layer chip resistor according to claim 1, it is characterized in that: described table electrode is metallic conduction cream table electrode.
5. a kind of double insulating layer chip resistor according to claim 1, it is characterized in that: described termination electrode comprises metallic conduction cream layer and the coat of metal, the described coat of metal is arranged at the surface of described metallic conduction cream layer.
6. a kind of double insulating layer chip resistor according to claim 1, it is characterized in that: described top layer insulating barrier is the glass medium insulating barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220453451 CN202996456U (en) | 2012-09-07 | 2012-09-07 | Double-insulating-layer chip type resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220453451 CN202996456U (en) | 2012-09-07 | 2012-09-07 | Double-insulating-layer chip type resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202996456U true CN202996456U (en) | 2013-06-12 |
Family
ID=48567602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220453451 Expired - Fee Related CN202996456U (en) | 2012-09-07 | 2012-09-07 | Double-insulating-layer chip type resistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202996456U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680782A (en) * | 2012-09-07 | 2014-03-26 | 成都默一科技有限公司 | Bilayer-insulator chip resistor |
| CN112567482A (en) * | 2018-08-10 | 2021-03-26 | 罗姆股份有限公司 | Resistor with a resistor element |
-
2012
- 2012-09-07 CN CN 201220453451 patent/CN202996456U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680782A (en) * | 2012-09-07 | 2014-03-26 | 成都默一科技有限公司 | Bilayer-insulator chip resistor |
| CN112567482A (en) * | 2018-08-10 | 2021-03-26 | 罗姆股份有限公司 | Resistor with a resistor element |
| US11335480B2 (en) | 2018-08-10 | 2022-05-17 | Rohm Co., Ltd. | Resistor |
| US11823819B2 (en) | 2018-08-10 | 2023-11-21 | Rohm Co., Ltd. | Resistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104576048B (en) | Multilayer ceramic capacitor and the plate of multilayer ceramic capacitor is installed thereon | |
| CN103412668B (en) | Touch screen induction module and manufacturing method thereof, and displayer | |
| US9368251B2 (en) | Multilayer ceramic capacitor with conductive fullerene-filling resin layer, method for same, and mounting board with same | |
| CN102543894B (en) | Electrical connection pad structure and integrated circuit comprising a plurality of electrical connection pad structures | |
| CN101692360A (en) | Chip type thermal resistor and manufacturing method thereof | |
| CN102082017B (en) | Manufacturing method of surface mounted device resistor | |
| CN202996456U (en) | Double-insulating-layer chip type resistor | |
| CN104216594A (en) | Low-impedance capacitive touch screen and manufacturing method thereof | |
| CN202816523U (en) | Chip resistor with double resistive layers | |
| CN203178979U (en) | Touch screen induction module and display with same | |
| CN201196910Y (en) | Packaging body used for sheet-type multilayer ceramic capacitor and sheet-type multi-layer piezoresistor | |
| CN203870600U (en) | Uniwafer capacitive touch sensor | |
| CN103680782A (en) | Bilayer-insulator chip resistor | |
| CN202855461U (en) | Chip resistor | |
| CN204918466U (en) | Conducting adhesive tape | |
| CN204215387U (en) | A kind of low-impedance capacitor touch-screen | |
| CN203057693U (en) | Capacitive type ceramic circuit board | |
| CN201527866U (en) | Surface mounted concave type electrode network resistor | |
| CN207744231U (en) | Circuit board | |
| CN203311395U (en) | Capacitive touch screen with three-dimensional via hole | |
| CN201788828U (en) | Solid-state tantalum capacitor | |
| CN205196097U (en) | Miniature piece formula electronic component | |
| CN201993729U (en) | Equivalent potential adjustment structure for touch panel | |
| CN210986582U (en) | PCB based on nanoscale carbon resistor | |
| CN202259637U (en) | 20-watt load plate with impedance of 50 Omega and with thin aluminum nitride ceramic substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20131126 Address after: 518000 A5 block B2, third industrial zone, Yan Chuan, Songgang street, Baoan District, Guangdong, Shenzhen Patentee after: Shenzhen Pak Heng Electronics Co., Ltd. Address before: High tech Zone Gaopeng road in Chengdu city of Sichuan province 610041 5 block A No. 2 A-320 Patentee before: Chengdu Moyi Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130612 Termination date: 20170907 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |