CN202870294U - Electromagnetic environment simulation intensive pulse flow generation system - Google Patents
Electromagnetic environment simulation intensive pulse flow generation system Download PDFInfo
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- CN202870294U CN202870294U CN 201220572084 CN201220572084U CN202870294U CN 202870294 U CN202870294 U CN 202870294U CN 201220572084 CN201220572084 CN 201220572084 CN 201220572084 U CN201220572084 U CN 201220572084U CN 202870294 U CN202870294 U CN 202870294U
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Abstract
The utility model relates to the field of electromagnetic environment simulation pulse flows, and discloses an electromagnetic environment simulation intensive pulse flow generation system. The electromagnetic environment simulation intensive pulse flow generation system comprises a first memory, a second memory, an FPGA module, a PCI bridging chip and a PCI bus, wherein the FPGA module is electrically connected with the first memory, the second memory, the PCI bridging chip and the PCI bus respectively. The electromagnetic environment simulation intensive pulse flow generation system uses double memories, implements a ping-pong mode of downloading while replaying, and generates high-speed and real radar pulse signals.
Description
Technical field
The utility model relates to electromagnetic environment analog pulse stream field, relates in particular to a kind of electromagnetic environment and simulates intensive stream of pulses and produce system.
Background technology
In electro-magnetic environment simulator, with single channel simulation multiple goal radar emission signal, main control computer can be in advance setting calculates whole time domains, frequency domain and the amplitude characteristic that needs the radar generated pulse train that produces according to combat, and be stored in the hard disc of computer in coding (pulse describing word) mode; When l-G simulation test begins, computing machine imports the hard disc data segmentation among the SRAM of simulator main pulse generation unit, this unit hardware steering logic automatically from SRAM order read the pulse describing word, output video main pulse and relevant parallel data are to the baseband signal generation unit after the decoding.
Be electromagnetic environment that is virtually reality like reality, the stream of pulses density that needs to produce should be not less than 500,000 pulse/sec, and this real-time to scheme has proposed very high requirement.Be without loss of generality, suppose that a l-G simulation test need continue about 30 minutes, the train of impulses number that then need produce is 30 * 60 * 5,000,00=,900 000 000, suppose that a pulse describing word need take 9 storage unit (the wide 32bit of being of word), so total storage depth of train of impulses is: 900000000 * 9 * 32bit=30G * 8bit=30GByte.So the data of flood tide all once are stored in the main pulse generation unit, and are obviously unrealistic, if use existing memory capacity to store, Data duplication is play in process of the test, then real analog electrical magnetic environment signal again.
Summary of the invention
The purpose of the utility model embodiment is: provide a kind of electromagnetic environment to simulate intensive stream of pulses and produce system, have at a high speed, produce really radar pulse signal.
A kind of electromagnetic environment that the utility model embodiment provides is simulated intensive stream of pulses and is produced system, comprising:
First memory, second memory, buffer memory pulse describing word;
The FPGA module receives the data that transmission is come in, and described data sectional is stored to first memory and second memory, simultaneously can also be respectively reads the row decoding playback of going forward side by side of pulse describing word from described first memory or second memory;
The PCI bridging chip is realized the data communication between described FPGA module and described pci bus;
Pci bus is delivered to described FPGA module with 1ms step-length form by described PCI bridging chip with the l-G simulation test data of segmentation;
Described FPGA module links to each other with described first memory, second memory, PCI bridging chip, the mutual electricity of pci bus respectively.
Optionally, described first memory and second memory are selected the IDT70V7519 model.
Optionally, described FPGA module is selected XC3S2000 series.
Optionally, the PCI9056 model of described PCI bridging chip employing.
Optionally, described pci bus employing is the 32bit/33MHz pci bus.
Therefore, use the technical scheme of the utility model embodiment, adopting two storeies is first memory and second memory, for providing the ping pong scheme of limit download and limit playback, described FPGA module produces radar pulse, namely when described FPGA module during to described first memory downloading data, also can read the pulse describing word from described second memory and decipher playback, perhaps when described FPGA module during to described second memory downloading data, also can read the pulse describing word from described first memory and decipher playback.Meanwhile, the pci bus with high-speed downloads ability is carried out high-speed downloads and the transmission of data by described PCI bridging chip, thereby realizes the communication of data, and is final so that described FPGA module realizes real time modelling generation stream of radar pulses signal.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present utility model, consists of the application's a part, does not consist of to improper restriction of the present utility model, in the accompanying drawings:
A kind of electromagnetic environment that Fig. 1 provides for the utility model embodiment 1 is simulated the structured flowchart of the system of intensive stream of pulses generation.
Embodiment
Describe the utility model in detail below in conjunction with accompanying drawing and specific embodiment, be used for explaining the utility model in this illustrative examples of the present utility model and explanation, but not as to restriction of the present utility model.
Embodiment 1:
As shown in Figure 1, electromagnetic environment described in the utility model is simulated the system that intensive stream of pulses produces, comprise first memory 1, second memory 2, FPGA module 3, PCI bridging chip 4 and pci bus 5, described FPGA module 3 links to each other with described first memory 1, second memory 2, PCI bridging chip 4, pci bus 5 mutual electricity respectively.
What described first memory 1 and second memory 2 were selected respectively is the IDT70V7519 model, has the high-speed SRAM chip of 8K * 32bit, is used for cushioning the pulse describing word.Suppose that impulse density is 500,000 pulse/sec, average per 2 μ s come a pulse, the minimum emulation cycle is namely rattled the interval when being made as 1ms, the storage depth of first memory 1 or second memory 2 all is not less than 1ms ÷ 2 a μ s=500 pulse describing word, a pulse describing word takies 9 * 32bit, so the storage depth of first memory 1 or second memory 2 is 500 * 9 * 32bit=4500 * 32bit ≈ 4.39K * 32bit.
Described FPGA module 3, what select is the XC3S2000 family chip, can receive the data that transmission is come in, and described data sectional is stored to first memory 1 and second memory 2, simultaneously can also be respectively read the row decoding playback of going forward side by side of pulse describing word from described first memory 1 or second memory 2, but in this process, described speed of download must be faster than playback speed, could satisfy like this real-time working of whole system.
Described PCI bridging chip 4, employing be the PCI9056 model, be used for realizing the data communication between described FPGA module and described pci bus.
Described pci bus, the large 32bit/33MHz of speed of download is delivered to described FPGA module 3 with 1ms step-length form by described PCI bridging chip with the l-G simulation test data of segmentation.Storage depth according to above-mentioned first memory 1 and second memory 2 is about 4.39K * 32bit, if the pulse of playback 1ms, need download to such an extent that data volume can be set as 4.5K * 32bit, the speed of download of described pci bus can reach 32bit33MHz simultaneously, so the time that the number needs of downloading first memory 1 or second memory 2 is used is 4500 * 30ns=0.135ms, be far smaller than the 1ms of prior art, fully requirement of real time.
More than technical scheme that the utility model embodiment is provided be described in detail, used specific case herein principle and the embodiment of the utility model embodiment are set forth, the explanation of above embodiment is only applicable to help to understand the principle of the utility model embodiment; Simultaneously, for one of ordinary skill in the art, according to the utility model embodiment, all will change on embodiment and range of application, in sum, this description should not be construed as restriction of the present utility model.
Claims (5)
1. an electromagnetic environment is simulated the system that intensive stream of pulses produces, and it is characterized in that, comprising:
First memory, second memory, buffer memory pulse describing word;
The FPGA module receives the data that transmission is come in, and described data sectional is stored to first memory and second memory, simultaneously can also be respectively reads the row decoding playback of going forward side by side of pulse describing word from described first memory or second memory;
The PCI bridging chip is realized the data communication between described FPGA module and described pci bus;
Pci bus is delivered to described FPGA module with 1ms step-length form by described PCI bridging chip with the l-G simulation test data of segmentation;
Described FPGA module links to each other with described first memory, second memory, PCI bridging chip, the mutual electricity of pci bus respectively.
2. electromagnetic environment according to claim 1 is simulated the system that intensive stream of pulses produces, and it is characterized in that:
Described first memory and second memory are selected the IDT70V7519 model.
3. electromagnetic environment according to claim 1 is simulated the system that intensive stream of pulses produces, and it is characterized in that:
Described FPGA module is selected XC3S2000 series.
4. electromagnetic environment according to claim 1 is simulated the system that intensive stream of pulses produces, and it is characterized in that:
What described PCI bridging chip adopted is the PCI9056 model.
5. electromagnetic environment according to claim 1 is simulated the system that intensive stream of pulses produces, and it is characterized in that:
What described pci bus adopted is the 32bit/33MHz pci bus.
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| CN 201220572084 CN202870294U (en) | 2012-10-31 | 2012-10-31 | Electromagnetic environment simulation intensive pulse flow generation system |
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| CN 201220572084 CN202870294U (en) | 2012-10-31 | 2012-10-31 | Electromagnetic environment simulation intensive pulse flow generation system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106772239A (en) * | 2017-02-20 | 2017-05-31 | 上海微小卫星工程中心 | Rotate the simulation source test system and its application method of baseline interferometer alignment system |
| CN106842137A (en) * | 2016-12-30 | 2017-06-13 | 北京华力创通科技股份有限公司 | A kind of radar signal generation method and device |
| CN111025239A (en) * | 2019-12-26 | 2020-04-17 | 南京国立电子科技有限公司 | Pulse transmitting method, device, storage medium and pulse transmitting equipment |
| CN112769417A (en) * | 2019-11-01 | 2021-05-07 | 雅特力科技(重庆)有限公司 | Clock fault detector |
-
2012
- 2012-10-31 CN CN 201220572084 patent/CN202870294U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106842137A (en) * | 2016-12-30 | 2017-06-13 | 北京华力创通科技股份有限公司 | A kind of radar signal generation method and device |
| CN106772239A (en) * | 2017-02-20 | 2017-05-31 | 上海微小卫星工程中心 | Rotate the simulation source test system and its application method of baseline interferometer alignment system |
| CN106772239B (en) * | 2017-02-20 | 2019-04-02 | 上海微小卫星工程中心 | Rotate the simulation source test macro and its application method of baseline interferometer positioning system |
| CN112769417A (en) * | 2019-11-01 | 2021-05-07 | 雅特力科技(重庆)有限公司 | Clock fault detector |
| CN112769417B (en) * | 2019-11-01 | 2022-05-20 | 雅特力科技(重庆)有限公司 | Clock fault detector |
| CN111025239A (en) * | 2019-12-26 | 2020-04-17 | 南京国立电子科技有限公司 | Pulse transmitting method, device, storage medium and pulse transmitting equipment |
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Granted publication date: 20130410 Termination date: 20181031 |
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| CF01 | Termination of patent right due to non-payment of annual fee |