CN202839611U - Semiconductor device having electrostatic discharge protection module - Google Patents
Semiconductor device having electrostatic discharge protection module Download PDFInfo
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- CN202839611U CN202839611U CN 201220521400 CN201220521400U CN202839611U CN 202839611 U CN202839611 U CN 202839611U CN 201220521400 CN201220521400 CN 201220521400 CN 201220521400 U CN201220521400 U CN 201220521400U CN 202839611 U CN202839611 U CN 202839611U
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Abstract
A semiconductor device having an electrostatic discharge protection module is provided. According to the embodiment of the present invention, the esd protection module is in a pie shape, and includes a central doped region of the first conductivity type and a plurality of second conductivity type doped regions and first conductivity type doped regions alternately arranged around the central doped region, the central doped region is filled with the lower portion of the whole gate metal pad portion of the semiconductor transistor and coupled thereto, and the source metal of the semiconductor transistor is coupled to the first conductivity type doped region on the outermost periphery in the esd protection module. The electrostatic discharge protection module can protect the gate oxide layer of the semiconductor transistor from being damaged by electrostatic discharge, and has smaller series resistance and improved current balance.
Description
Technical field
Embodiment of the present utility model relates to semiconductor device, relates in particular to the semiconductor device with electrostatic protection module.
Background technology
The semiconductor device such as mos field effect transistor (MOSFET), junction field effect transistor (JFET) and double-diffused metal oxide semiconductor field-effect transistor (DMOS) are widely used in electronic industry.For several simple examples, these semiconductor device can be used in power amplifier and the low noise amplifier, also can be used as power switch pipe and are used for circuit for power conversion.For job stability and the fail safe that improves these semiconductor device, usually need to provide static discharge (ESD) protection module for it.
Take DMOS when the power switch pipe as example, in the transient changing process that DMOS turn-offs, since the grid that puts on DMOS that static discharge (ESD) produces and the voltage between the source electrode may moment up to more than 10000 volts, and cause the gate oxide of DMOS to damage.This will cause having used the electronic product cisco unity malfunction of this DMOS.Usually; in order to prevent that ESD is to the infringement of the gate oxide of the semiconductor device such as DMOS; can between the grid of the semiconductor device such as DMOS and source electrode, couple static discharge (ESD) protection module; (for example be higher than certain value with the voltage that produces at static discharge (ESD); this value can be set as the breakdown voltage value of the gate oxide that is lower than DMOS) time make this esd protection module conducting, thereby provide path for the energy of ESD discharges.This esd protection module can be discrete, also can be integrated in the semiconductor device.In order to reduce product size and production cost, the esd protection module integration has been become a kind of trend in semiconductor device.
Typically, the esd protection module can comprise the PN diode of one group of series connection.These PN diodes can be by being manufactured with for example depositing polysilicon layer on the substrate surface of MOSFET itself of semiconductor device, then this polysilicon layer etching is preserved for making the part of PN diode group, the polysilicon layer that will keep again mixes and forms the P type of alternative arrangement and N-type doped region and form.The PN diode group of this series connection is coupled between the source electrode metal of MOSFET and the gate electrode metal thinks that the gate oxide of MOSFET provides esd protection.Yet the series resistance of these PN diodes and electric current uniformity are the key factors that affects its esd protection performance.Series resistance is less, and the electric current uniformity is better, and the esd protection performance that it can provide is higher.
Thereby a kind of semiconductor device that is integrated with the esd protection module wish to be proposed, make this esd protection module have less resistance and electric current uniformity preferably, thereby provide better esd protection for this semiconductor device.
The utility model content
For one or more problems of the prior art, embodiment of the present utility model provides a kind of semiconductor device that includes the esd protection module.
Aspect one of the present utility model, a kind of semiconductor device has been proposed, this semiconductor device can comprise: Semiconductor substrate, have the first conduction type, comprise effective unit area and fringe region; Semiconductor transistor is formed in effective unit area of described Semiconductor substrate, and wherein said semiconductor transistor comprises drain region, grid region and source region; Couple the gate metal and the source metal that couples described source region in described grid region; And electrostatic discharge (ESD) protection module, be formed at the fringe region top of described Semiconductor substrate, comprise electrostatic discharge (ESD) protection layer and the first separator, wherein said the first separator is between described Semiconductor substrate and described electrostatic discharge (ESD) protection layer, with described electrostatic discharge (ESD) protection layer and the isolation of described Semiconductor substrate; Wherein, described source metal is positioned at top, described effective unit area, described gate metal is positioned at described fringe region top, has external series gap between described source metal and the described gate metal, and wherein said gate metal has gate metal pad portion and gate metal cabling part; Described electrostatic discharge (ESD) protection layer is pie, comprise the center doped region of the first conduction type and a plurality of the second conduction type doped regions and the first conduction type doped region of alternately arranging around this center doped region, wherein said the second conduction type and described the first conductivity type opposite, described center doped region is covered with in fact the below of whole described gate metal pad portion; And described gate metal pad portion couples the center doped region of described electrostatic discharge (ESD) protection layer, and described source metal couples the first conduction type doped region of outermost in the described electrostatic discharge (ESD) protection layer.
According to embodiment of the present utility model; the described electrostatic discharge (ESD) protection layer of this semiconductor device may further include: the suspension doped region with described second conduction type; periphery around described a plurality of the second conduction type doped regions of alternately arranging and the first conduction type doped region forms, and this suspension doped region electricity suspends.
According to embodiment of the present utility model, the described gate metal pad portion of this semiconductor device dents in the described source metal, forms the gate metal neck that connects this gate metal pad portion and gate metal cabling part between described gate metal pad portion and described gate metal cabling part; Described source metal has source metal and refers to, extends to the both sides of described gate metal neck, with the described gate metal pad portion of ring bag.
According to embodiment of the present utility model, in this semiconductor device, the center doped region of described first conduction type of described electrostatic discharge (ESD) protection layer and have heavier doping content around other the first conduction type doped region of this center doped region.
According to embodiment of the present utility model, this semiconductor device may further include interlayer dielectric layer, this interlayer dielectric layer covers described electrostatic discharge (ESD) protection layer and described Semiconductor substrate, and described gate metal and described source metal are separated with described electrostatic discharge (ESD) protection layer and described Semiconductor substrate; Described center doped region couples by the first through hole and the described gate metal pad portion that is formed in the described interlayer dielectric layer; The first conduction type doped region of outermost couples by the second through hole and the described source metal that is formed in the described interlayer dielectric layer in the described electrostatic discharge (ESD) protection layer.
According to embodiment of the present utility model, in this semiconductor device, described semiconductor transistor can comprise the vertical-type trench gate metal oxide semiconductor field effect transistor.
Description of drawings
Below accompanying drawing help to understand better next description to the different embodiment of the utility model.These accompanying drawings are not feature, size and the scale according to reality, but schematically show the principal character of some execution modes of the utility model.These drawings and embodiments provide embodiment more of the present utility model in the mode of non-limiting, non exhaustive property.For simplicity's sake, the identical or similar assembly or the structure that have identical function in the different accompanying drawings adopt identical Reference numeral.
Fig. 1 shows the longitudinal profile schematic diagram according to the semiconductor device 100 of an embodiment of the utility model;
Fig. 2 shows the plane schematic top plan view corresponding to semiconductor device shown in Fig. 1 100 according to an embodiment of the utility model;
Fig. 3 shows according to the plane of the esd protection layer 109 of an embodiment of the utility model schematic diagram of arranging;
Fig. 4 shows the gate metal pad portion 107 corresponding to Fig. 2
1Floor map is amplified near part;
Fig. 5 A-5I shows the manufacture process longitudinal profile schematic diagram that has the semiconductor device 100 of esd protection module according to the manufacturing of an embodiment of the utility model;
Fig. 6 A-6H shows the manufacture process longitudinal profile schematic diagram that has the semiconductor device 100 of esd protection module according to the manufacturing of another embodiment of the utility model.
Embodiment
The below will describe embodiment more of the present utility model in detail.In ensuing explanation, some concrete details, for example the design parameter of the particular circuit configurations among the embodiment, device architecture, processing step and these circuit, device and technique all is used for providing better understanding to embodiment of the present utility model.Even those skilled in the art be appreciated that lack some details or with the situation of the combinations such as additive method, element, material under, embodiment of the present utility model also can be implemented.
In specification of the present utility model and claims, if adopted such as " left and right, inside and outside, forward and backward, upper and lower, top, on, the end, under " etc. the word of a class, all just for convenience of description, the inevitable or permanent relative position that does not represent assembly/structure.It should be appreciated by those skilled in the art that this class word can exchange in suitable situation, for example, so that embodiment of the present utility model can still can operate being different under the direction that this specification describes.In addition, " couple " word mean with direct or indirectly electric or non-electric mode connect." one/this/that " also is not used in and refers in particular to odd number, and may contain plural form." ... interior " may contain " ... interior/on ".The usage of " in one embodiment/according to an embodiment of the present utility model " and being not used in is refered in particular among the same embodiment, also may be among the same embodiment certainly.Unless otherwise indicated, "or" can contain " and/or " the meaning.If the embodiment of " transistor " can comprise " field-effect transistor " or " bipolar junction transistor ", then " grid/grid region ", " source electrode/source region ", " drain electrode/drain region " can comprise respectively " base stage/base ", " emitter/emitter region ", " collector electrode/collector region ", and vice versa.Those skilled in the art should understand that above explanation to each word only provides some exemplary usages, and be not used in these words of restriction.
Fig. 1 shows the longitudinal profile schematic diagram according to the semiconductor device 100 of an embodiment of the utility model.Fig. 2 shows the plane schematic top plan view corresponding to semiconductor device shown in Fig. 1 100 according to an embodiment of the utility model.Need to prove, Fig. 2 has illustrated the top plan view (mainly having illustrated the metal level of wafer and the polysilicon layer of ESD module) of the whole wafer of semiconductor device 100, Fig. 1 only is the cut-away section schematic diagram of device cell in the whole wafer, and for example the right side is divided with the longitudinal profile schematic diagram shown in the left part and corresponded respectively to the part shown in the AA ' and BB ' hatching among Fig. 2 among Fig. 1.Below in conjunction with Fig. 1 and Fig. 2 the semiconductor device 100 according to the utility model embodiment is described.
According to an embodiment of the present utility model, semiconductor device 100 comprises semiconductor transistor 101 (shown in Fig. 1 right side is divided, being illustrated as MOSFET) and static discharge (ESD) protection module 102 (shown in Fig. 1 left part).In exemplary embodiment shown in Figure 1, this semiconductor device 100 has substrate 103, and this substrate 103 has the first conduction type (for example: be illustrated as N-type among Fig. 1), and may comprise heavy doping substrate part 103
1(for example be illustrated as N among Fig. 1
+Type heavy doping substrate partly) and light dope epitaxial loayer part 103
2(for example be illustrated as N among Fig. 1
-Type light dope epitaxial loayer part).This substrate 103 can be divided into effective unit area and fringe region (referring to the signal of Fig. 2).Semiconductor transistor 101 (for example MOSFET) is formed in described effective unit area, and esd protection module 102 is formed in the described fringe region.
According to an embodiment of the present utility model, semiconductor transistor 101 (being illustrated as MOSFET among Fig. 1) can comprise drain region (103), grid region 105, source region 106 and couple the gate metal 107 in described grid region 105 and couple the source metal 108 in described source region 106.In the exemplary embodiment shown in Fig. 1, the heavy doping substrate part 103 of substrate 103
1Can be used as the drain region of semiconductor transistor 101 (for example MOSFET).
According to an embodiment of the present utility model, semiconductor transistor 101 (for example MOSFET) can further include the tagma 104 that is formed on the substrate 103, has the second conduction type (for example: be illustrated as the P type among Fig. 1) with described the first conductivity type opposite.Those of ordinary skill in the art is to be understood that tagma 104 can be by in substrate 103 (the epitaxial loayer part 103 of substrate 103
2) in inject the ion with described second conduction type and form, tagma 104 has relatively light doping content usually.
In the exemplary embodiment shown in Fig. 1, grid region 105 comprises groove-shaped grid 105
1With gate oxide 105
2Groove-shaped grid 105
1Be positioned at gate groove 105
3In, wherein gate groove 105
3 Pass tagma 104 from the surface longitudinal of substrate 103 and extend to epitaxial loayer 103
2In.Gate oxide 105
2Be covered with gate groove 105
3Sidewall and bottom surface, with groove-shaped grid 105
1Keep apart with substrate 103 and tagma 104.In the exemplary embodiment shown in Fig. 1, source region 106 be formed at grid region 105 around, have described the first conduction type and (for example: be illustrated as N among Fig. 1 have heavier doping content
+The district).According to an embodiment of the present utility model, grid region 105 is by grid contact trench 105
TCouple with described gate metal 107.With gate groove 105
3Similar, grid contact trench 105
TIn be filled with electric conducting material 105
C, grid contact trench 105
TSidewall and bottom surface be coated with separator 105
D, with electric conducting material 105
CKeep apart with on every side substrate 103 and tagma 104.Grid contact trench 105
TGenerally than gate groove 105
3Wide, contact with gate metal 107 being easy to.Herein, widely refer to weigh from the direction of the bottom surface tangent line L that is parallel to substrate 103.Grid contact trench 105
TThe electric conducting material 105 of middle filling
CCan with form groove-shaped grid 105
1Material identical, for example be the polysilicon of doping, also can with form groove-shaped grid 105
1Material different.Separator 105
DCan adopt and gate oxide 105
2Identical dielectric material for example is Si oxide, also can adopt and gate oxide 105
2Different dielectric materials.Grid contact trench 105
TWith gate groove 105
3Be interconnective, for example interconnect by horizontal connection groove (not shown in figure 1).As shown in Figure 1, refer to laterally that herein connecting groove can form in the direction of the bottom surface tangent line L that is parallel to substrate 103.According to embodiment of the present utility model, connect groove structure can with grid contact trench 105
TPerhaps gate groove 105
3Identical, for example connect groove can with grid contact trench 105
TBe filled with identical electric conducting material 105
CAnd have identical bottom surface and a sidewall spacers 105
D, perhaps connect groove can with gate groove 105
3Be filled with the groove-shaped grid 105 of identical formation
1Material and have identical bottom surface and sidewall gate oxide 105
2Will be understood by those skilled in the art that, among Fig. 1 for grid region 105 and grid contact trench 105
TAll be schematically etc. the expression of relevant grid structure, the corresponding relation of section peace face of Fig. 1 and Fig. 2 also is schematically, and is not used in the utility model is carried out accurately concrete restriction.In fact, gate groove 105
3And grid contact trench 105
TStructure and arrangement mode and the interconnected relationship between them be not limited to shown in Figure 1 and above described based on Fig. 1.
In exemplary embodiment illustrated in figures 1 and 2, source metal 108 is positioned at the top, effective unit area of described substrate 103, and gate metal 107 is positioned at the fringe region top of described substrate 103.Have external series gap between source metal 108 and the gate metal 107, wherein gate metal 107 has gate metal pad portion 107
1With gate metal cabling part 107
2(referring to the plan view from above of Fig. 2 signal).In the exemplary embodiment of Fig. 2 signal, gate metal 107 forms around this source metal 108, and source metal 108 is surrounded.In a further embodiment, gate metal 107 might not surround source metal 108 fully.
According to an exemplary embodiment of the present utility model, static discharge (ESD) protection module 102 can comprise esd protection layer 109, is positioned at the fringe region top of substrate 103; And first separator 110, with described esd protection layer 109 and substrate 103 isolation.According to an exemplary embodiment of the present utility model, esd protection layer 109 comprises polysilicon layer, has the first conduction type doped region 109 of alternately arranging
1(be illustrated as N among Fig. 1
+The type doped region) and the second conduction type doped region 109
2(being illustrated as P type doped region among Fig. 1).According to different embodiment of the present utility model, esd protection layer 109 also can comprise and device fabrication compatible other semiconductor material layer mutually.Therefore, here " polysilicon " means semi-conducting material and the composition thereof of having contained other the similar silicon beyond silicon and the silica removal.
According to an exemplary embodiment of the present utility model, esd protection layer 109 is pie, comprises the center doped region 109 with described first conduction type
1(be illustrated as N among Fig. 1
+The type doped region) with around this center doped region 109
1A plurality of second conduction type doped regions 109 of alternately arranging
2(being illustrated as P type doped region among Fig. 1) and the first conduction type doped region 109
1(be illustrated as N among Fig. 1
+The type doped region), center doped region 109
1Basically be covered with whole described gate metal pad portion 107
1The below.Described gate metal pad portion 107
1Couple the center doped region 109 of described esd protection layer 109
1, described source metal 108 couples the first conduction type doped region 109 of outermost in the described esd protection layer 109
1(that is: described a plurality of the second conduction type doped region 109
2With the first conduction type doped region 109
1The described center of middle distance doped region 109
1The first conduction type doped region 109 farthest
1).Esd protection module 102 is coupled between the gate metal 107 (or grid region 105) and source metal 108 (or source region 106) of semiconductor transistor (for example MOSFET) 101 like this, because esd protection module 102 comprises that the PN diode of a plurality of coupled in series that are formed in the esd protection layer 109 is (by the doped region 109 of alternately arranging
1With 109
2Form); thereby can be when the voltage that produces because of static discharge (ESD) be higher than the esd protection threshold value; make the PN diode current flow (being 102 conductings of esd protection module) of these a plurality of coupled in series, thus the gate oxide 105 of protection semiconductor transistor (for example MOSFET) 101
2Be without prejudice.According to an exemplary embodiment of the present utility model, described esd protection threshold value can be set as the gate oxide 105 that is lower than semiconductor transistor (for example MOSFET) 101
2Breakdown voltage value.According to embodiment of the present utility model, can be by changing in the esd protection layer 109 around center doped region 109
1Described a plurality of second conduction type doped regions 109 of alternately arranging
2With the first conduction type doped region 109
1Number described esd protection threshold value is arranged.Therefore, " a plurality of " here and being not used in refer in particular to more than one, but can comprise one.
According to an exemplary embodiment of the present utility model, the center doped region 109 of described the first conduction type
1With around this center doped region 109
1Other the first conduction type doped region 109
1Have heavier doping content, can reduce like this series resistance (namely being formed at the series resistance of the PN diode of a plurality of coupled in series in the esd protection layer 109) of esd protection module 102.In addition, according to embodiment of the present utility model, center doped region 109
1Basically be covered with whole gate metal pad portion 107
1The below, have relatively large area, can further reduce the series resistance of esd protection module 102, increase simultaneously the current balance of esd protection module 102, and centered by doped region 109
1With gate metal pad portion 107
1Between but larger contact area is provided, help to reduce the gate metal 107 of semiconductor transistor (for example MOSFET) 101 and the metal/semiconductor contact resistance between the esd protection module 102.
The plane that Fig. 3 shows esd protection layer 109 schematic diagram of arranging.Although among Fig. 3 esd protection layer 109 is illustrated as round and smooth rectangular-shaped; yet will be understood by those skilled in the art that; in other embodiments; esd protection layer 109 might not be the rectangle pie; and can be any other close-shaped cake, such as cake, oval cake, have the polygon cake at round and smooth angle etc.Therefore, " pie " is descriptive, do not express or hints that esd protection layer 109 necessarily has the cake shape.
According to an exemplary embodiment of the present utility model, esd protection layer 109 can further include the suspension doped region 109 with described second conduction type
3, around described a plurality of the second conduction type doped regions 109 of alternately arranging
2With the first conduction type doped region 109
1The periphery form.This suspension doped region 109
3Have relatively light doping content and (for example can have the doped region 109 with described the first conduction type
1Identical doping content also can be than doped region 109
1Doping content less, be illustrated as P among Fig. 1
-Distinguish), and (for example: this suspension doped region 109 do not have a mind to couple any electromotive force
3Source electrode, gate electrode and the drain electrode etc. with semiconductor transistor 101 do not couple, and namely it has the suspension electromotive force, is in electric suspended state).Suspension doped region 109
3Formed the protection potential barrier in electrostatic discharge (ESD) protection module 102 peripheries; help to intercept the charge carrier that derives from esd protection module 102 outsides and enter this esd protection module 102; thereby the infringement of protecting this esd protection module 102 not invaded by outside charge carrier has improved its performance.
According to an exemplary embodiment of the present utility model; semiconductor device 100 can further include interlayer dielectric layer (ILD) 111; cover esd protection layer 109 and Semiconductor substrate 103, be used for preventing short circuit between source metal 108 and the grid region 105 and the short circuit between gate metal 107 and the source region 106.According to an embodiment of the present utility model, the center doped region 109 of esd protection layer 109
1By being formed at the first through hole 111 in the interlayer dielectric layer 111
1With gate metal pad portion 107
1Couple.Similarly, the first conduction type doped region 109 of outermost in the esd protection layer 109
1By being formed at the second through hole 111 in the interlayer dielectric layer 111
2Couple with described source metal 108.Will be understood by those skilled in the art that, here the first mentioned through hole 111
1With the second through hole 111
2And be not used in to refer in particular to and only have " one ", but can contain the meaning of " a plurality of ".For example, according to an exemplary embodiment of the present utility model, described the first through hole 111
1Comprise a plurality of through holes, be covered with the described center of being positioned at of described interlayer dielectric layer 111 doped region 109
1The part of top.The embodiment other according to the utility model, described the first through hole 111
1Also can be a larger through hole, occupy the described center of being positioned at of described interlayer dielectric layer 111 doped region 109
1The part of top.
Fig. 4 shows the gate metal pad portion 107 corresponding to Fig. 2
1Floor map is amplified near part.According to an exemplary embodiment of the present utility model, referring to Fig. 4, gate metal pad portion 107
1Dent in the source metal 108, by source metal 108 ring bags, in gate metal pad portion 107
1With gate metal cabling part 107
2Between form relatively thin gate metal neck 107
3, will be by the metal pad part 107 of source metal 108 ring bags
1With gate metal cabling part 107
2Be connected.Correspondingly, 108 of source metals have source metal and refer to 108
1, extend to gate metal neck 107
3Both sides near, with ring bag gate metal pad portion 107
1Source metal refers to 108 like this
1Part also can be coupled to the first conduction type doped region 109 of outermost in the described esd protection layer 109
1But increased the contact area between source metal 108 and the esd protection layer 109; thereby help further to reduce the series resistance of esd protection module 102 and the metal/semiconductor contact resistance between esd protection module 102 and the source metal 108, improve the current balance of esd protection module 102.
More than based on Fig. 1 to Fig. 4 the semiconductor device 100 according to each embodiment of the utility model is illustrated, although in the above description, semiconductor device 100 exemplarily comprises vertical-type trench gate mosfet 101, and is integrated with esd protection module 102.Yet above-mentioned exemplary illustration and being not used in to each embodiment of the utility model limits the utility model; according to variant embodiment of the present utility model and execution mode; semiconductor spare 100 also may comprise the semiconductor transistor 101 of other type, replaces MOSFET 101 and described esd protection module 102 among aforementioned each embodiment integrated such as double-diffused metal oxide semiconductor field-effect transistor (DMOS), bipolar junction transistor (BJT) etc.And semiconductor transistor 101 not only is confined to vertical-type trench-gate transistors described above, also can be lateral transistor and planar gate transistor.
The beneficial effect of power device according to each embodiment of the utility model and distortion execution mode thereof should not be considered to only be confined to above-described.Can be better understood by the accompanying drawing of reading detailed description of the present utility model and studying each embodiment according to these and other beneficial effect of each embodiment of the utility model.
Fig. 5 A-5I shows the manufacture process longitudinal profile schematic diagram that has the semiconductor device 100 of esd protection module according to the manufacturing of an embodiment of the utility model.
At first, shown in Fig. 5 A, provide have the first conduction type Semiconductor substrate 103 of (for example: be illustrated as N-type among Fig. 5 A).According to an exemplary embodiment of the present utility model, this Semiconductor substrate 103 may comprise heavy doping substrate part 103
1(for example be illustrated as N among Fig. 5 A
+Type heavy doping substrate partly) and light dope epitaxial loayer part 103
2(for example be illustrated as N among Fig. 5 A
-Type light dope epitaxial loayer part).This Semiconductor substrate 103 can be divided into effective unit area and fringe region (referring to the signal of Fig. 2).Need to prove that among Fig. 5 A to Fig. 5 I, the left side has illustrated the cut-away section schematic diagram that is formed with esd protection module 102 of described fringe region, the right side has illustrated the cut-away section schematic diagram that is formed with MOSFET101 of described effective unit area.
Next, shown in Fig. 5 B, in effective unit area of Semiconductor substrate 103, form grid region 105.According to an exemplary embodiment of the present utility model, described grid region 105 comprises groove-shaped grid 105
1With gate oxide 105
2The step that forms this grid region 105 can comprise: form gate groove 105 in effective unit area of Semiconductor substrate 103
3At described gate groove 105
3The bottom and sidewall on form to cover the gate oxide 105 of its bottom and sidewall
2And adopt electric conducting material to fill described gate groove 105
3Thereby form groove-shaped grid 105
1According to an exemplary embodiment of the present utility model, described gate oxide 105
2Can comprise silicon dioxide layer.According to an exemplary embodiment of the present utility model, described electric conducting material can comprise the polysilicon of doping.According to embodiment of the present utility model, when forming groove-shaped grid region 105, in the fringe region of Semiconductor substrate 103, form grid contact trench 105
T, at described grid contact trench 105
TThe bottom and sidewall on form to cover the separator 105 of its bottom and sidewall
DAnd employing electric conducting material 105
CFill described grid contact trench 105
TAccording to embodiment of the present utility model, forming groove-shaped grid region 105 and grid contact trench 105
TThe time, also form connection groove (not shown among Fig. 5 B), with described gate groove 105
3With described grid contact trench 105
TTransversely link.Described connection groove has and described gate groove 105
3Or described grid contact trench 105
TIdentical structure.
Next step, shown in Fig. 5 C, in Semiconductor substrate 103, carry out the tagma Implantation, form the tagma ion doped layer 104d (being illustrated as P type doped layer among Fig. 5 C) with second conduction type, described the second conduction type and described the first conductivity type opposite.Will be understood by those skilled in the art that the tagma Implantation shown in Fig. 5 C is to grid 105
1Impact very little, can ignore.Those of ordinary skill in the art also should be appreciated that, in the process of carrying out the processing steps such as Implantation, ion diffusion, and groove-shaped grid 105
1Usually can be oxidized and form thin oxide layer with groove-shaped grid 105 on its surface
1Be closed in gate groove 105
3In (such as Fig. 5 C signal).In fact, those of ordinary skill in the art be also to be understood that in the process of carrying out the processing steps such as Implantation, ion diffusion, and the surface of Semiconductor substrate 103 usually also can be oxidized and grow thin conductor oxidate layer, for simplicity's sake, not signal among Fig. 5 C.
Then, shown in Fig. 5 D, at upper formation first separator 110 of described Semiconductor substrate 103, and on this first separator 110 deposit ESD polysilicon layer 109.
Then, shown in Fig. 5 E, in this ESD polysilicon layer, have the ESD Implantation of described the second conduction type, form the ESD ion doped layer 109d with described second conduction type.
Next, shown in Fig. 5 F, at first for example by annealing, carry out the ion propulsion diffusion, thereby make ion doped layer 104d diffusion in tagma in substrate 103, form tagma 104, and make the ion among the ESD ion doped layer 109d diffuse to whole polysilicon layer 109, thereby make polysilicon layer 109 have described the second conduction type.
Then; shown in Fig. 5 G; the part that is used to form ESD module 102 that adopts the ESD mask layer to shelter polysilicon layer 109; and with all the other not masked portion etch away; then remove the ESD mask layer; thereby above the fringe region of substrate 103, form esd protection module basis layer (the first separator 110 and polysilicon layer 109 after comprising etching), make it be pie.
Next, shown in Fig. 5 H, adopt source region ion implantation mask layer to shelter, the Implantation that in described Semiconductor substrate 103 and described polysilicon layer 109, has the first conduction type, so that form source region 106 in the tagma 104 of effective unit area of described Semiconductor substrate 103, and make described polysilicon layer 109 have the center doped region 109 of the first conduction type
1With around this center doped region 109
1A plurality of second conduction type doped regions 109 of alternately arranging
2With the first conduction type doped region 109
1Will be understood by those skilled in the art that, also comprise the step of removing source region ion implantation mask layer and carrying out the ion diffusion here.
Next, shown in Fig. 5 I, form the second separator 111 at polysilicon layer 109 and substrate 103, and in this second separator 111, form the first through hole 111
1With the second through hole 111
2, wherein said the first through hole 111
1Be positioned at the center doped region 109 of described polysilicon layer 109
1The top, described the second through hole 111
2Be positioned at the first conduction type doped region 109 of the outermost of described polysilicon layer 109
1The top.Then, form gate metal 107 and source metal 108 at the second separator 111, make described gate metal 107 be positioned at described fringe region top, described source metal 108 is positioned at top, described effective unit area, have external series gap between described gate metal 107 and the described source metal 108, wherein said gate metal 107 has gate metal pad portion 107
1With gate metal cabling part 107
2(referring to Fig. 2), described gate metal pad portion 107
1Be positioned at the center doped region 109 of described polysilicon layer 109
1The top covers whole described center doped region 109 basically
1And by described the first through hole 111
1Couple described center doped region 109
1, described source metal 108 is by described the second through hole 111
2Couple the first conduction type doped region 109 of outermost in the described polysilicon layer 109
1
According to an embodiment of the present utility model, in the step shown in Fig. 5 H, carried out having the Implantation of the first conduction type after, also make described polysilicon layer 109 have the suspension doped region 109 of described the second conduction type
3, be positioned at described a plurality of the second conduction type doped regions of alternately arranging and the periphery of the first conduction type doped region, this suspension doped region 109
3Do not have a mind to couple any electromotive force.
According to an embodiment of the present utility model, in step 5I, when forming gate metal 107 and source metal 108, also comprise making described gate metal pad portion 107
1Dent in the described source metal 108, in described gate metal pad portion 107
1With described gate metal cabling part 107
2Between form to connect this gate metal pad portion 107
1With gate metal cabling part 107
2Gate metal neck 107
3And at described gate metal neck 107
3Both sides form source metal and refer to 108
1, so that the described gate metal pad portion 107 of described source metal 108 ring bags
1(referring to Fig. 4).
More than the manufacturing integration according to the utility model embodiment is had the explanation of manufacture process of the semiconductor device 100 of semiconductor transistor 101 and esd protection module 102 based on Fig. 5 A-5I, and be not used in the utility model be limited in as described above in each embodiment.The manufacture process of describing based on Fig. 5 A-5I is changed and revises all is possible.
For example, Fig. 6 A-6H shows the manufacture process longitudinal profile schematic diagram that has the semiconductor device 100 of esd protection module according to the manufacturing of a variant embodiment of the utility model.Embodiment according to this distortion, in the step shown in Fig. 5 A and the 5B (referring to Fig. 6 A and Fig. 6 B) afterwards, the step of carrying out the tagma Implantation in Semiconductor substrate 103 shown in Fig. 5 C can be omitted, and and then carries out formation the first separator 110 shown in Fig. 5 D and the step (referring to Fig. 6 C) of ESD polysilicon layer 109.Then, the step shown in Fig. 5 E to Fig. 5 I is carried out following adjustment: after the step shown in Fig. 5 D, carry out the step shown in Fig. 5 G, form the first separator 110 and the polysilicon layer 109 (referring to Fig. 6 D) of pie; After the step shown in Fig. 5 G, carry out the step shown in Fig. 5 E and Fig. 5 F (referring to Fig. 6 E and Fig. 6 F); After the step shown in Fig. 5 F, carry out the step shown in Fig. 5 H and Fig. 5 I (referring to Fig. 6 G and Fig. 6 H).In the exemplary embodiment of this distortion, before carrying out the step shown in Fig. 5 E, first the first separator 110 and ESD polysilicon layer 109 have been carried out the etch step shown in Fig. 5 G, thereby do not injected the ESD ion of the second conduction type in the substrate 103 that is covered by the first separator 110 and ESD polysilicon layer 109 after the etching yet, form tagma 104 (referring to Fig. 6 E and Fig. 6 F) through the diffusing step of Fig. 5 F.Can carry out separately the tagma Implantation like this, thereby simplify manufacturing step, also can save production cost simultaneously.
More than to according to each embodiment of the utility model and the distortion execution mode forms the manufacture process of semiconductor device and the description of method step only is exemplary, and be not used in and limit of the present utility model.In addition, some known manufacturing steps, technique, material and used impurity etc. do not provide or do not describe in detail so that the utility model is clear, simple and clear and be convenient to understand.Utility model person of ordinary skill in the field should be appreciated that, more than the method described among each embodiment and step may be able to adopt in differing order and realize, be not limited only to described embodiment.
Although in this specification as an example of the semiconductor device that is integrated with N raceway groove vertical-type trench gate mosfet and esd protection module example to illustrating according to the semiconductor device that is integrated with semiconductor transistor and esd protection module of each embodiment of the utility model and describing; but this does not also mean that restriction of the present utility model, will be understood by those skilled in the art that it is the P channel mosfet that structure given here and principle are equally applicable to semiconductor transistor integrated in this semiconductor device; N raceway groove/P raceway groove DMOS; transistor device and the semi-conducting material of other type and the situations of semiconductor device such as BJT.
Therefore, above-mentioned specification of the present utility model and execution mode only are illustrated the semiconductor device of the utility model embodiment in an exemplary fashion, and are not used in the scope of the present utility model that limits.It all is possible changing and revise for disclosed embodiment, the selectivity embodiment that other are feasible and can be understood by those skilled in the art the equivalent variations of element among the embodiment.Other variations of embodiment disclosed in the utility model and modification do not exceed spirit of the present utility model and protection range.
Claims (6)
1. semiconductor device comprises:
Semiconductor substrate has the first conduction type, comprises effective unit area and fringe region;
Semiconductor transistor is formed in effective unit area of described Semiconductor substrate, and wherein said semiconductor transistor comprises drain region, grid region and source region;
Couple the gate metal and the source metal that couples described source region in described grid region; With
The electrostatic discharge (ESD) protection module, be formed at the fringe region top of described Semiconductor substrate, comprise electrostatic discharge (ESD) protection layer and the first separator, wherein said the first separator is between described Semiconductor substrate and described electrostatic discharge (ESD) protection layer, with described electrostatic discharge (ESD) protection layer and the isolation of described Semiconductor substrate; It is characterized in that,
Described source metal is positioned at top, described effective unit area, described gate metal is positioned at described fringe region top, have external series gap between described source metal and the described gate metal, wherein said gate metal has gate metal pad portion and gate metal cabling part;
Described electrostatic discharge (ESD) protection layer is pie, comprise the center doped region of the first conduction type and a plurality of the second conduction type doped regions and the first conduction type doped region of alternately arranging around this center doped region, wherein said the second conduction type and described the first conductivity type opposite, described center doped region is covered with in fact the below of whole described gate metal pad portion; And
Described gate metal pad portion couples the center doped region of described electrostatic discharge (ESD) protection layer, and described source metal couples the first conduction type doped region of outermost in the described electrostatic discharge (ESD) protection layer.
2. semiconductor device as claimed in claim 1 is characterized in that, described electrostatic discharge (ESD) protection layer further comprises:
Suspension doped region with described second conduction type, around the periphery formation of described a plurality of the second conduction type doped regions of alternately arranging and the first conduction type doped region, this suspension doped region electricity suspends.
3. semiconductor device as claimed in claim 1 is characterized in that:
Described gate metal pad portion dents in the described source metal, forms the gate metal neck that connects this gate metal pad portion and gate metal cabling part between described gate metal pad portion and described gate metal cabling part;
Described source metal has source metal and refers to, extends to the both sides of described gate metal neck, with the described gate metal pad portion of ring bag.
4. semiconductor device as claimed in claim 1 is characterized in that, the center doped region of described the first conduction type and have heavier doping content around other the first conduction type doped region of this center doped region.
5. semiconductor device as claimed in claim 1, it is characterized in that, further comprise interlayer dielectric layer, cover described electrostatic discharge (ESD) protection layer and described Semiconductor substrate, described gate metal and described source metal are separated with described electrostatic discharge (ESD) protection layer and described Semiconductor substrate; Described center doped region couples by the first through hole and the described gate metal pad portion that is formed in the described interlayer dielectric layer; The first conduction type doped region of outermost couples by the second through hole and the described source metal that is formed in the described interlayer dielectric layer in the described electrostatic discharge (ESD) protection layer.
6. semiconductor device as claimed in claim 1 is characterized in that, described semiconductor transistor comprises the vertical-type trench gate metal oxide semiconductor field effect transistor.
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|---|---|---|---|
| CN 201220521400 CN202839611U (en) | 2012-10-12 | 2012-10-12 | Semiconductor device having electrostatic discharge protection module |
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|---|---|---|---|
| CN 201220521400 CN202839611U (en) | 2012-10-12 | 2012-10-12 | Semiconductor device having electrostatic discharge protection module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891143A (en) * | 2012-10-12 | 2013-01-23 | 成都芯源***有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891143A (en) * | 2012-10-12 | 2013-01-23 | 成都芯源***有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
| CN102891143B (en) * | 2012-10-12 | 2015-09-09 | 成都芯源***有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
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