CN202838922U - FPGA (Field Programmable Gate Array) based flat panel display driving apparatus - Google Patents
FPGA (Field Programmable Gate Array) based flat panel display driving apparatus Download PDFInfo
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- CN202838922U CN202838922U CN 201220167549 CN201220167549U CN202838922U CN 202838922 U CN202838922 U CN 202838922U CN 201220167549 CN201220167549 CN 201220167549 CN 201220167549 U CN201220167549 U CN 201220167549U CN 202838922 U CN202838922 U CN 202838922U
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Abstract
The utility model discloses a FPGA based flat panel display driving apparatus, which comprises a core control module, a master control core processing unit, a phase-locked loop IP core module, a clock reference module, a memory IP core module, a storage module, a timing sequence generating module, a display screen, an SD card control module and an SD card module. The driving apparatus can control various external SDRAM and SPI interface memories; program control of a phase-locked loop can used to adapt to different speed requirements of flat panel displays with different resolutions; and a standard AMBA bus module expansively controls different external storage equipments, so that the driving apparatus can be flexibly embedded into other systems.
Description
Technical field
The utility model relates to a kind of dull and stereotyped explicit drive unit based on FPGA, be for flat-panel display device such as TFT LCD specifically, Oled etc. utilize core processing unit to transmit the Universal driving circuit that the demonstration data realize showing based on the flat-panel display device of FPGA image.
Background technology
Along with science and technology development with rapid changepl. never-ending changes and improvements, great revolution has also occured in display technique, particularly after the nineties in last century along with the sharp increase of technological breakthrough and the market demand. the flat panel display (FPD) take liquid crystal display (LCD) as representative emerges rapidly.People mainly concentrate on field-emission plane display (FED), plasma panel display (PDP), tft liquid crystal flat-panel monitor (TFT-LCD) and display of organic electroluminescence (OLED to the research of flat-panel display device at present.Wherein TFT-LCD is the display device of catching up with comprehensively and surpass CRT on the combination properties such as present brightness, contrast, power consumption, life-span, volume and weight.Its function admirable, large-scale production characteristic are good, and automaticity is high.The cost of raw material is cheap, and development space is wide, becomes rapidly the focus of people's research.TFT-LCD is just towards high resolving power, full color, thin type future development at present.Because flat-panel monitor has the series of advantages such as volume is little, lightweight, power consumptive province, radiation is little, Electro Magnetic Compatibility is good, present, the flat-panel monitor take LCD, PDP, FED, OLED and LCoS etc. as representative is a large amount of coming into the market.Their each tool advantages, its displaying principle also is not quite similar; But their display interface control circuit can be general, so just impelled the birth of flat pannel display interface control universal circuit.The flat pannel display interface control circuit has comprised demonstration data processing circuit, display-memory and control circuit and scanning sequence control circuit.
Control has multiple implementation to the Via Color TFT-LCD Digital Image Display both at home and abroad at present.
1) employing is based on the display card of PC or industrial computer
Employing drives control TFT-LCD and shows digital picture based on display card and the cpu data interface of PC or industrial computer.This scheme can be utilized the abundant software resource of PC, realize the high-quality image demonstration of expecting, but system cost is high, power consumption is large, volume is large, speed is slow, can't satisfy the requirement of embedded digital picture system, and this scheme generally is used for non-embedded large-scale instrument and equipment.
2) employing is with the microprocessor (MCU) of TFT-LCD interface
Employing need not consider to drive control TFT-LCD with the MCU of the TFT-LCD interface CPU as system, how only need to solve the Buffer output data, has greatly simplified the system difficulty.But MCU belongs to the task processor-intensive, poor arithmetic ability, and speed is slow, is not suitable for the application requirements of the intensive computing of embedded digital picture system.This scheme is multiplex in electronic consumer products, such as multimedia handset etc.In addition, with the MCU price of TFT-LCD interface generally more than hundred yuan, if this MCU is only used the overall system high cost as the driving governor of TFT-LCD.
3) adopt TFT-LCD to drive the control special chip
General integrated large capacity SRAM in this special chip, CPIJ just can drive control TFT-LCD demonstration digital picture as long as write view data according to the control sequential of chip, has simplified the system difficulty.But this chip price can't satisfy cheaply requirement of system generally more than hundred yuan, is only applicable to the insensitive top-grade instrument equipment of cost.
4) programmable logic device (PLD)+SRAM/DRAM
By external buffer memory, CPU and TFT LCD carry out data-interface.Data-interface work comprises the CPU output image data to memory buffer, and the view data of programmable logic device (PLD) read buffer memory and be input to TFT.LCD and show that both carry out simultaneously.Adopt SRAM or DRAM as external buffer memory, cost is lower, but SRAM and DRAM only have a reading-writing port, can't carry out simultaneously read-write operation, can only frequently switch reading-writing port, and complex time has reduced the reliability of system.Simultaneously, must adopt high-grade programmable logic device (PLD), improve overall cost.Adopt this scheme, generally reduce the overall system cost by reducing display quality of image.Therefore, this scheme is multiplex in to the less demanding occasion of display quality of image, is unsuitable for digital image system.
5) programmable logic device (PLD)+FIFO
FIFO has independently reading-writing port, can carry out simultaneously read-write operation.Adopt FIFO as external buffer memory, can avoid frequently switching reading-writing port, reduced the complexity of sequential.But, Universal FIFO (based on SRAM), price is very expensive, can't satisfy cheaply requirement of system.If can reduce the cost of FIFO, programmable logic device (PLD)+FIFO will be the highest a kind of scheme of cost performance.
FPGA (Field Programmable Gate Array) is field programmable gate array, at PAL, the programmable logic device (PLD) that grows up on the GAL basis, compare with in the past PAL or GAL device, FPGA's is larger, alternative tens even several thousand general purpose I C chips, become a kind of system-level parts.
Summary of the invention
For overcoming the deficiencies in the prior art, the purpose of this utility model is to provide that a kind of bandwidth is enough, information mutual communication, highly versatile, system cost is low, volume is little invention.
For achieving the above object, the utility model adopts following technical scheme:
A kind of flat pannel display drive unit based on FPGA, comprise kernel control module, master control core processing unit, phaselocked loop IP kernel module, clock reference module, memory I P core module, memory module, sequential generation module, display screen, SD card control module, SD card module
Described kernel control module is connected with master control core processing unit, memory I P core module, SD card control module respectively; The output terminal of described phaselocked loop IP kernel module is connected with the input end of clock reference module; The output terminal of described clock reference module is connected with the input end of kernel control module, memory I P core module, sequential generation module, display screen, SD card control module respectively; Described memory I P core module is connected with memory module; The output terminal of described memory I P core module, sequential generation module all is connected with the input end of display screen; The output terminal of described SD card control module is connected with the input end of SD card module.Described kernel control module is connected with the master control core processing unit by the Host Controler Interface module, and described Host Controler Interface module is for processing the module of asynchronous sequential logic.
Wherein kernel control module is backlight and drive and the control signal such as enable to flat-panel monitor output; The other end of Host Controler Interface module is connected with external master control processing unit is first; One end of phaselocked loop IP kernel module is connected with the external major clock LCK of system.The Host Controler Interface module can be configured according to different master control processing unit units; Phaselocked loop IP kernel module can be configured according to different rate requests (the highest 350MHz).
Described kernel control module is connected with the master control core processing unit by the Host Controler Interface module, and described Host Controler Interface module is for processing the module of asynchronous sequential logic.
Described memory I P core module comprises output FIFO IP kernel module, AMBA bus AHB-Lite IP kernel module, SDRAM control IP kernel module, PSRAM control IP kernel module;
The input end of described output FIFO IP kernel module is connected with the output terminal of kernel control module;
Described AMBA bus AHB-Lite IP kernel module is connected with kernel control module, the output terminal of described clock reference module is connected with the input end of SDRAM control IP kernel module, PSRAM control IP kernel module respectively, AMBA bus AHB-Lite IP kernel module is connected with SDRAM control IP kernel module, PSRAM control IP kernel module respectively, and SDRAM control IP kernel module, PSRAM control IP kernel module are connected with memory module respectively;
The output terminal of described output FIFO IP kernel module is connected with the input end of display screen.
Described SD control module comprises SPI IP kernel module, input FIFO IP kernel module, SD card control state machine module, and the output terminal of described input FIFO IP kernel module is connected with the input end of kernel control module; The output terminal of described clock reference module is connected with the input end of SPI IP kernel module, input FIFO IP kernel module, SD card control state machine module respectively, SD card control state machine module is connected with SPI IP kernel module, input FIFO IP kernel module respectively, and SPI IP kernel module is connected with the SD card module.
Described clock reference module is the asynchronous clock driver module, for flat-panel monitor provides required timing control signal.
Described sequential generation module is the module of timing control signal.
Described output FIFO IP kernel module, AMBA bus AHB-Lite IP kernel module, SDRAM control IP kernel module, PSRAM control IP kernel module, SPI IP kernel module, input FIFO IP kernel module are the IP kernel module through the technical grade checking.
SDRAM control IP kernel module can be configured according to different SDRAM chips; PSRAM control IP kernel module can be configured according to different SRAM/PSRAM chips; SPI IP kernel module can be configured according to different SD cards/SPI flash chip;
Output FIFO IP kernel module, sequential generative circuit module can be configured according to different flat-panel monitors.
Described kernel control module adopts Actel based on the low-power consumption FPGA chip of Flash technique.
Kernel control module is core of the present utility model, is responsible for the control of whole driving circuit, also is simultaneously the processing unit that shows data.Kernel control module arranges the mode of operation of driving circuit and the duty of query driven circuit by the operation of Host Controler Interface module.For the data that will show, at first from SD card or external master control processing unit unit, take out raw display data by kernel control module, then deposit display-memory SDRAM or SRAM/PSRAM in, finally be sent to display device.Utilize the hardware description language programming to realize kernel control module, can carry out flexibly Programming, supporting bus width (8-, 16-, 32-) and flexibly function combination configuration.
The Main Function of sequential generation module and output FIFO IP kernel module is clock signal to be provided and to show data for flat-panel monitor.It belongs to the IO equipment interface, is the interface between kernel control module and the flat-panel monitor, and kernel control module operates the demonstration output mode by controlling output FIFO IP kernel module.
Show that data are not directly to output to follow-up display channel, but first through the buffering of output FIFO IP kernel module, enter again subsequent conditioning circuit.Because address generator according to the employed display characteristic of hardware and current scanning position, can calculate the frame buffer address in advance, just the pixel data that is ahead of scanning position can be read in frame buffer, and temporarily be stored in the output FIFO IP kernel module.And follow-up display channel can obtain without time-delay ground the pixel data of current scanning position from output FIFO IP kernel module.
Output FIFO IP kernel module can be combined into required different depth and the FIFO of bit wide according to the flat-panel monitor that need drive.FIFO is a kind of fast data storage and reading unit, and input port is synchronized with memory clock, and output port is synchronized with pixel clock.The FIFO circuit to write the end data width the same with the highway width of frame buffer.When data among the FIFO will run through, just export the empty sign of FIFO, require the read request of frame buffer preferential answering address generator, reading out data at once is to guarantee the data volume among the FIFO.Will write when full when data among the FIFO, just export FIFO full scale will signal.The sequential generation module is realized refreshing flat-panel monitor.
But the utility model is realized the different driving requirement of flat-panel monitor based on the technology of FPGA flexible configuration, and drive interface is flexible, can drive different types of flat-panel monitor, integrates for system-level application to provide the foundation.
Description of drawings
Fig. 1 is a kind of flat pannel display drive unit one-piece construction block diagram based on FPGA of the utility model;
Fig. 2 is the connection diagram of the external master control processing unit of the utility model and driving circuit.
Specific embodiment
To help to understand the utility model by example.But do not limit content of the present utility model.All distortion that those of ordinary skill in the art can directly derive or associate from the disclosed content of the utility model all should be thought protection domain of the present utility model.
For realizing the purpose of this utility model, the utility model provides a kind of flat pannel display drive unit based on FPGA, as shown in Figure 1, comprise kernel control module 1, master control core processing unit 2, phaselocked loop IP kernel module 3, clock reference module 4, memory I P core module 5, memory module 6, sequential generation module 7, display screen 8, SD card control module 9, SD card module 10
Kernel control module 1 is connected with master control core processing unit 2, memory I P core module 5, SD card control module 9 respectively; The output terminal of described phaselocked loop IP kernel module 3 is connected with the input end of clock reference module 4; The output terminal of described clock reference module 4 is connected with the input end of kernel control module 1, IP kernel module 5, sequential generation module 7, display screen 8, SD card control module 9 respectively; Described memory I P core module 5 is connected with memory module 6; The output terminal of described memory I P core module 5, sequential generation module 7 is connected with the input end of display screen 8 respectively, the output terminal of clock reference module 4 is connected with the input end of SD card control module 9, and SD card control state machine is inputted FIFO IP kernel module respectively with in the SD card control module 9 in the SD card control module 9, SPI IP kernel module is connected.
Kernel control module 1 is connected with master control core processing unit 2 by the Host Controler Interface module, and described Host Controler Interface module is for processing the module of asynchronous sequential logic.
Memory I P core module 5 comprises output FIFO IP kernel module, AMBA bus AHB-Lite IP kernel module, SDRAM control IP kernel module, PSRAM control IP kernel module;
AMBA bus AHB-Lite IP kernel module is connected with kernel control module 1, the output terminal of clock reference module 4 is connected with the input end of SDRAM control IP kernel module, PSRAM control IP kernel module respectively, AMBA bus AHB-Lite IP kernel module is connected with SDRAM control IP kernel module, PSRAM control IP kernel module respectively, and SDRAM control IP kernel module, PSRAM control IP kernel module are connected with memory module 6 respectively.
Kernel control module 1 is connected with master control core processing unit 2 by the Host Controler Interface module, and SD card module 10 is connected with SD card control module 9.
SD control module 9 comprises SPI IP kernel module, input FIFO IP kernel module, SD card control state machine module, and the output terminal of described input FIFO IP kernel module is connected with the input end of kernel control module 1; The output terminal of described clock reference module 4 is connected with the input end of SPI IP kernel module, input FIFO IP kernel module, SD card control state machine module respectively, SD card control state machine module is connected with SPI IP kernel module, input FIFO IP kernel module respectively, and SPI IP kernel module is connected with SD card module 10.
Output FIFO IP kernel module, AMBA bus AHB-Lite IP kernel module, SDRAM control IP kernel module, PSRAM control IP kernel module, SPI IP kernel module, input FIFO IP kernel module are the IP kernel module through the technical grade checking.
In the present embodiment, the concrete model of each element is:
Master control core processing unit 2:ATmega64(TQFP64) single-chip microcomputer; SD card: Trencend 2GB; Display screen 8:AT070TN92; SDRAM:K4S281632K(TSOP54); Backlight driving unit: LT1615(SOT23-5), LT1618(MSOP-10); FPGA:A3P250 (VQ 208).
As shown in Figure 2,5 ports in two complete 8 bit ports of ATmega64 and another 8 bit port are connected with the kernel control module 1 of driving circuit, realization is to controlling of driving circuit and shaking hands of communication protocol, and the state machine of kernel control module 1 comprises data or the order that the asynchronous logic of processing Handshake Protocol and register-stored are transmitted by FPDP.
For example the ATmega64 single-chip microcomputer is by the cooperation of two 8 bit data ports and control signal, send the demonstration data that control code to kernel control module 1 reads the storage of SD card, utilize SPI IP kernel module that external SD card module 10 is realized read operation by controlling SD card control module 9 after the corresponding control code of kernel control module 1 decoding, and data are stored to input FIFO IP kernel module, then kernel control module 1 data that will input FIFO IP kernel module stores are controlled the IP kernel module through AMBA bus AHB-Lite IP kernel module and SDRAM and are written to external SDRAM chip or are written to external SRAM or PSRAM chip by PSRAM IP kernel module;
The demonstration data communication device that kernel control module 1 can regularly will be stored among external SDRAM or SRAM or the PSRAM according to the resolution of different flat-panel monitors is crossed SDRAM control IP kernel module or PSRAM IP kernel module, read through AMBA bus AHB-Lite IP kernel module, and reading out data is sent to panel display screen 8 by output FIFO IP kernel module under the control of sequential generation module 7, realize display effect.
The resolution of display screen 8 is 800*480, shows that data transmit according to the RGB565 form, the sweep frequency of 60Hz, and then HSync is 28.8KHz in theory, and VSync is 48KHz, and Dclk is 23.04MHz.
Input clock CLK is 48MHz, generate the output of 96MHz clock signal through phaselocked loop IP kernel module 3, processing through clock reference module 4 generates four groups of clock signals, is respectively applied to the operation clock of kernel control module 1, the read-write clock of SDRAM, the Dot Clock signal Dclk of display screen and the read-write operation of SD card, the input clock signal of sequential generation module 7.
Claims (7)
1. flat pannel display drive unit based on FPGA, it is characterized in that comprising kernel control module (1), master control core processing unit (2), phaselocked loop IP kernel module (3), clock reference module (4), memory I P core module (5), memory module (6), sequential generation module (7), display screen (8), SD card control module (9), SD card module (10)
Described kernel control module (1) is connected with master control core processing unit (2), memory I P core module (5), SD card control module (9) respectively; The output terminal of described phaselocked loop IP kernel module (3) is connected with the input end of clock reference module (4); The output terminal of described clock reference module (4) is connected with the input end of kernel control module (1), memory I P core module (5), sequential generation module (7), display screen (8), SD card control module (9) respectively; Described memory I P core module (5) is connected with memory module (6); The output terminal of described memory I P core module (5), sequential generation module (7) all is connected with the input end of display screen (8); The output terminal of described SD card control module (9) is connected with the input end of SD card module (10).
2. described flat pannel display drive unit based on FPGA according to claim 1, it is characterized in that described kernel control module (1) is connected with master control core processing unit (2) by the Host Controler Interface module, described Host Controler Interface module is for processing the module of asynchronous sequential logic.
3. described flat pannel display drive unit based on FPGA according to claim 1 is characterized in that described memory I P core module (5) comprises output FIFO IP kernel module, AMBA bus AHB-Lite IP kernel module, SDRAM control IP kernel module, PSRAM control IP kernel module;
The input end of described output FIFO IP kernel module is connected with the output terminal of kernel control module (1);
Described AMBA bus AHB-Lite IP kernel module is connected with kernel control module (1), the output terminal of described clock reference module (4) is connected with the input end of SDRAM control IP kernel module, PSRAM control IP kernel module respectively, AMBA bus AHB-Lite IP kernel module is connected with SDRAM control IP kernel module, PSRAM control IP kernel module respectively, and SDRAM control IP kernel module, PSRAM control IP kernel module are connected with memory module (6) respectively;
The output terminal of described output FIFO IP kernel module is connected with the input end of display screen (8).
4. described flat pannel display drive unit based on FPGA according to claim 1, it is characterized in that described SD control module (9) comprises SPI IP kernel module, input FIFO IP kernel module, SD card control state machine module, the output terminal of described input FIFO IP kernel module is connected with the input end of kernel control module (1); The output terminal of described clock reference module (4) is connected with the input end of SPI IP kernel module, input FIFO IP kernel module, SD card control state machine module respectively, SD card control state machine module is connected with SPI IP kernel module, input FIFO IP kernel module respectively, and SPI IP kernel module is connected with SD card module (10).
5. described flat pannel display drive unit based on FPGA according to claim 1 is characterized in that described clock reference module (4) is the asynchronous clock driver module.
6. described flat pannel display drive unit based on FPGA according to claim 1 is characterized in that described sequential generation module (7) is the module of timing control signal.
7. described flat pannel display drive unit based on FPGA according to claim 1 is characterized in that described output FIFO IP kernel module, AMBA bus AHB-Lite IP kernel module, SDRAM control IP kernel module, PSRAM control IP kernel module, SPI IP kernel module, input FIFO IP kernel module are the IP kernel module through the technical grade checking.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220167549 CN202838922U (en) | 2012-04-19 | 2012-04-19 | FPGA (Field Programmable Gate Array) based flat panel display driving apparatus |
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| CN 201220167549 CN202838922U (en) | 2012-04-19 | 2012-04-19 | FPGA (Field Programmable Gate Array) based flat panel display driving apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103309514A (en) * | 2013-06-28 | 2013-09-18 | 周国辉 | High-speed synchronous display card |
| CN104571984A (en) * | 2013-10-28 | 2015-04-29 | 京微雅格（北京）科技有限公司 | Extensible FPGA (Field Programmable Gate Array) display system with MCU (Microprogrammed Control Unit), display method and electronic equipment |
| CN110191253A (en) * | 2019-04-10 | 2019-08-30 | 电子科技大学 | LCoS micro-display drive control module based on FPGA |
-
2012
- 2012-04-19 CN CN 201220167549 patent/CN202838922U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103309514A (en) * | 2013-06-28 | 2013-09-18 | 周国辉 | High-speed synchronous display card |
| CN103309514B (en) * | 2013-06-28 | 2016-04-06 | 哈尔滨师范大学 | High-speed synchronous display card |
| CN104571984A (en) * | 2013-10-28 | 2015-04-29 | 京微雅格（北京）科技有限公司 | Extensible FPGA (Field Programmable Gate Array) display system with MCU (Microprogrammed Control Unit), display method and electronic equipment |
| CN110191253A (en) * | 2019-04-10 | 2019-08-30 | 电子科技大学 | LCoS micro-display drive control module based on FPGA |
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Granted publication date: 20130327 Termination date: 20200419 |