CN202352302U - Liquid crystal display device and time schedule controller thereof - Google Patents
Liquid crystal display device and time schedule controller thereof Download PDFInfo
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- CN202352302U CN202352302U CN 201120416176 CN201120416176U CN202352302U CN 202352302 U CN202352302 U CN 202352302U CN 201120416176 CN201120416176 CN 201120416176 CN 201120416176 U CN201120416176 U CN 201120416176U CN 202352302 U CN202352302 U CN 202352302U
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Abstract
The utility model discloses a liquid crystal display device and a time schedule controller thereof. According to the time schedule controller, transmission signals are received, then control signals and clock signals are output to a gate driver and a data driver, and pixel data are transmitted to the data driver. The time schedule controller comprises a receiving device used for receiving the transmission signals, a data processor used for processing the transmission signals, an output device for outputting the pixel data and the clock signals and a control signal producing device for producing the control signals, wherein the receiving device is respectively connected with input ends of the data processor and the control signal producing device, an output end of the data processor is connected with an input end of the output device, and an output end of the output device and an output end of the control signal producing device are connected with an input end of the gate driver and an input end of the data driver. The liquid crystal display device and the time schedule controller have the advantages that the circuit structure is simple and production cost is lowered.
Description
Technical field
The utility model relates to the liquid crystal panel technical field, in particular a kind of liquid crystal indicator and time schedule controller thereof.
Background technology
At present, liquid crystal panel is widely used in fields such as display, notebook computer, mobile phone because of it has low-power consumption, low radiation, advantage such as frivolous.And in the use of liquid crystal panel, very crucial to the driving of liquid crystal panel.And time schedule controller (T-con) internal circuit element that the control liquid crystal panel drives is many; Circuit structure is complicated, does not fully integrate inner circuit component, develops for the subsequent applications liquid crystal panel and makes troubles; Be unfavorable for controlling cost, also make troubles simultaneously to circuit analysis.
Therefore, prior art awaits to improve and development.
The utility model content
In view of the deficiency of above-mentioned prior art, the purpose of the utility model is to provide a kind of liquid crystal indicator and time schedule controller thereof, and not only circuit structure is simple, and has reduced manufacturing cost.
The technical scheme of the utility model is following:
A kind of time schedule controller of liquid crystal indicator, said time schedule controller transfers to gate drivers and data driver with control signal, clock signal after receiving transmission signals, and pixel data is transferred to said data driver, and said time schedule controller comprises:
One is used to receive the receiving trap of said transmission signals;
One is used to handle the data processor of the said transmission signals that receives;
The output unit of one said pixel data of output and said clock signal;
One is used to produce the control signal generator means of said control signal; Wherein, Said receiving trap is connected with the input end of said data processor and the input end of said control signal generator means respectively; The output terminal of said data processor is connected with the input end of said output unit; The output terminal of said output unit is connected with the input end of said gate drivers and the input end of said data driver respectively, and the output terminal of said control signal generator means is connected with the input end of said gate drivers and the input end of said data driver respectively.
Further; Said data processor comprises: one is used for extracting from transmission signals demoder, a gamma-correction circuit, a data buffer, a scrambler of said pixel data and enable signal; Said demoder connects said gamma-correction circuit; Said gamma-correction circuit connects said data buffer, and said data buffer connects said scrambler.
Further, said data buffer is the first in first out buffer, comprises two sub-first in first out buffers, and said two sub-first in first out buffers are stored the data of the left and right half screen of said demoder output respectively.
Further, said demoder, said gamma-correction circuit, said data buffer and said scrambler are integrated in the said data processor.
Further, said receiving trap, said data processor, said output unit and said control signal generator means are integrated is arranged on the same PCB mainboard.
Further, said receiving trap is the LVDS receiving trap, and said output unit is the mini-LVDS output unit.
A kind of liquid crystal indicator wherein, comprises above-mentioned described time schedule controller.
Liquid crystal indicator that the utility model provided and time schedule controller thereof are realized data processing through data processor, realize that frequency of operation is adjustable, and it is simple to have a circuit structure, advantages such as production cost reduction.
Description of drawings
Fig. 1 is the schematic block circuit diagram of preferred embodiment of the time schedule controller of the utility model liquid crystal indicator.
Embodiment
The utility model provides a kind of liquid crystal indicator and time schedule controller thereof, for purpose, technical scheme and the effect that makes the utility model is clearer, clear and definite, below with reference to accompanying drawing and give an actual example to the utility model further explain.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
See also Fig. 1, Fig. 1 is the schematic block circuit diagram of preferred embodiment of the time schedule controller of the utility model liquid crystal indicator.The utility model liquid crystal indicator comprises time schedule controller 100, gate drivers (not shown) and data driver (not shown) and liquid crystal panel (not shown).In the preferred embodiment of the utility model, this liquid crystal panel is IPS-a (in-plane a changes) liquid crystal panel.After time schedule controller 100 receives transmission signals, export control signal and clock signal to gate drivers and data driver, and pixel data is transferred to data driver.Gate drivers and data driver drive liquid crystal panel work then.As shown in Figure 1, time schedule controller 100 comprises LVDS (low-voltage differential signal) receiving trap 110, data processor 120, mini-LVDS output unit 130 and control signal generator means 140.LVDS receiving trap 110 is used to receive data-signal, clock signal and enables transmission signals such as (DE) signal.Data processor 120 is used to handle this transmission signals that receives.Mini-LVDS output unit 130 output pixel data and clock signal are to data driver, and clock signal is to gate drivers.Control signal generator means 140 is used to produce control signal, and exports gate drivers and data driver respectively to.LVDS receiving trap 110 is connected with the input end of data processor 120 and the input end of control signal generator means 140 respectively.The output terminal of data processor 120 is connected with the input end of mini-LVDS output unit 130.The output terminal of mini-LVDS output unit 130 is connected with the input end of gate drivers and the input end of data driver respectively.The output terminal of control signal generator means 140 is connected with the input end of gate drivers and the input end of data driver respectively.
LVDS receiving trap 110, data processor 120, mini-LVDS output unit 130 and control signal generator means 140 integrated being arranged on the same PCB mainboard.
Specifically; LVDS receiving trap 110 is used to receive data-signal, clock signal and enable signal (DE); The LVDS (low-voltage differential signal) of input is converted into TTL signal (level pulse signal), and gives data processor 120 data transmission of this TTL signal.Wherein, data-signal is pending data, for example view data and lteral data.The LVDS signal has 5 the tunnel, comprises 3 circuit-switched data signals, 1 tunnel clock signal and 1 road DE signal.Wherein data-signal comprises red (R), green (G), blue pixel datas such as (B).Wherein, clock signal is that data processor 20 provides time clock, and transfers to mini-LVDS output unit 130 through data processor 20.
Wherein, The data stream that 121 pairs of LVDS receiving traps 110 of demoder are received is decoded; Therefrom read red (R), green (G), blue pixel data and enable signals (DE) such as (B), and red (R) after will handling, green (G), blue pixel datas such as (B) and enable signal (DE) export gamma-correction circuit 122 to.
Gamma-correction circuit 122 is used for demoder 121 decoded pixel datas are carried out gamma correction, and the output gamma correction data is given data buffer 123.
The gamma correction data of 123 pairs of gamma-correction circuits of data buffer 122 output is carried out buffer-stored, then according to order output data to the scrambler 124 of first in first out.This data buffer 123 is the first in first out buffer, comprises two sub-first in first out buffers (FIFO), and two sub-first in first out buffers are stored the data of the left and right half screen of self-demarking code device output respectively.
Input data after scrambler 124 cooperates control signal to buffering are encoded, and export gate drivers (Gate-Driver) and data driver (Source-Driver) to through mini-LVDS output unit 130.Wherein, mini-LVDS output unit 130 with clock signal and the pixel data of accomplishing of having encoded be converted into the output of mini-LVDS form.The frequency of clock signal is 60Hz.
Control signal generator means 140 receives the DE signal and the clock signal of LVDS receiving trap 110 outputs; And generation control signal; To be mainly used in and to produce frequency be the frame starting signal of 60Hz and capable enabling signal and all the other control signals that frequency is 48KHz to control signal generator means 140 in the present embodiment, and the control signal of generation directly exports gate drivers and data driver to.
Particularly; Control signal generator means 140 is a benchmark with the rising edge of DE signal behind the DE signal that finds frame to begin, add certain delay after; Producing frequency is the frame starting signal (STV) of 60Hz; And to produce frequency be the capable enabling signal (STH) of 48kHz, produces remaining control signal simultaneously, exports above-mentioned control signal to gate drivers and data driver respectively then.
In addition; Demoder 121, gamma-correction circuit 122, data buffer 123 and scrambler 124 are integrated in the data processor 120; Can realize the adjusting of frequency of operation and be implemented in a passage or two passages carry out the input and the output of data that data buffer 123 adopts the first in first out data buffers can reduce the quantity of peripheral storage through programming.
Preferably, the time schedule controller of a kind of liquid crystal indicator that the utility model provides is input as the LVDS signal of 60Hz, 1 passage; Be output as mini-LVDS signal and 6 control signals of 60Hz, 8bit, two passages; 6 control signals are respectively applied for the operate as normal of control gate driver and data driver, and wherein, gate drivers is located at the Y axle; The position that its decision image shows, the data that the pixel of horizontal each row of notice will be imported; Data driver is located at the X axle, and it mainly is the input of arrangement data, is responsible for image data is sent to liquid crystal panel.
Based on the foregoing description, the utility model also provides a kind of liquid crystal indicator, and the liquid crystal indicator of this embodiment comprises above-mentioned described time schedule controller 100.
In sum; The time schedule controller of a kind of liquid crystal indicator that the utility model provided is realized data processing through data processor, realizes that frequency of operation is adjustable; And support the input and output of a passage and two passages; Adopt the first in first out data buffer to reduce the usage quantity of peripheral storages such as RAM, FLASH simultaneously, circuit structure is simple, has reduced production cost.
Should be understood that; The application of the utility model is not limited to above-mentioned giving an example; Concerning those of ordinary skills, can improve or conversion according to above-mentioned explanation, all these improvement and conversion all should belong to the protection domain of the utility model accompanying claims.
Claims (7)
1. the time schedule controller of a liquid crystal indicator; Said time schedule controller transfers to gate drivers and data driver with control signal, clock signal after receiving transmission signals, and pixel data is transferred to said data driver; It is characterized in that said time schedule controller comprises:
One is used to receive the receiving trap of said transmission signals;
One is used to handle the data processor of the said transmission signals that receives;
The output unit of one said pixel data of output and said clock signal;
One is used to produce the control signal generator means of said control signal; Wherein, Said receiving trap is connected with the input end of said data processor and the input end of said control signal generator means respectively; The output terminal of said data processor is connected with the input end of said output unit; The output terminal of said output unit is connected with the input end of said gate drivers and the input end of said data driver respectively, and the output terminal of said control signal generator means is connected with the input end of said gate drivers and the input end of said data driver respectively.
2. according to the time schedule controller of the said liquid crystal indicator of claim 1; It is characterized in that; Said data processor comprises: one is used for extracting from transmission signals demoder, a gamma-correction circuit, a data buffer, a scrambler of said pixel data and enable signal; Said demoder connects said gamma-correction circuit, and said gamma-correction circuit connects said data buffer, and said data buffer connects said scrambler.
3. according to the time schedule controller of the said liquid crystal indicator of claim 2; It is characterized in that; Said data buffer is the first in first out buffer, comprises two sub-first in first out buffers, and said two sub-first in first out buffers are stored the data of the left and right half screen of said demoder output respectively.
4. according to the time schedule controller of the said liquid crystal indicator of claim 2, it is characterized in that said demoder, said gamma-correction circuit, said data buffer and said scrambler are integrated in the said data processor.
5. according to the time schedule controller of the said liquid crystal indicator of claim 1, it is characterized in that said receiving trap, said data processor, said output unit and said control signal generator means are integrated to be arranged on the same PCB mainboard.
6. according to the time schedule controller of each said liquid crystal indicator in the claim 1 to 5, it is characterized in that said receiving trap is the LVDS receiving trap, said output unit is the mini-LVDS output unit.
7. a liquid crystal indicator is characterized in that, comprises each described time schedule controller of aforesaid right requirement 1-6.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120416176 CN202352302U (en) | 2011-10-27 | 2011-10-27 | Liquid crystal display device and time schedule controller thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201120416176 CN202352302U (en) | 2011-10-27 | 2011-10-27 | Liquid crystal display device and time schedule controller thereof |
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| CN202352302U true CN202352302U (en) | 2012-07-25 |
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| CN 201120416176 Expired - Fee Related CN202352302U (en) | 2011-10-27 | 2011-10-27 | Liquid crystal display device and time schedule controller thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304053A (en) * | 2015-11-25 | 2016-02-03 | 深圳市华星光电技术有限公司 | Sequence control chip inner starting signal control method, chip, and display panel |
| CN106710514A (en) * | 2015-07-24 | 2017-05-24 | 西安诺瓦电子科技有限公司 | Programmable logic device, receiving card and LED display screen control system |
| CN106952600A (en) * | 2016-01-07 | 2017-07-14 | 奇景光电股份有限公司 | Time schedule controller and its signal output method |
-
2011
- 2011-10-27 CN CN 201120416176 patent/CN202352302U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106710514A (en) * | 2015-07-24 | 2017-05-24 | 西安诺瓦电子科技有限公司 | Programmable logic device, receiving card and LED display screen control system |
| CN106710514B (en) * | 2015-07-24 | 2018-10-26 | 西安诺瓦电子科技有限公司 | Programmable logic device receives card and LED display control system |
| CN105304053A (en) * | 2015-11-25 | 2016-02-03 | 深圳市华星光电技术有限公司 | Sequence control chip inner starting signal control method, chip, and display panel |
| WO2017088242A1 (en) * | 2015-11-25 | 2017-06-01 | 深圳市华星光电技术有限公司 | Method for controlling start signal in timing controller integrated circuit, integrated circuit, and display panel |
| US9898993B2 (en) | 2015-11-25 | 2018-02-20 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Method for controlling message signal within timing controller integrated circuit, timing controller integrated circuit and display panel |
| CN106952600A (en) * | 2016-01-07 | 2017-07-14 | 奇景光电股份有限公司 | Time schedule controller and its signal output method |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120725 Termination date: 20151027 |
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| EXPY | Termination of patent right or utility model |