CN202694547U - Broadband coded signal detection circuit and wireless remote control signal decoding circuit thereof - Google Patents
Broadband coded signal detection circuit and wireless remote control signal decoding circuit thereof Download PDFInfo
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- CN202694547U CN202694547U CN 201220259086 CN201220259086U CN202694547U CN 202694547 U CN202694547 U CN 202694547U CN 201220259086 CN201220259086 CN 201220259086 CN 201220259086 U CN201220259086 U CN 201220259086U CN 202694547 U CN202694547 U CN 202694547U
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Abstract
The utility model discloses a broadband coded signal detection circuit and a wireless remote control signal decoding circuit thereof, relates to the field of wireless remote control signal receiving and processing technology and solves the problem of narrow frequency tolerance range in prior art. The broadband coded signal detection circuit comprises a width counter, a width memorizer, a basic reference memorizer, a summator, a coding length determining circuit and a quantity counter, a coded signal is input to the width counter, the width counter inputs the signal to the width memorizer, the width memorizer inputs the signal to the summator and the basic reference memorizer, the basic reference memorizer inputs the signal to the summator, the summator inputs the signal to the coding length determining circuit, the coding length determining circuit inputs the signal to the quantity counter, the quantity counter inputs the signal to the width memorizer and the basic reference memorizer, and the quantity counter outputs a counting reset signal and a counting setting signal to subsequent circuits. According to the broadband coded signal detection circuit and the wireless remote control signal decoding circuit thereof, the frequency tolerance is in a range from (-87.5%) to (+100%) in theory, and by means of the circuits, the actual measurement range of the frequency tolerance is from (-86.7%) to (+64%).
Description
Technical field
The utility model relates to wireless remote control signals reception ﹠ disposal technical field, particularly relates to the technological improvement aspect of a kind of wireless remote control signals frequency tolerance scope and detection sensitivity.
Background technology
Along with the development of electronic industrial technology, the wireless remote control product is used more and more extensive in daily life, and is too numerous to enumerate, and existing wireless remote control signals processing form also is varied, and application is very extensive.Wherein larger purposes is in fields such as remote-control toy, household remote.At present, the emission of the wireless remote control signals of four functions/five-function, reception adopt special-purpose integrated circuit to realize more, and be with low cost, is convenient to produce in batches; But existing integrated circuit is when processing remote signal, to frequency tolerance require high (theory can accept ± 25% frequency tolerance, but restricted by various factors, when frequency departure reach ± distant control function lost efficacy 15% the time), give to produce to debug and bring a lot of troubles, affected production efficiency, qualification rate and the stability of product.
Summary of the invention
For the above-mentioned narrow shortcoming of prior art medium frequency range of tolerable variance of mentioning, and a kind of wideband coded signal testing circuit and the wireless remote control signals decoding circuit thereof that propose.
The technical scheme that its technical matters that solves the utility model adopts is: a kind of wideband coded signal testing circuit is characterized in that described circuit includes: width counter, width storer, benchmark memory, totalizer, code length decision circuitry and number count device; Coded signal inputs to the width counter, width counter input signal is to the width storer, width storer input signal is to totalizer and benchmark memory, the benchmark memory input signal is to totalizer, the totalizer input signal is to the code length decision circuitry, code length decision circuitry input signal is to the number count device, and number count device input signal is to width storer and benchmark memory, and number count device output count resets signal, counting asserts signal are given follow-up circuit; Wherein
The width counter begins the cycle of coded signal is carried out the width counting take the coded signal rising edge as reset signal, and before resetting, width gauge numerical value I is stored in the width storer at every turn;
The width storer, be provided with one by the selector switch of number count device control, when the number count value J of number count device feedback＜4, the width storing value B of width storer is exported to totalizer, number count value J when number count device feedback 〉=4 the time, 2 times width storing value B are exported to totalizer;
Benchmark memory, when the width storer detects code error or finishes, by number count device control, the width storing value B of width storer is assigned to benchmark memory, the benchmark storing value A of benchmark memory is as judging whether effective benchmark of next coded signal length;
Totalizer, when receiving the width storing value B of width storer, carry out the A/4-|A-B| computing, when the width storing value B of width storer that receives 2 times, carry out the A/4-|A-2*B| computing, and with operation result on the occasion of or negative value export to the code length decision circuitry;
The code length decision circuitry, when totalizer be output as on the occasion of, and current width gauge numerical value I, width storing value B, when number count value J does not overflow, it is effective to be judged as coded signal length, otherwise coded signal length is invalid;
The number count device is used for the quantity of coded signal is counted, and is encoded to counting clock with the action after processing, and coded signal length is invalid to be counted for reset signal; When the number count value J=0 of number count device, the control benchmark memory is also exported the count resets signal simultaneously from width storer value, closes the counting of back counting circuit; When number count value J＜4, control width storer is exported to totalizer with width storing value B; As number count value J 〉=4 the time, control width storer is exported to totalizer with 2 times width storing value; When counter J=4, also asserts signal is counted in output simultaneously, opens the counting of back counting circuit.
Described width counter and number count device are 7 counter.
Described width storer and benchmark memory are 7 storer.
Described totalizer is 2 groups of 8 totalizers.
Use the wireless remote control signals decoding circuit of above-mentioned wideband coded signal testing circuit, it is characterized in that described decoding circuit is integrated except including each described wideband coded signal testing circuit of claim 1 to 4, also include oscillating unit, reset unit, signal processing unit, counting control unit, counting unit, code translator, sampling unit and logic output unit; Wherein:
Described oscillating unit generates the global clock signal, produces reference period Tosc;
Described electrification reset unit generates global reset signal;
Described signal processing unit receives the input of the coded signal of transmitting terminal, by clock sampling, exports to described wideband coded signal testing circuit and counting unit behind the burr at removal rising edge place;
Described wideband coded signal testing circuit by each action code in the coded signal of contrast input or the length of end code, is judged the correctness of coded signal; When detect coded signal for wrong/when finishing, output count resets signal is to counting control unit, when detecting coded signal and be the active data code, output counting asserts signal is to counting control unit, output counting asserts signal is to sampling unit simultaneously;
Described counting control unit, the work of control counting unit, when receiving the count resets signal, control is closed and the reset count unit; When receiving the counting asserts signal, counting unit is opened in control;
Described counting unit, the number of enumeration data code inputs to code translator with count results;
Described code translator is converted into corresponding decoded signal with the count results of inputting, and exports to sampling unit;
Described sampling unit, when the count resets signal is effective, the sampling decoded signal, and sampled result exported to the output logic unit;
Described output logic unit will sample decoded signal and be converted into actuating signal, export to the subsequent drive circuit.
The beneficial effects of the utility model are: the utility model is the integrated modules such as width counter, width storer, benchmark memory, totalizer, code length decision circuitry, number count device in inside, global clock signal, global reset signal, three input signals of coded signal are arranged, count resets signal, two output signals of counting asserts signal are arranged, so that the utility model allows-87.5 ~+100% frequency tolerance in theory, the actual measurement scope is-86.7 ~+64%.
Description of drawings
Fig. 1 is the utility model wideband coded signal testing circuit internal logic block scheme.
Fig. 2 is the utility model wideband coded signal testing circuit workflow diagram.
Fig. 3 is a kind of typical radio remote signal sequential chart that the utility model is processed.
Fig. 4 is a kind of wireless remote control signals decoding circuit that uses the utility model wideband coded signal testing circuit.
Embodiment
Present embodiment is the utility model preferred implementation, and other all its principles are identical with present embodiment or approximate with basic structure, all within the utility model protection domain.
A kind of wideband coded signal testing circuit that the utility model proposes, please referring to shown in the accompanying drawing 1, this main circuit will be integrated with width counter, width storer, benchmark memory, totalizer, code length decision circuitry and number count device, and the input signal that this testing circuit receives has global clock signal, global reset signal, three input signals of coded signal; The signal of output has count resets signal and counting asserts signal, the global clock signal, global reset signal inputs to above-mentioned all modules, coded signal inputs to the width counter, width counter input signal is to the width storer, width storer input signal is to totalizer and benchmark memory, the benchmark memory input signal is to totalizer, the totalizer input signal is to the code length decision circuitry, code length decision circuitry input signal is to the number count device, number count device input signal is to width storer and benchmark memory, and the number count device is exported the count resets signal, the counting asserts signal is given follow-up circuit.
Shown in Fig. 2, concrete implementation, the width counter begins the cycle of coded signal is carried out the width counting take the coded signal rising edge as reset signal, and before resetting, width gauge numerical value I is stored in the width storer at every turn;
The width storer, be provided with one by the selector switch of number count device control, when the number count value J of number count device feedback＜4, the width storing value B of width storer is exported to totalizer, number count value J when number count device feedback 〉=4 the time, 2 times width storing value B are exported to totalizer;
Benchmark memory, when the width storer detects code error or finishes, by number count device control, the width storing value B of width storer is assigned to benchmark memory, the benchmark storing value A of benchmark memory is as judging whether effective benchmark of next coded signal length;
Totalizer, when receiving the width storing value B of width storer, carry out the A/4-|A-B| computing, when the width storing value B of width storer that receives 2 times, carry out the A/4-|A-2*B| computing, and with operation result on the occasion of or negative value export to the code length decision circuitry;
The code length decision circuitry, when totalizer be output as on the occasion of, and current width gauge numerical value I, width storing value B, when number count value J does not overflow, it is effective to be judged as coded signal length, otherwise coded signal length is invalid; 1, width counter, carry-out bit are 0 without overflowing, and carry-out bit is 1 to overflow.Width storer carry-out bit is 0 without overflowing, and carry-out bit is 1 to overflow;
Totalizer, carry-out bit 0 be for negative, and carry-out bit 1 is for just; Number count device, carry-out bit are 0 without overflowing, and carry-out bit is 1 to overflow;
The number count device is used for the quantity of coded signal is counted, and is encoded to counting clock with the action after processing, and coded signal length is invalid to be counted for reset signal; When the number count value J=0 of number count device, the control benchmark memory is also exported the count resets signal simultaneously from width storer value, closes the counting of back counting circuit; When number count value J＜4, control width storer is exported to totalizer with width storing value B; As number count value J 〉=4 the time, control width storer is exported to totalizer with 2 times width storing value; When counter J=4, also asserts signal is counted in output simultaneously, opens the counting of back counting circuit.Described width counter and number count device are 7 counter.Described width storer and benchmark memory are 7 storer.Described totalizer is 2 groups of 8 totalizers.
A kind of typical wireless remote control signals sequential of the present utility model is please referring to accompanying drawing 3.The coding that receives is comprised of N action code and 14 end code.The frequency Fosc that reference period Tosc is corresponding is reference frequency.Wherein the dutycycle of preamble code W1 is 75%, and one-period is Tosc*2
8The dutycycle of numeric data code W2 is 50%, and one-period is Tosc*2
7Wherein action code comprises 4 preamble code W1 and n numeric data code W2, and n is decided by the action of input; End code comprises 4 preamble code W1 and 4 numeric data code W2.Decoded output begins receiving the first element code, stops when receiving first end code, if signal interrupts suddenly, does not receive end code, then at Tosc*2
16In stop.If coding changes then output signal also can change immediately during reception.
Please referring to accompanying drawing 4, a kind of wireless remote control signals decoding circuit that comprises above-mentioned wideband coded signal testing circuit, except including above-mentioned wideband coded signal testing circuit, also include oscillating unit, the modules such as reset unit, signal processing unit, counting control unit, counting unit, code translator, sampling unit and logic output unit.This decoding circuit is used for receiving the wireless remote control signals input, wireless remote control signals inputs to signal processing unit, signal processing unit inputs to wideband coded signal testing circuit and counting unit, wideband coded signal testing circuit signal inputs to counting control unit and sampling unit, counting control unit inputs to counting unit, counting unit inputs to decoding unit, decoding unit inputs to sampling unit, sampling unit inputs to the logic output unit, and logic output unit output action signal is to the subsequent drive circuit; Wherein:
Described oscillating unit generates the global clock signal, produces reference period Tosc;
Described electrification reset unit generates global reset signal;
Described signal processing unit receives the input of the coded signal of transmitting terminal, by clock sampling, exports to described wideband coded signal testing circuit and counting unit behind the burr at removal rising edge place;
Described wideband coded signal testing circuit by each action code in the coded signal of contrast input or the length of end code, is judged the correctness of coded signal; When detect coded signal for wrong/when finishing, output count resets signal is to counting control unit, when detecting coded signal and be the active data code, output counting asserts signal is to counting control unit, output counting asserts signal is to sampling unit simultaneously;
Described counting control unit, the work of control counting unit, when receiving the count resets signal, control is closed and the reset count unit; When receiving the counting asserts signal, counting unit is opened in control;
Described counting unit, the number of enumeration data code inputs to code translator with count results;
Described code translator is converted into corresponding decoded signal with the count results of inputting, and exports to sampling unit;
Described sampling unit, when the count resets signal is effective, the sampling decoded signal, and sampled result exported to the output logic unit;
Described output logic unit will sample decoded signal and be converted into actuating signal, export to the subsequent drive circuit.
The utility model is the integrated modules such as width counter, width storer, benchmark memory, totalizer, code length decision circuitry, number count device in inside, so that the utility model allows-87.5 ~+100% frequency tolerance in theory, the actual measurement scope has greatly improved production efficiency, qualification rate and the stability of the wireless remote control product of using this technology-86.7 ~+64%.
Claims (5)
1. a wideband coded signal testing circuit is characterized in that described circuit includes: width counter, width storer, benchmark memory, totalizer, code length decision circuitry and number count device; Coded signal inputs to the width counter, width counter input signal is to the width storer, width storer input signal is to totalizer and benchmark memory, the benchmark memory input signal is to totalizer, the totalizer input signal is to the code length decision circuitry, code length decision circuitry input signal is to the number count device, and number count device input signal is to width storer and benchmark memory, and number count device output count resets signal, counting asserts signal are given follow-up circuit; Wherein
The width counter carries out width to the cycle of coded signal and counts;
The width storer, be provided with one by the selector switch of number count device control, when the number count value J of number count device feedback＜4, the width storing value B of width storer is exported to totalizer, number count value J when number count device feedback 〉=4 the time, 2 times width storing value B are exported to totalizer;
Benchmark memory, when the width storer detects code error or finishes, by number count device control, the width storing value B of width storer is assigned to benchmark memory, the benchmark storing value A of benchmark memory is as judging whether effective benchmark of next coded signal length;
Totalizer is advanced arithmetical operation according to the output signal that receives the width storer, and the signal after will processing is exported to the code length decision circuitry;
The code length decision circuitry according to the overflow status of adder output signal and current width counter, width storer, number count device, is judged coded signal length validity;
The number count device is used for the quantity of coded signal is counted, and is encoded to counting clock with the action after processing, and coded signal length is invalid to be counted for reset signal; When the number count value J=0 of number count device, the control benchmark memory is also exported the count resets signal simultaneously from width storer value, closes the counting of back counting circuit; When number count value J＜4, control width storer is exported to totalizer with width storing value B; As number count value J 〉=4 the time, control width storer is exported to totalizer with 2 times width storing value; When counter J=4, also asserts signal is counted in output simultaneously, opens the counting of back counting circuit.
2. a kind of wideband coded signal testing circuit according to claim 1, it is characterized in that: described width counter and number count device are 7 counter.
3. a kind of wideband coded signal testing circuit according to claim 1, it is characterized in that: described width storer and benchmark memory are 7 storer.
4. a kind of wideband coded signal testing circuit according to claim 1, it is characterized in that: described totalizer is 2 groups of 8 totalizers.
5. an application rights requires the wireless remote control signals decoding circuit of 1 to 4 each described wideband coded signal testing circuit, it is characterized in that described decoding circuit is integrated except including each described wideband coded signal testing circuit of claim 1 to 4, also include oscillating unit, reset unit, signal processing unit, counting control unit, counting unit, code translator, sampling unit and logic output unit; Wherein:
Described oscillating unit generates the global clock signal, produces reference period Tosc;
Described electrification reset unit generates global reset signal;
Described signal processing unit receives the input of the coded signal of transmitting terminal, by clock sampling, exports to described wideband coded signal testing circuit and counting unit behind the burr at removal rising edge place;
Described wideband coded signal testing circuit by each action code in the coded signal of contrast input or the length of end code, is judged the correctness of coded signal; When detect coded signal for wrong/when finishing, output count resets signal is to counting control unit, when detecting coded signal and be the active data code, output counting asserts signal is to counting control unit, output counting asserts signal is to sampling unit simultaneously;
Described counting control unit, the work of control counting unit, when receiving the count resets signal, control is closed and the reset count unit; When receiving the counting asserts signal, counting unit is opened in control;
Described counting unit, the number of enumeration data code inputs to code translator with count results;
Described code translator is converted into corresponding decoded signal with the count results of inputting, and exports to sampling unit;
Described sampling unit, when the count resets signal is effective, the sampling decoded signal, and sampled result exported to the output logic unit;
Described output logic unit will sample decoded signal and be converted into actuating signal, export to the subsequent drive circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220259086 CN202694547U (en) | 2012-06-04 | 2012-06-04 | Broadband coded signal detection circuit and wireless remote control signal decoding circuit thereof |
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| CN 201220259086 CN202694547U (en) | 2012-06-04 | 2012-06-04 | Broadband coded signal detection circuit and wireless remote control signal decoding circuit thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616474A (en) * | 2015-02-13 | 2015-05-13 | 深圳市励创微电子有限公司 | Wireless remote control encoder chip and application circuit thereof |
| CN108958114A (en) * | 2018-07-12 | 2018-12-07 | 四川赛科安全技术有限公司 | It is built in MCU for realizing the hardware compression method of industrial bus communication |
-
2012
- 2012-06-04 CN CN 201220259086 patent/CN202694547U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616474A (en) * | 2015-02-13 | 2015-05-13 | 深圳市励创微电子有限公司 | Wireless remote control encoder chip and application circuit thereof |
| CN104616474B (en) * | 2015-02-13 | 2018-07-27 | 深圳市励创微电子有限公司 | Wireless remote control coding chip and its application circuit |
| CN108958114A (en) * | 2018-07-12 | 2018-12-07 | 四川赛科安全技术有限公司 | It is built in MCU for realizing the hardware compression method of industrial bus communication |
| CN108958114B (en) * | 2018-07-12 | 2020-03-24 | 四川赛科安全技术有限公司 | Hardware coding and decoding method built in MCU for realizing industrial bus communication |
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| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130123 Effective date of abandoning: 20140528 |
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| RGAV | Abandon patent right to avoid regrant |