CN202586873U - Frequency multiplier circuit and Bluetooth three dimensional glasses phase tester - Google Patents
Frequency multiplier circuit and Bluetooth three dimensional glasses phase tester Download PDFInfo
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- CN202586873U CN202586873U CN 201220224668 CN201220224668U CN202586873U CN 202586873 U CN202586873 U CN 202586873U CN 201220224668 CN201220224668 CN 201220224668 CN 201220224668 U CN201220224668 U CN 201220224668U CN 202586873 U CN202586873 U CN 202586873U
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Abstract
The utility model discloses a frequency multiplier circuit and a Bluetooth three dimensional glasses phase tester. The frequency multiplier circuit comprises a power supply input terminal, a signal input terminal, a signal output terminal, a first differentiating circuit, a first switch tube, a reverse circuit, a second differentiating circuit, a second switch tube and a first resistor, wherein an input terminal of the first differentiating circuit is connected with the signal input terminal, an output terminal of the first differentiating circuit is connected with the signal output terminal through the first switch tube, the signal input terminal is connected with an input terminal of the second differentiating circuit through the reverse circuit, an output terminal of the second differentiating circuit is connected with the signal output terminal through the second switch tube, and the signal output terminal is further connected with the power supply input terminal through the first resistor. According to the frequency multiplier circuit and the Bluetooth three dimensional glasses phase tester, frequency multiplication of a square signal to be carried out frequency multiplication is realized through a simple analog circuit; circuit cost is reduced; and a performance price ratio of the circuit is improved.
Description
Technical field
The utility model relates to the electronic circuit technology field, relates in particular to a kind of frequency multiplier circuit and bluetooth 3D glasses phase test appearance.
Background technology
Frequency multiplier circuit of the prior art has following several kinds usually: the frequency multiplication of frequency multiplication square-wave signal is realized treating in (1) through analog phase-locked look or digital phase-locked loop; The best performance of this frequency multiplication mode; But; This frequency multiplication mode normally adopts special-purpose frequency multiplication integrated circuit to realize, causes the cost of circuit higher.(2) realize treating the frequency multiplication of frequency multiplication square-wave signal through digital circuit.Yet this frequency multiplication mode need be used one or more logical devices usually, makes that the cost of circuit is not low yet.(3) through the cooperating of analog circuit and digital circuit, the frequency multiplication of frequency multiplication square-wave signal is treated in realization, and the flexibility of this frequency multiplication mode is good, but its circuit cost is also higher.
The utility model content
The main purpose of the utility model provides a kind of frequency multiplier circuit, is intended to treat through simple Realization of Analog Circuit the frequency multiplication of frequency multiplication square-wave signal, with cost that reduces circuit and the cost performance that improves circuit.
In order to achieve the above object; The utility model proposes a kind of frequency multiplier circuit; This frequency multiplier circuit comprises the power supply input that is used to provide supply power voltage, be used to import signal input part, the signal output part that is used to export the frequency multiplication square-wave signal of treating the frequency multiplication square-wave signal, be used for treating that with said the frequency multiplication square-wave signal carries out differential and handles; And export first pulse signal first differential circuit, be used for said first pulse signal convert into first square-wave signal first switching tube, be used for the said frequency multiplication square-wave signal of treating is carried out the negater circuit of reverse process, is used for said after the reverse process treated that the frequency multiplication square-wave signal carries out differential and handles; And export second pulse signal second differential circuit, be used for first resistance that said second pulse signal is converted into the second switch pipe of second square-wave signal and is used for the load of said first switching tube and said second switch pipe, wherein:
The input of said first differential circuit is connected with said signal input part; The output of said first differential circuit is connected with said signal output part through said first switching tube; Said signal input part also is connected through the input of said negater circuit with said second differential circuit; The output of said second differential circuit is connected with said signal output part through said second switch pipe, and said signal output part also is connected with said power supply input through said first resistance.
Preferably, said first switching tube is a NPN triode, and said second switch pipe is the 2nd NPN triode; The base stage of a said NPN triode is connected with the output of said first differential circuit; The base stage of said the 2nd NPN triode is connected with the output of said second differential circuit; The collector electrode of the collector electrode of a said NPN triode and said the 2nd NPN triode all is connected with said signal output part; And be connected the equal ground connection of emitter of the emitter of a said NPN triode and said the 2nd NPN triode with said power supply input through said first resistance.
Preferably, said first differential circuit comprises second resistance, the 3rd resistance and first electric capacity; One end of said second resistance is connected with said signal input part; The other end of said second resistance is connected with the base stage of a said NPN triode through said first electric capacity; One end of said the 3rd resistance is connected with the base stage of a said NPN triode, the other end ground connection of said the 3rd resistance.
Preferably, said negater circuit comprises the 4th resistance and the 3rd NPN triode; One end of said the 4th resistance is connected with said signal input part; The other end of said the 4th resistance is connected with the base stage of said the 3rd NPN triode; The grounded emitter of said the 3rd NPN triode, the collector electrode of said the 3rd NPN triode is connected with the input of said second differential circuit.
Preferably, said second differential circuit comprises the 5th resistance, the 6th resistance and second electric capacity; One end of said the 5th resistance is connected with said power supply input; The collector electrode of the 3rd NPN triode in the other end of said the 5th resistance and the said negater circuit is connected; And be connected with the base stage of said the 2nd NPN triode through said second electric capacity; One end of said the 6th resistance is connected with the base stage of said the 2nd NPN triode, the other end ground connection of said the 6th resistance.
Preferably, saidly treat that the duty ratio of frequency multiplication square-wave signal is 50%.
Preferably, the resistance of said first resistance, second resistance, the 4th resistance and the 5th resistance equates that all the resistance of said the 3rd resistance equates that greater than the resistance of said the 6th resistance the capacitance of said first electric capacity equals the capacitance of said second electric capacity.
Preferably, the delay time constant of said first differential circuit and said second differential circuit is equal to 1/4th of the said cycle of treating the frequency multiplication square-wave signal.
The utility model also proposes a kind of bluetooth 3D glasses phase test appearance; This bluetooth 3D glasses phase test appearance comprises frequency multiplier circuit; Said frequency multiplier circuit comprises the power supply input that is used to provide supply power voltage, be used to import signal input part, the signal output part that is used to export the frequency multiplication square-wave signal of treating the frequency multiplication square-wave signal, be used for treating that with said the frequency multiplication square-wave signal carries out differential and handles; And export first pulse signal first differential circuit, be used for said first pulse signal convert into first square-wave signal first switching tube, be used for the said frequency multiplication square-wave signal of treating is carried out the negater circuit of reverse process, is used for said after the reverse process treated that the frequency multiplication square-wave signal carries out differential and handles; And export second pulse signal second differential circuit, be used for first resistance that said second pulse signal is converted into the second switch pipe of second square-wave signal and is used for the load of said first switching tube and said second switch pipe, wherein:
The input of said first differential circuit is connected with said signal input part; The output of said first differential circuit is connected with said signal output part through said first switching tube; Said signal input part also is connected through the input of said negater circuit with said second differential circuit; The output of said second differential circuit is connected with said signal output part through said second switch pipe, and said signal output part also is connected with said power supply input through said first resistance.
The frequency multiplier circuit that the utility model proposes; Treat that to what signal input part was imported the frequency multiplication square-wave signal carries out differential and handles through first differential circuit; And the signal behind the differential is exported to the base stage of a NPN triode; Through a negater circuit the above-mentioned frequency multiplication square-wave signal of treating is carried out reverse process simultaneously; And the frequency multiplication square-wave signal of treating after will be reverse exports second differential circuit to, and second differential circuit treats that the frequency multiplication square-wave signal carries out differential and handles to this after reverse, and exports the signal behind the differential base stage of the 2nd NPN triode to; At last the collector signal of a NPN triode is carried out and processing with the collector signal of the 2nd NPN triode, realize the frequency multiplication of treating the frequency multiplication square-wave signal that signal input part is imported.The utility model frequency multiplier circuit through simple Realization of Analog Circuit treat the frequency multiplication of frequency multiplication square-wave signal, reduced the cost of circuit, improved the cost performance of circuit.
Description of drawings
Fig. 1 is the electrical block diagram of the utility model frequency multiplier circuit preferred embodiment;
Fig. 2 is the oscillogram of treating the frequency multiplication square-wave signal that signal input part is imported in the preferred embodiment of the utility model frequency multiplier circuit;
Fig. 3 is the signal waveforms that the output of first differential circuit in the preferred embodiment of the utility model frequency multiplier circuit is exported;
Fig. 4 is the signal waveforms that the output of negater circuit in the preferred embodiment of the utility model frequency multiplier circuit is exported;
Fig. 5 is the signal waveforms that the output of second differential circuit in the preferred embodiment of the utility model frequency multiplier circuit is exported;
Fig. 6 is the signal waveforms that signal output part is exported in the preferred embodiment of the utility model frequency multiplier circuit.
The realization of the utility model purpose, functional characteristics and advantage will combine embodiment, further specify with reference to accompanying drawing.
Embodiment
Further specify the technical scheme of the utility model below in conjunction with Figure of description and specific embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Fig. 1 is the electrical block diagram of the utility model frequency multiplier circuit preferred embodiment.
With reference to Fig. 1, the utility model frequency multiplier circuit comprises power supply input 101, signal input part 102, signal output part 103, first differential circuit 104, negater circuit 105, second differential circuit 106, first switching tube 107, second switch pipe 108, first resistance R 1.
Wherein, The input of first differential circuit 104 is connected with signal input part 102; The output of first differential circuit 104 is connected with signal output part 103 through first switching tube 107; Signal input part 102 also is connected through the input of negater circuit 105 with second differential circuit 106, and the output of second differential circuit 106 is connected with signal output part 103 through second switch pipe 108, and signal output part 103 also is connected with power supply input 101 through first resistance R 1.
Particularly; The base stage of the one NPN triode Q1 is connected with the output of first differential circuit 104; The base stage of the 2nd NPN triode Q2 is connected with the output of second differential circuit 106; The collector electrode of the collector electrode of the one NPN triode Q1 and the 2nd NPN triode Q2 all is connected with signal output part 103, and is connected the equal ground connection of emitter of the emitter of a NPN triode Q1 and the 2nd NPN triode Q2 with power supply input 101 through first resistance R 1.Wherein, first resistance R 1 is the common load of a NPN triode Q1 and the 2nd NPN triode Q2.
Among the utility model embodiment, first differential circuit 104 comprises second resistance R 2, the 3rd resistance R 3 and first capacitor C 1.One end of second resistance R 2 is connected with signal input part 102; The other end of second resistance R 2 is connected with the base stage of a NPN triode Q1 through first capacitor C 1; One end of the 3rd resistance R 3 is connected with the base stage of a NPN triode Q1, the other end ground connection of the 3rd resistance R 3;
Negater circuit 105 comprises the 4th resistance R 4 and the 3rd NPN triode Q3.One end of the 4th resistance R 4 is connected with signal input part 102; The other end of the 4th resistance R 4 is connected with the base stage of the 3rd NPN triode Q3; The grounded emitter of the 3rd NPN triode Q3, the collector electrode of the 3rd NPN triode Q3 is connected with the input of second differential circuit 106;
Second differential circuit 106 comprises the 5th resistance R 5, the 6th resistance R 6 and second capacitor C 2.One end of the 5th resistance R 5 is connected with power supply input 101; The collector electrode of the 3rd NPN triode Q3 in the other end of the 5th resistance R 5 and the negater circuit 105 is connected; And be connected with the base stage of the 2nd NPN triode Q2 through second capacitor C 2; One end of the 6th resistance R 6 is connected with the base stage of the 2nd NPN triode Q2, the other end ground connection of the 6th resistance R 6.
The operation principle of the utility model frequency multiplier circuit specifically describes as follows: power supply input 101 is used to the entire circuit system supply power voltage is provided; Signal input part 102 is used for input and treats the frequency multiplication square-wave signal; Signal output part 103 is used to export the frequency multiplication square-wave signal; First differential circuit 104 is used to treat the frequency multiplication square-wave signal and carries out the differential processing, and exports the base stage that first pulse signal is given a NPN triode Q1; The one NPN triode Q1 is used for converting first pulse signal that its base stage is imported into first square-wave signal (collector signal of a NPN triode Q1); The voltage of promptly importing when the base stage of a NPN triode Q1 is during greater than 0.7V; Its collector electrode output low level signal then; The voltage of importing when the base stage of a NPN triode Q1 is during less than 0.7V, then its collector electrode output high level signal; Negater circuit 105 is used for 102 inputs of signal input part are treated that the frequency multiplication square-wave signal carries out reverse process (rising edge and the trailing edge that are about to treat the frequency multiplication square-wave signal are to falling), obtains one and treats frequency multiplication square-wave signal (being that shown by reference numeral is the signal at a point place) after reverse; Second differential circuit 106 is used for the frequency multiplication square-wave signal of treating after reverse is carried out the differential processing, and exports the base stage that second pulse signal is given the 2nd NPN triode Q2; The 2nd NPN triode Q2 is used for converting second pulse signal that its base stage is imported into second square-wave signal (collector signal of the 2nd NPN triode Q2); The voltage of promptly importing when the base stage of the 2nd NPN triode Q2 is during greater than 0.7V; Its collector electrode output low level signal then; The voltage of importing when the base stage of the 2nd NPN triode Q2 is during less than 0.7V, then its collector electrode output high level signal.At last; First square-wave signal through the collector electrode of a NPN triode Q1 is exported carries out and processing with second square-wave signal that the collector electrode of the 2nd NPN triode Q2 is exported; Promptly as long as the signal that the collector electrode of one of them triode (a NPN triode Q1 or the 2nd NPN triode Q2) is exported is a low level; Then the signal exported of the collector electrode of another triode (the 2nd a NPN triode Q2 or a NPN triode Q1) is no matter be high level or low level; The signal that signal output part 103 is exported all is a low level, thereby makes that frequency of signal output part 103 outputs is the frequency multiplication square-wave signal that 2 times of frequency multiplication square-wave signal frequencies are treated in 102 inputs of signal input part.
The utility model embodiment is on the type selecting of device, and first resistance R 1, second resistance R 2, the 4th resistance R 4 and the 5th resistance R 5 can be chosen the same resistance (such as 10K).First capacitor C 1 can be chosen the same capacitance (such as 330nF) with second capacitor C 2.The 3rd resistance R 3 can be chosen the same resistance with the 6th resistance R 6; But; The resistance of the 3rd resistance R 3 and the 6th resistance R 6 will change along with the change of the frequency of treating the frequency multiplication square-wave signal, if treat that the frequency of frequency multiplication square-wave signal is lower, then can not change the capacitance of first capacitor C 1; And only change the resistance of the 3rd resistance R 3, to adjust the delay time constant of first differential circuit 104.In like manner, also can not change the capacitance of second capacitor C 2, and only change the resistance of the 6th resistance R 6, to adjust the delay time constant of second differential circuit 106.Generally, the resistance of the 3rd resistance R 3 is larger than the resistance of the 6th resistance R 6.And; If treat that the frequency of frequency multiplication square-wave signal is high more, the resistance of the 3rd resistance R 3 and the 6th resistance R 6 also will diminish simultaneously, yet; Because the driving force that less the 6th resistance R 6 and the 3rd resistance R 3 can influence behind the circuit grade; Therefore, also can adopt the 3rd bigger resistance R 3 and the 6th resistance R 6, through changing the capacitance of first capacitor C 1 and second capacitor C 2; To realize changing respectively the delay time constant of first differential circuit 104 and the delay time constant of second differential circuit 106 (frequency of treating the frequency multiplication square-wave signal is high more, and then relevant capacitance value is more little).
In addition; Need to prove; The frequency multiplier circuit that the utility model embodiment is provided; The duty ratio of treating the frequency multiplication square-wave signal that its signal input part 102 is imported is required to be 50%; And the utility model frequency multiplier circuit realizes that the key of frequency multiplication is to adjust the parameter of corresponding device in first differential circuit 104 and second differential circuit 106, makes the delay time constant of the win differential circuit 104 and second differential circuit 106 be 1/4th of cycle of treating the frequency multiplication square-wave signal that signal input part 102 imported.In order to make reasonable frequency multiplication square-wave signal of waveform of signal output part 103 outputs; Can before signal output part 103, increase some waveform shaping circuits; The centre yet can increase amplifying circuit; With the waveform of the frequency multiplication square-wave signal that improves signal output part 103 output, make the more precipitous ideal of its waveform.
Fig. 2 is the oscillogram of treating the frequency multiplication square-wave signal that signal input part is imported in the preferred embodiment of the utility model frequency multiplier circuit.As shown in Figure 2; The duty ratio of treating frequency multiplication square-wave signal (shown by reference numeral is Vin) that signal input part 102 is imported among the utility model embodiment is 50%; When these duty ratios of signal input part 102 input be 50% treat the frequency multiplication square-wave signal after; The signal (shown by reference numeral is VQ1_b) of the output of first differential circuit 104 (i.e. the base stage of a NPN triode Q1) is as shown in Figure 3; With reference to Fig. 3, the signal of the output of first differential circuit 104 among the utility model embodiment (i.e. the base stage of a NPN triode Q1) is first pulse signal.After first pulse signal shown in Figure 3 being inputed to the base stage of a NPN triode Q1; The one NPN triode Q1 does not respond (i.e. not conducting) to negative level, and will be greater than 0.7V and the positive level that descends gradually convert the positive pulse from low to high of 1/4th width in the frequency multiplication square-wave signal cycle of treating that signal input part 102 imported into.
Fig. 4 is the signal waveforms that the output of negater circuit in the preferred embodiment of the utility model frequency multiplier circuit is exported.As shown in Figure 4; The signal (shown by reference numeral is Va) that the output of negater circuit 105 among the utility model embodiment (i.e. the collector electrode of the 3rd NPN triode Q3) is exported is treated the waveform (rising edge that is about to treat the frequency multiplication square-wave signal with trailing edge to) of frequency multiplication square-wave signal for shown in Figure 2 after reverse; After should be reverse treat that the frequency multiplication square-wave signal is handled through the differential of second differential circuit 106 after; Export signal waveform as shown in Figure 5; With reference to Fig. 5, the signal (shown by reference numeral is VQ2_b) of the output of second differential circuit 106 among the utility model embodiment (i.e. the base stage of the 2nd NPN triode Q2) is similarly second pulse signal.In like manner; After second pulse signal shown in Figure 5 being inputed to the base stage of the 2nd NPN triode Q2; The 2nd NPN triode Q2 does not respond (i.e. not conducting) to negative level, and will be greater than 0.7V and the positive level that descends gradually convert the positive pulse from low to high of 1/4th width in the frequency multiplication square-wave signal cycle of treating that signal input part 102 imported into.Thereby make the utility model frequency multiplier circuit treat to rise to after the delay in frequency multiplication square-wave signal cycle 1/4 action of high level respectively at the rising edge of treating the frequency multiplication square-wave signal shown in Figure 2 and trailing edge; Just having formed frequency is to treat the frequency multiplication square-wave signal of 2 times of frequency multiplication square-wave signal frequencies (shown by reference numeral is Vout), and the waveform of this frequency multiplication square-wave signal is as shown in Figure 6.
The frequency multiplier circuit that the utility model proposes; Treat that to what signal input part was imported the frequency multiplication square-wave signal carries out differential and handles through first differential circuit; And the signal behind the differential is exported to the base stage of a NPN triode; Through a negater circuit the above-mentioned frequency multiplication square-wave signal of treating is carried out reverse process simultaneously; And the frequency multiplication square-wave signal of treating after will be reverse exports second differential circuit to, and second differential circuit treats that the frequency multiplication square-wave signal carries out differential and handles to this after reverse, and exports the signal behind the differential base stage of the 2nd NPN triode to; At last the collector signal of a NPN triode is carried out and processing with the collector signal of the 2nd NPN triode, realize the frequency multiplication of treating the frequency multiplication square-wave signal that signal input part is imported.The utility model frequency multiplier circuit through simple Realization of Analog Circuit treat the frequency multiplication of frequency multiplication square-wave signal, reduced the cost of circuit, improved the cost performance of circuit.
The utility model also proposes a kind of bluetooth 3D glasses phase test appearance, and this bluetooth 3D glasses phase test appearance comprises frequency multiplier circuit, and the circuit structure of its frequency multiplier circuit is identical with the circuit structure of the described frequency multiplier circuit of top embodiment, repeats no more here.
The above is merely the preferred embodiment of the utility model; Be not thus the restriction the utility model claim; Every equivalent structure or equivalent flow process conversion that utilizes the utility model specification and accompanying drawing content to be done; Or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the utility model.
Claims (9)
1. frequency multiplier circuit; Comprise and be used to provide the power supply input of supply power voltage, the signal output part that is used to import the signal input part of treating the frequency multiplication square-wave signal and is used to export the frequency multiplication square-wave signal; It is characterized in that; Also comprise and be used for treating that with said the frequency multiplication square-wave signal carries out differential and handles; And export first pulse signal first differential circuit, be used for said first pulse signal convert into first square-wave signal first switching tube, be used for the said frequency multiplication square-wave signal of treating is carried out the negater circuit of reverse process, is used for said after the reverse process treated that the frequency multiplication square-wave signal carries out differential and handles; And export second pulse signal second differential circuit, be used for first resistance that said second pulse signal is converted into the second switch pipe of second square-wave signal and is used for the load of said first switching tube and said second switch pipe, wherein:
The input of said first differential circuit is connected with said signal input part; The output of said first differential circuit is connected with said signal output part through said first switching tube; Said signal input part also is connected through the input of said negater circuit with said second differential circuit; The output of said second differential circuit is connected with said signal output part through said second switch pipe, and said signal output part also is connected with said power supply input through said first resistance.
2. frequency multiplier circuit according to claim 1 is characterized in that, said first switching tube is a NPN triode, and said second switch pipe is the 2nd NPN triode; The base stage of a said NPN triode is connected with the output of said first differential circuit; The base stage of said the 2nd NPN triode is connected with the output of said second differential circuit; The collector electrode of the collector electrode of a said NPN triode and said the 2nd NPN triode all is connected with said signal output part; And be connected the equal ground connection of emitter of the emitter of a said NPN triode and said the 2nd NPN triode with said power supply input through said first resistance.
3. frequency multiplier circuit according to claim 2 is characterized in that, said first differential circuit comprises second resistance, the 3rd resistance and first electric capacity; One end of said second resistance is connected with said signal input part; The other end of said second resistance is connected with the base stage of a said NPN triode through said first electric capacity; One end of said the 3rd resistance is connected with the base stage of a said NPN triode, the other end ground connection of said the 3rd resistance.
4. according to claim 1,2 or 3 described frequency multiplier circuits, it is characterized in that said negater circuit comprises the 4th resistance and the 3rd NPN triode; One end of said the 4th resistance is connected with said signal input part; The other end of said the 4th resistance is connected with the base stage of said the 3rd NPN triode; The grounded emitter of said the 3rd NPN triode, the collector electrode of said the 3rd NPN triode is connected with the input of said second differential circuit.
5. frequency multiplier circuit according to claim 4 is characterized in that, said second differential circuit comprises the 5th resistance, the 6th resistance and second electric capacity; One end of said the 5th resistance is connected with said power supply input; The collector electrode of the 3rd NPN triode in the other end of said the 5th resistance and the said negater circuit is connected; And be connected with the base stage of said the 2nd NPN triode through said second electric capacity; One end of said the 6th resistance is connected with the base stage of said the 2nd NPN triode, the other end ground connection of said the 6th resistance.
6. frequency multiplier circuit according to claim 5 is characterized in that, saidly treats that the duty ratio of frequency multiplication square-wave signal is 50%.
7. frequency multiplier circuit according to claim 6; It is characterized in that; The resistance of said first resistance, second resistance, the 4th resistance and the 5th resistance all equates; The resistance of said the 3rd resistance equates that greater than the resistance of said the 6th resistance the capacitance of said first electric capacity equals the capacitance of said second electric capacity.
8. frequency multiplier circuit according to claim 7 is characterized in that, the delay time constant of said first differential circuit and said second differential circuit is equal to 1/4th of the said cycle of treating the frequency multiplication square-wave signal.
9. a bluetooth 3D glasses phase test appearance is characterized in that, comprises each described frequency multiplier circuit among the claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220224668 CN202586873U (en) | 2012-05-18 | 2012-05-18 | Frequency multiplier circuit and Bluetooth three dimensional glasses phase tester |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220224668 CN202586873U (en) | 2012-05-18 | 2012-05-18 | Frequency multiplier circuit and Bluetooth three dimensional glasses phase tester |
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| CN202586873U true CN202586873U (en) | 2012-12-05 |
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| CN 201220224668 Expired - Fee Related CN202586873U (en) | 2012-05-18 | 2012-05-18 | Frequency multiplier circuit and Bluetooth three dimensional glasses phase tester |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346736A (en) * | 2013-05-24 | 2013-10-09 | 中国电子科技集团公司第四十一研究所 | Broadband high-power 1-mm solid-state signal source system |
| CN109302177A (en) * | 2018-11-27 | 2019-02-01 | 国网上海市电力公司 | A kind of digital feedback precision square wave phase shifter based on two frequency multiplication two divided-frequencies |
-
2012
- 2012-05-18 CN CN 201220224668 patent/CN202586873U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346736A (en) * | 2013-05-24 | 2013-10-09 | 中国电子科技集团公司第四十一研究所 | Broadband high-power 1-mm solid-state signal source system |
| CN103346736B (en) * | 2013-05-24 | 2016-09-07 | 中国电子科技集团公司第四十一研究所 | A kind of broadband high-power 1mm solid-state signal source system |
| CN109302177A (en) * | 2018-11-27 | 2019-02-01 | 国网上海市电力公司 | A kind of digital feedback precision square wave phase shifter based on two frequency multiplication two divided-frequencies |
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Granted publication date: 20121205 Termination date: 20200518 |