CN202548833U - High-speed transmission controllable management serial protocol PCIE (peripheral component interface express) bus - Google Patents
High-speed transmission controllable management serial protocol PCIE (peripheral component interface express) bus Download PDFInfo
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- CN202548833U CN202548833U CN2011205324761U CN201120532476U CN202548833U CN 202548833 U CN202548833 U CN 202548833U CN 2011205324761 U CN2011205324761 U CN 2011205324761U CN 201120532476 U CN201120532476 U CN 201120532476U CN 202548833 U CN202548833 U CN 202548833U
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- pcie
- interface
- bus
- golden finger
- serial
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Abstract
The utility model discloses a high-speed transmission controllable management serial protocol PCIE (peripheral component interface express) bus which comprises a main board. A south bridge of the main board is connected with a PCIE-X1 golden finger, the PCIE-X1 golden finger is respectively connected with a USB (universal serial bus) interface, an SATA (serial advanced technology attachment) hard disk interface, a POWER/HDD indicating lamp and an RS232 serial interface. Particularly, the PCIE-X1 golden finger is connected with the USB interface through a USB bus, connected with the SATA hard disk interface through an SATA bus, connected with the POWER/HDD indicating lamp through an LED connecting line, and connected with the RS232 serial interface through a COM connecting line. By means of structural improvement, common interfaces are combined, cost can be effectively saved, installation and maintenance are facilitated, structural fault points are decreased, installation time can be saved, and working efficiency is improved.
Description
Technical field
The utility model relates to the bus interface technology field, concrete relates to a kind of high-speed transfer controllable management serial protocol PCIE bus.
Background technology
Industrial computer has a lot of buses commonly used, and wherein main type is: SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment, a kind of serial hardware driver interface based on industry standard); USB (Universal Serial BUS, USB); COM (serial ports) etc.Because bus commonly used is a lot, its corresponding interface specification is also a lot, so if will use a plurality of interfaces simultaneously, the wiring meeting of equipment increases, the trouble spot of physics also can be along with increase simultaneously, and then causes material cost to rise and problems such as maintenance cost increase.
The utility model content
The purpose of the utility model is to solve the problem that exists in the prior art, and a kind of functional multi-usage high-speed transfer controllable management serial protocol PCIE bus is provided.
The utility model is achieved through following technical scheme:
High-speed transfer controllable management serial protocol PCIE bus comprises mainboard, and mainboard is provided with the mainboard south bridge, and the mainboard south bridge is connected with the PCIE-X1 golden finger.
Wherein, the PCIE-X1 golden finger links to each other with USB interface, SATA hard-disk interface, POWER/HDD pilot lamp and RS232 serial interface respectively.
Concrete, link to each other through usb bus between PCIE-X1 golden finger and the USB interface.
Link to each other through the SATA bus between PCIE-X1 golden finger and the SATA hard-disk interface.
Link to each other through the LED connecting line between PCIE-X1 golden finger and the POWER/HDD pilot lamp.
Link to each other through the COM connecting line between PCIE-X1 golden finger and the RS232 serial interface.
The utility model usefulness is:
The utility model merges common interfaces through architecture advances, can effectively practice thrift cost, is convenient to installation and maintenance simultaneously, has reduced structural trouble spot, can practice thrift the set-up time, increases work efficiency.
Description of drawings
To combine embodiment and accompanying drawing that the utility model is done further to describe in detail below:
Fig. 1 is the system architecture synoptic diagram of the utility model.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Be illustrated in figure 1 as the high-speed transfer controllable management serial protocol PCIE bus of the utility model, comprise mainboard, mainboard is provided with the mainboard south bridge, and the mainboard south bridge is connected with the PCIE-X1 golden finger.
Wherein, the utility model is integrated in PCIE X1 interface with SATA, USB, COM and LED.
Concrete, link to each other with USB interface, SATA hard-disk interface, POWER/HDD pilot lamp and RS232 serial interface respectively through the PCIE-X1 golden finger.
Further, link to each other through usb bus between PCIE-X1 golden finger and the USB interface.
Link to each other through the SATA bus between PCIE-X1 golden finger and the SATA hard-disk interface.
Link to each other through the LED connecting line between PCIE-X1 golden finger and the POWER/HDD pilot lamp.
Link to each other through the COM connecting line between PCIE-X1 golden finger and the RS232 serial interface.
The utility model merges above-mentioned common interfaces through Structure Conversion, has effectively reached the creation purpose.
Claims (5)
1. high-speed transfer controllable management serial protocol PCIE bus comprises mainboard, it is characterized in that mainboard is provided with the mainboard south bridge, and the mainboard south bridge is connected with the PCIE-X1 golden finger; Wherein, the PCIE-X1 golden finger links to each other with USB interface, SATA hard-disk interface, POWER/HDD pilot lamp and RS232 serial interface respectively.
2. high-speed transfer controllable management serial protocol PCIE bus according to claim 1 is characterized in that linking to each other through usb bus between described PCIE-X1 golden finger and the USB interface.
3. high-speed transfer controllable management serial protocol PCIE bus according to claim 1 is characterized in that linking to each other through the SATA bus between described PCIE-X1 golden finger and the SATA hard-disk interface.
4. high-speed transfer controllable management serial protocol PCIE bus according to claim 1 is characterized in that linking to each other through the LED connecting line between described PCIE-X1 golden finger and the POWER/HDD pilot lamp.
5. high-speed transfer controllable management serial protocol PCIE bus according to claim 1 is characterized in that linking to each other through the COM connecting line between described PCIE-X1 golden finger and the RS232 serial interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205324761U CN202548833U (en) | 2011-12-19 | 2011-12-19 | High-speed transmission controllable management serial protocol PCIE (peripheral component interface express) bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205324761U CN202548833U (en) | 2011-12-19 | 2011-12-19 | High-speed transmission controllable management serial protocol PCIE (peripheral component interface express) bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202548833U true CN202548833U (en) | 2012-11-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205324761U Expired - Fee Related CN202548833U (en) | 2011-12-19 | 2011-12-19 | High-speed transmission controllable management serial protocol PCIE (peripheral component interface express) bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202548833U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107729274A (en) * | 2017-09-15 | 2018-02-23 | 郑州云海信息技术有限公司 | It is a kind of to realize PCIEx1 connectors and the circuit and method of NVME SSD interconnections |
-
2011
- 2011-12-19 CN CN2011205324761U patent/CN202548833U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107729274A (en) * | 2017-09-15 | 2018-02-23 | 郑州云海信息技术有限公司 | It is a kind of to realize PCIEx1 connectors and the circuit and method of NVME SSD interconnections |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN HOLL INTELLIGENT TECHNOLOGY CO., LTD. Free format text: FORMER NAME: SHENZHEN WEIDA HOLL TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 518052 Guangdong city of Shenzhen province Nanshan District two pass road forward hot electrons strategic emerging industrial park 20 floor to four floor Patentee after: SHENZHEN HOLL INTELLIGENT TECHNOLOGY CO., LTD. Address before: 27 B room, 2 floor, two industrial zone, Shenzhen Road, Nantou, Nanshan District, Guangdong 518052, China Patentee before: Holl IPC Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121121 Termination date: 20161219 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |