CN206225359U - A kind of integrated circuit sealing ring - Google Patents
A kind of integrated circuit sealing ring Download PDFInfo
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- CN206225359U CN206225359U CN201621285071.1U CN201621285071U CN206225359U CN 206225359 U CN206225359 U CN 206225359U CN 201621285071 U CN201621285071 U CN 201621285071U CN 206225359 U CN206225359 U CN 206225359U
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- sealing ring
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Abstract
The utility model provides a kind of integrated circuit sealing ring, including：Substrate layer；It is formed at the doped region in the substrate layer；The dielectric layer and the laminated construction of metal level being formed on the doped region, each metal level and the doped region are realized being electrically connected with by connecting hole；And, the capacitor in the laminated construction is formed at, first pole plate and the second pole plate of the capacitor are connected by the metal level in the laminated construction and the metal level in buffering area with substrate and internal circuit respectively.Integrated circuit sealing ring of the present utility model is not influenceing integrated circuit area, also in the case of not changing the function and performance of sealing ring, improved in the structure of existing integrated circuit sealing ring, made integrated circuit while meeting the density requirements of polysilicon and increasing filter function.
Description
Technical field
The utility model is related to field of semiconductor manufacture, more particularly to a kind of integrated circuit sealing ring.
Background technology
In semiconductor fabrication process, can be formed on a semiconductor substrate by techniques such as photoetching, etching and depositions
Semiconductor chip including semiconductor active device and the interconnection structure being arranged on device.Generally, can on wafer
To form multiple chips, these chips are cut down from wafer again finally, by packaging technology, form integrated circuit.
During diced chip, the stress produced by cutting blade can cause damage to the edge of chip, or even meeting
Chip is caused to burst apart.In the prior art, in order to prevent chip from being sustained damage in cutting, in lsi internal circuit
Active device area periphery sets sealing ring, and the sealing ring can stop that the stress that cutting blade is produced causes active device area
Undesired stress fracture, and the sealing ring of chip can stop the influence that steam infiltration and ionic soil are caused.
As shown in figure 1, the buffering area of ring-type is provided between sealing ring and active device region, to form active device region
To the excessive of sealing ring, the periphery of sealing ring is provided with the scribe line for splitting chip.It is illustrated in figure 2 and is cut along AA ' directions
The vertical structure figure of increasing back sealing ring, including substrate 100 are cut, the substrate can be P-type material substrate or n type material substrate；It is described
Same type impurity of the concentration higher than backing material is doped with substrate 100, to form doped region 101；And be formed at described
The laminated construction of dielectric layer and metal level on doped region 101.In the present embodiment, from P type substrate and p-type heavily doped region,
The doped region is used to reduce sealing ring with the contact resistance between wafer substrate；M1, M2, M3 are respectively the first metal layer, the
Two metal levels, the 3rd metal level, with the complexity in circuits of integrated circuit, metal level can be more than three layers, and commonly referred to as it is most
Upper strata is top layer metallic layer；102a, 102b, 102c are dielectric layer, in integrated circuits for the adjacent metal that insulate；First gold medal
Contact hole between category layer M1 and doped region 101 is C, and the contact hole between the first metal layer M1 and second metal layer M2 is V1,
Contact hole between second metal layer M2 and the 3rd metal level M3 is V2, by that analogy.
Sealing ring is generally made up of metal level-metal throuth hole layer-active area, without polysilicon structure, with big width
May be difficult to meet polysilicon density requirements in the integrated circuit of the protection ring of degree, during chemical-mechanical polishing (CMP) is operated
Uneven inclusion can be caused.
In integrated circuit design, generally require and use MOS (metal-oxide semiconductor (MOS)) transistor capacitances or PIP
(Poly-Insolator-Poly polysilicon-insulating layer-polysilicons) electric capacity or MIM (Metal-Insolator-Metal, gold
Category-insulator-metal) electric capacity, the two ends of electric capacity connect the low potential on high potential and the integrated circuit ground in integrated circuit, use respectively
In filtering, high frequency small-signal subsidiary on high potential is leached, reduce its exchange ripple coefficient, lift the stability of circuit.Due to
The capacitance of per unit square is not very big in integrated circuit, and general representative value is micro- to every square of 5fF per square micron in 0.5fF
Between rice, therefore, above-mentioned filter capacitor can take certain integrated circuit area, bring the increase of cost.
Therefore, how to solve the problems, such as that polysilicon density requirements and electric capacity the occupancy chip area of sealing ring are big simultaneously,
As one of those skilled in the art's problem demanding prompt solution.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of integrated circuit sealing
Ring, for solve sealing ring in the prior art be unsatisfactory for polysilicon density requirements and electric capacity take chip area it is big the problems such as.
In order to achieve the above objects and other related objects, the utility model provides a kind of integrated circuit sealing ring, the collection
At least include into circuit sealing ring：
Substrate layer；
It is formed at the doped region in the substrate layer；
The dielectric layer and the laminated construction of metal level being formed on the doped region, each metal level and the doped region pass through
Connecting hole is realized being electrically connected with；
And,
The capacitor in the laminated construction is formed at, first pole plate and the second pole plate of the capacitor pass through institute respectively
State the metal level in laminated construction and the metal level in buffering area is connected with substrate and internal circuit.
Preferably, the substrate layer is P type substrate, and the doped region adulterates for p-type.
Preferably, the substrate layer is N-type substrate, and the doped region is n-type doping.
Preferably, the capacitor is mos capacitance, and the first pole plate of the capacitor is to be formed at the doped region and institute
The first polysilicon between the bottom metal layer in laminated construction is stated, the second pole plate of the capacitor is the doped region.
Preferably, the capacitor is PIP capacitor, and first pole plate and the second pole plate of the capacitor are described to be formed at
In laminated construction between arbitrary neighborhood two metal layers, or it is formed at the underlying metal in the doped region and the laminated construction
The second polysilicon and the 3rd polysilicon between layer, second polysilicon and the 3rd polysilicon vertical distribution.
Preferably, the capacitor is MIM capacitor, and the first pole plate of the capacitor is to be formed in the laminated construction
Metallic plate between arbitrary neighborhood two metal layers, the second pole plate of the capacitor in the laminated construction with the metal
The neighbouring metal level of plate.
Preferably, the material of the dielectric layer is silica or silicon nitride.
Preferably, the material of the metal level is copper or aluminium.
As described above, integrated circuit sealing ring of the present utility model, has the advantages that：
Integrated circuit sealing ring of the present utility model increase in the structure of existing integrated circuit sealing ring polysilicon or
Metallic plate, to form capacitor, in the case where integrated circuit area is not influenceed, the density for making integrated circuit meet polysilicon is wanted
Ask, it is to avoid caused uneven surface envelope during chemical-mechanical polishing operation；It is not take up extra domain and increases electricity simultaneously
Hold.
Brief description of the drawings
Fig. 1 is shown as the schematic top plan view of sealing ring of the prior art.
Fig. 2 is shown as the schematic cross-sectional view of sealing ring of the prior art.
Fig. 3 is shown as a kind of implementation method of sealing ring of the present utility model.
Fig. 4 is shown as the schematic top plan view of sealing ring of the present utility model.
Fig. 5 is shown as the another embodiment of sealing ring of the present utility model.
Fig. 6 is shown as another implementation method of sealing ring of the present utility model.
Component label instructions
100 substrates
101 doped regions
102a~102c dielectric layers
M1~M3 first~the 3rd metal level
200 substrate layers
201 doped regions
202a~202c first~the 3rd dielectric layer
203a~203c first~the 3rd polysilicon
204 metallic plates
Specific embodiment
Implementation method of the present utility model is illustrated below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages of the present utility model and effect easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Refer to Fig. 3~Fig. 6.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, when only display is with relevant component in the utility model rather than according to actual implementation in schema then
Component count, shape and size are drawn, and the kenel of each component, quantity and ratio can be a kind of random changing during its actual implementation
Become, and its assembly layout kenel be likely to it is increasingly complex.
Embodiment one
As shown in figure 3, the utility model provides a kind of integrated circuit sealing ring, the integrated circuit sealing ring is at least wrapped
Include：
Substrate layer 200, the doped region 201 being formed in the substrate layer 200, Jie being formed on the doped region 201
The laminated construction of matter layer and metal level, and it is formed at the capacitor in the laminated construction.
As shown in figure 3, the substrate layer 200 is P-type material substrate or n type material substrate, and in the present embodiment, the lining
The material of bottom 200 is P-type material, i.e., mix the triads such as boron in the semiconductors；And n type material is then to mix in the semiconductors
Enter the pentads such as phosphorus.
As shown in figure 3, the doped region 201 is formed at the top layer of the substrate layer 200, by the substrate layer 200
In heavy doping is carried out to form the doped region 201, the doping of the Doped ions of the doped region 201 and the substrate layer 200
Ion is identical, and the concentration of Doped ions is adulterated more than the concentration of Doped ions in the substrate layer 200 in the doped region 201
The species of ion be able to can also be differed with identical.In the present embodiment, the doped region 201 be p-type heavy doping, and adulterate from
The species of the sub Doped ions with the substrate layer 200 is identical.The doped region 201 can reduce the laminated construction with it is described
Contact resistance between substrate layer 200.
As shown in figure 3, the upper strata of the doped region 201 is first medium layer 202a, the first medium layer 202a's is upper
Layer is second dielectric layer 202b for the upper strata of the first metal layer M1, the first metal layer M1, the second dielectric layer 202b's
Upper strata is the 3rd dielectric layer 202c, the 3rd dielectric layer 202c for the upper strata of second metal layer M2, the second metal layer M2
Upper strata for the 3rd metal level M3 ... dielectric layers and metal level constantly alternate setting forming laminated construction, the laminated construction
The number of plies of dielectric layer and metal level determines by the complexity in circuits of integrated circuit, in the present embodiment, is set as 3 layers of medium
Layer and 3 layers of metal level.The material of each dielectric layer is silica or silicon nitride；The material of each metal level is copper or aluminium；In this reality
Apply in example, the material of each dielectric layer is silica, and the material of each metal level is copper, and those skilled in the art can be according to design
Need, from different materials, not to be limited with the present embodiment.
The doped region 201 is realized being electrically connected with the first metal layer M1 by connecting hole C；The first metal layer
The M1 and second metal layer M2 realizes being electrically connected with by connecting hole V1；The second metal layer M2 and the 3rd metal level
M3 realizes being electrically connected with by connecting hole V3 ... similarly realizes electric connection between each metal level by connecting hole.
As shown in figure 3, being formed with the first polysilicon in the first medium layer 202a of the top of the doped region 201
203a.The first polysilicon 203a forms mos capacitance, first polysilicon with the region that the doped region 201 is overlapped
203a and the doped region 201 respectively as capacitor the first pole plate and the second pole plate, the capacity of capacitor and described first
The distance between polysilicon 203a and the doped region 201 are relevant.In the present embodiment, the doped region 201 is used as capacitor
Bottom crown, be electrically connected with the substrate layer 200；The first polysilicon 203a as capacitor top crown, by even
Meet hole C to be connected with the first metal layer M1 of buffering area, the first metal layer M1 is connected with second metal layer M2 by connecting hole V1, respectively
Metal level passes sequentially through through hole and realizes being electrically connected with, the first polysilicon 203a can by the metal level in the buffering area and
Through hole is connected with the metal level of the random layer of the active device region, and then realizes the connection with active device, plays to inside
Filtering, energy storage of circuit etc. are acted on.
As shown in figure 4, the area of the capacitor can do further restriction according to design requirement, do not limit one by one herein.
When as filter capacitor, because filter capacitor is needed according to the different capacitance of Electric circuit selection, and polysilicon and electric capacity metal
Layer is influenceed by factors such as material stresses, in the case where design rule is met, does not allow to be made to especially greatly, therefore, root
According to needing capacitive division into independent elementary cell, in the present embodiment, the capacitor is to be uniformly distributed in sealing ring region
Multiple rectangle electric capacity in domain, the need for circuit parameter, choose one or several electric capacity mode in parallel access inside
Circuit.
Embodiment two
The present embodiment provides a kind of integrated circuit sealing ring, the sealing ring in the integrated circuit sealing ring and embodiment one
Structure it is basically identical, difference is, between arbitrary neighborhood two metal layers, or the doped region and the laminated construction
In bottom metal layer between be formed with the second polysilicon and the 3rd polysilicon, second polysilicon and the 3rd polysilicon
Vertical distribution.
Specifically, as shown in figure 5, in the present embodiment, in the first medium layer 202a of the top of the doped region 201
The second polysilicon 203b and the 3rd polysilicon 203c, the second polysilicon 203b and the 3rd polysilicon 203c is formed with to hang down
Straight distribution, the second polysilicon 203b and the 3rd polysilicon 203c overlapping region forms PIP capacitor.More than described second
Crystal silicon 203b and the 3rd polysilicon 203c respectively as capacitor the first pole plate and the second pole plate, the capacity of capacitor with
The second polysilicon 203b is relevant with the distance between the 3rd polysilicon 203c.In the present embodiment, more than the described 3rd
Crystal silicon 203c as capacitor bottom crown, by connecting hole C, the first metal layer M1, connecting hole C, the doped region 201
It is electrically connected with the substrate layer 200；The second polysilicon 203b as capacitor top crown, by connecting hole C with it is slow
Rush the first metal layer M1 connections in area, the first metal layer M1 is connected with second metal layer M2 by connecting hole V1, each metal level according to
Secondary to realize being electrically connected with by through hole, the second polysilicon 203b can be by the metal level in the buffering area and through hole and institute
The metal level connection of the random layer of active device region is stated, and then realizes the connection with active device, play the filter to internal circuit
Ripple, energy storage etc. are acted on.
The situation that the second polysilicon 203b and the 3rd polysilicon 203c are formed between other metal levels is similar to,
Do not repeat one by one herein.
Further, as shown in figure 5, described in being formed at as the second polysilicon 203b and the 3rd polysilicon 203c
When between doped region 201 and the first metal layer M1, the second polysilicon 203b is formed with the doped region 201 simultaneously
Mos capacitance, mos capacitance is in parallel with PIP capacitor, further increases the capacitance of electric capacity.
Embodiment three
The present embodiment provides a kind of integrated circuit sealing ring, the integrated circuit sealing ring and embodiment one and embodiment two
In the difference of seal ring structure be to be formed with metallic plate between arbitrary neighborhood two metal layers.
Specifically, as shown in fig. 6, in the present embodiment, between the second metal layer M2 and the 3rd metal level M3
Dielectric layer in be formed with metallic plate 204, the metallic plate 204 forms MIM electricity with the region that the second metal layer M2 is overlapped
Hold.The second metal layer M2 and the metallic plate 204 respectively as capacitor the first pole plate and the second pole plate, capacitor
Capacity is relevant with the distance between the metallic plate 204 with the second metal layer M2.In the present embodiment, second metal
Layer M2 as capacitor bottom crown, by connecting hole V1, the first metal layer M1, connecting hole C, the doped region 201 with
The substrate layer 200 is electrically connected with；The metallic plate 204 as capacitor top crown, by connecting hole V2 and buffering area
3rd metal level M3 is connected, and the metallic plate 204 can be by the metal level in the buffering area and through hole and the active device
The metal level connection of the random layer in area, and then the connection with active device is realized, play filtering, energy storage to internal circuit etc. and make
With.
The situation that the metallic plate 204 is formed between other metal levels is similar to, and does not repeat one by one herein.
Further, as shown in fig. 6, when the metallic plate 204 is formed at the 3rd metal level M3 and second gold medal
When between category layer M2, the second polysilicon 203b and the 3rd polysilicon 203c be formed at the doped region 201 with it is described
Between the first metal layer M1, then the in parallel of MIM capacitor and mos capacitance and/or PIP capacitor is capable of achieving by the wiring of metal level, entered
The performance of one-step optimization capacitor.
The utility model is intended to not influence integrated circuit area, in the case of the function and performance of sealing ring are not also changed,
Improved in the structure of existing integrated circuit sealing ring, made integrated circuit while meeting density requirements and the increasing of polysilicon
Plus filter function.
In sum, the utility model provides a kind of integrated circuit sealing ring, including：Substrate layer；It is formed at the substrate
Doped region in layer；The dielectric layer and the laminated construction of metal level being formed on the doped region, each metal level and the doping
Realize being electrically connected with by connecting hole in area；And, it is formed at the capacitor in the laminated construction, the first pole of the capacitor
Plate and the second pole plate are respectively by the metal level in the laminated construction and the metal level in buffering area and substrate and internal circuit
Connection.Integrated circuit sealing ring of the present utility model increases polysilicon or metal in the structure of existing integrated circuit sealing ring
Plate, to form capacitor, in the case where integrated circuit area is not influenceed, makes integrated circuit meet the density requirements of polysilicon,
Caused uneven surface envelope during avoiding chemical-mechanical polishing from operating；It is not take up extra domain and increases electric capacity simultaneously.Institute
So that the utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all be carried out under without prejudice to spirit and scope of the present utility model to above-described embodiment
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model
All equivalent modifications completed under god and technological thought or change, should be covered by claim of the present utility model.
Claims (8)
1. a kind of integrated circuit sealing ring, it is characterised in that the integrated circuit sealing ring at least includes：
Substrate layer；
It is formed at the doped region in the substrate layer；
The dielectric layer and the laminated construction of metal level being formed on the doped region, each metal level and the doped region are by connection
Realize being electrically connected with hole；
And,
The capacitor in the laminated construction is formed at, first pole plate and the second pole plate of the capacitor are respectively by described folded
The metal level in metal level and buffering area in Rotating fields is connected with substrate and internal circuit.
2. integrated circuit sealing ring according to claim 1, it is characterised in that：The substrate layer is P type substrate, described to mix
Adulterated for p-type in miscellaneous area.
3. integrated circuit sealing ring according to claim 1, it is characterised in that：The substrate layer is N-type substrate, described to mix
Miscellaneous area is n-type doping.
4. integrated circuit sealing ring according to claim 1, it is characterised in that：The capacitor is mos capacitance, the electricity
First pole plate of container is the first polysilicon between the bottom metal layer being formed in the doped region and the laminated construction,
Second pole plate of the capacitor is the doped region.
5. integrated circuit sealing ring according to claim 1, it is characterised in that：The capacitor is PIP capacitor, the electricity
First pole plate and the second pole plate of container are to be formed in the laminated construction between arbitrary neighborhood two metal layers, or are formed at
The second polysilicon and the 3rd polysilicon between bottom metal layer in the doped region and the laminated construction, more than described second
Crystal silicon and the 3rd polysilicon vertical distribution.
6. integrated circuit sealing ring according to claim 1, it is characterised in that：The capacitor is MIM capacitor, the electricity
First pole plate of container is to be formed at the metallic plate in the laminated construction between arbitrary neighborhood two metal layers, the capacitor
The second pole plate be neighbouring with metallic plate metal level in the laminated construction.
7. integrated circuit sealing ring according to claim 1, it is characterised in that：The material of the dielectric layer is silica
Or silicon nitride.
8. integrated circuit sealing ring according to claim 1, it is characterised in that：The material of the metal level is copper or aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621285071.1U CN206225359U (en) | 2016-11-28 | 2016-11-28 | A kind of integrated circuit sealing ring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621285071.1U CN206225359U (en) | 2016-11-28 | 2016-11-28 | A kind of integrated circuit sealing ring |
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| Publication Number | Publication Date |
|---|---|
| CN206225359U true CN206225359U (en) | 2017-06-06 |
Family
ID=58786389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621285071.1U Active CN206225359U (en) | 2016-11-28 | 2016-11-28 | A kind of integrated circuit sealing ring |
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| CN (1) | CN206225359U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449600A (en) * | 2016-11-28 | 2017-02-22 | 上海南麟电子股份有限公司 | Sealing ring of integrated circuit |
| WO2021139600A1 (en) * | 2020-01-09 | 2021-07-15 | 华南理工大学 | Layout structure for improving high-frequency reliability of mim capacitor and implementation method thereof |
-
2016
- 2016-11-28 CN CN201621285071.1U patent/CN206225359U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449600A (en) * | 2016-11-28 | 2017-02-22 | 上海南麟电子股份有限公司 | Sealing ring of integrated circuit |
| WO2021139600A1 (en) * | 2020-01-09 | 2021-07-15 | 华南理工大学 | Layout structure for improving high-frequency reliability of mim capacitor and implementation method thereof |
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