CN202524483U - FPGA-based CIS image acquisition system - Google Patents
FPGA-based CIS image acquisition system Download PDFInfo
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- CN202524483U CN202524483U CN2012201285584U CN201220128558U CN202524483U CN 202524483 U CN202524483 U CN 202524483U CN 2012201285584 U CN2012201285584 U CN 2012201285584U CN 201220128558 U CN201220128558 U CN 201220128558U CN 202524483 U CN202524483 U CN 202524483U
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Abstract
The utility model discloses a FPGA-based CIS image acquisition system, which comprises a CIS sensor, an AD acquisition module connected with the output end of the CIS sensor, an FPGA data processing module in both-way connection with the AD acquisition module, an LVDS conversion module and a single-chip control module both in both-way connection with the FPGA data processing module, and a camera link interface in both-way connection with the LVDS conversion module. The single-chip control module is in both-way connection with the LVDS conversion module. The output end of the single-chip control module is connected with the input end of the AD acquisition module. The single-chip of the single-chip control module is a PIC single-chip. The output end of the FPGA data processing module is connected with the CIS sensor. The FPGA-based CIS image acquisition system can accurately acquire and detect a CIS image and can detect the defects of a PCB plate so as to improve the qualified rate of PCB plates.
Description
Technical field
The utility model relates to a kind of linear array contact figure acquisition system that is used for verifier or PCB industry other field; Particularly relate to a kind of based on FPGA (Field-Programmable Gate Array; Be field programmable gate array) CIS (Contact Image Sensor, contact-type image sensor) image capturing system.
Background technology
Contact-type image sensor (CIS) develops into shape approximately in the early 1990s, because its mechanism is compact, does not have complicated optical lens assembly, and volume is little; In light weight, anti-seismic performance is good, responds fast advantage; The part market that has progressively replaced CCD is widely used in fax, scanning, the identification of bank note bill, the cursor reading, simultaneously; CIS reduced the volume of detecting instrument in the application of PCB industry, the stability and the cost performance that have increased.
The development of PCB industry makes manual detection can't adapt to; Carry out the collection of PCB image through CIS, handle, can detect the defective in the pcb board easily, improved the competitiveness of PCB producer through software analysis; But how can better utilize FPGA to carry out the CIS IMAQ, acquisition system is more and more accurate.
The utility model content
The purpose of the utility model is to overcome the deficiency of prior art, and a kind of CIS image capturing system based on FPGA is provided, and can carry out acquisition testing to the CIS image accurately, detects the defective that exists in the pcb board, improves the qualification rate of pcb board.
In order to achieve the above object; The technical scheme that the utility model adopts is: a kind of CIS image capturing system based on FPGA; Comprise the CIS transducer; Described CIS image capturing system also comprise the AD acquisition module that is connected with CIS transducer output, with the two-way FPGA data processing module that is connected of AD acquisition module, with the two-way LVDS modular converter that is connected of FPGA data processing module and single chip control module, with the two-way cameralink interface that is connected of LVDS modular converter, FPGA provides the work schedule of CIS, the image of CIS output is gathered through AD and is converted digital signal to; Carry out preliminary treatment by FPGA; And store in the internal RAM, according to the cameralink data format, export data to the cameralink interface with the form of difference through the LVDS chip.
Further, described single chip control module is connected with the LVDS modular converter is two-way.
Further, the output of described single chip control module is connected with the input of AD acquisition module.
Further, the single-chip microcomputer of described single chip control module is the PIC single-chip microcomputer.
Further, the output of described FPGA data processing module is connected with the CIS transducer.
Further, described FPGA data processing module is a Cyclone III FPGA data processing module.
Further, described FPGA comprises that CIS sequential, A/D gather sequential, PLL frequency multiplication, two-port RAM, MCU communication, cameralink interface module.
Compared with prior art, the beneficial effect of the utility model is: can carry out acquisition testing to the CIS image accurately, detect the defective that exists in the pcb board, improve the qualification rate of pcb board.
Description of drawings
Fig. 1 is the system configuration sketch map of the utility model;
Fig. 2 is the FPGA general function module map of the utility model;
Fig. 3 is the CIS sequential chart of the utility model;
Fig. 4 is the AD conversion timing sequence figure of the utility model;
Fig. 5 is the method flow diagram of the utility model.
Embodiment
The purport of the utility model is to overcome the deficiency of prior art, and a kind of CIS image capturing system based on FPGA is provided, and native system is made up of FPGA, single-chip microcomputer, AD converter, LVDS chip; FPGA provides the work schedule of CIS, and the image of CIS output is gathered through AD; Convert digital signal to, carry out preliminary treatment, and store in the internal RAM by FPGA; According to the cameralink data format, export data to the cameralink interface with the form of difference through the LVDS chip.
FPGA provides work schedule for the CIS transducer, and the analog signal of CIS output is gathered through AD, after preliminary treatment such as FPGA denoising, binaryzation, stores in the FPGA internal RAM.Obtain user's setup parameter of single-chip microcomputer according to FPGA after, select the output image type; Output image is sent to the cameralink interface through the LVDS chip with the mode of difference, handles through image pick-up card to computer software.
Be elaborated with reference to accompanying drawing below in conjunction with embodiment, so that the technical characterictic and the advantage of the utility model are carried out more deep annotation.
The theory diagram of the utility model is as shown in Figure 1; A kind of CIS image capturing system based on FPGA; Comprise the CIS transducer, described CIS image capturing system also comprise the AD acquisition module that is connected with CIS transducer output, with the two-way FPGA data processing module that is connected of AD acquisition module, with the two-way LVDS modular converter that is connected of FPGA data processing module and single chip control module, with the two-way cameralink interface that is connected of LVDS modular converter.
Further, described single chip control module is connected with the LVDS modular converter is two-way.
Further, the output of described single chip control module is connected with the input of AD acquisition module.
Further, the single-chip microcomputer of described single chip control module is the PIC single-chip microcomputer.
Further, the output of described FPGA data processing module is connected with the CIS transducer.
Further, described FPGA data processing module is a Cyclone III FPGA data processing module.
Further, described FPGA comprises that CIS sequential, A/D gather sequential, PLL frequency multiplication, two-port RAM, MCU communication, cameralink interface module.
As shown in Figure 5, a kind of acquisition method according to described CIS image capturing system based on FPGA, its step is following:
Step 4, if host computer has Data Update, get into interrupt routine, return after receiving data;
Whether step 5, judgment data satisfy self-defining communication protocol, are execution in step 6 then, otherwise execution in step 4;
Step 6, judging whether to be new data, is execution in step 7 then, otherwise execution in step 12;
Whether step 7, judgment data are configuration AD running parameter, are execution in step 8 then, otherwise are sent to FPGA and execution in step 10;
Step 8, reconfigure the AD chip; And execution in step 9;
Step 9, data are write eeprom;
Step 11, return configuration status to host computer;
Step 12, termination routine.
It is 658 millimeters that contact-type image sensor (CIS) adopts a sweep limits, 600DPI, and sweep speed is the CIS of 70us/line.Its pixel clock frequency is 8M, inner CIS and line scanning by 36 sections 432 valid pixels, and its total valid pixel is a 36*432=15552 pixel.Per 4 sections analog signals are output as an interface, totally 9 output interfaces.
The CIS operate as normal need provide pixel clock signal CCLK and gating signal SI, and 8M makes that as speed the image transfer rate is 8M*15552 joint/second=121.5MKB/S, and this requires to use high-speed data processor.
Light source adopts red LED strip source, the volume of nearly 630 nanometers of wavelength little, low in energy consumption, easy for installation.
High-speed CCD (Charge-coupled Device charge coupled cell)/CIS AD sampling A WM8214, WM8214 are the special-purpose AD acquisition chips of 16 CCD/CIS of 40MSPS, and typical power consumption has only 390mW.It supports RGB triple channel color mode and black and white monochromatic mode, and inside has reset level clamp circuit (RLC) and two-phase is closed sample circuit (CDS), can adapt to the connection of various imageing sensors flexibly and reduce image noise; Through the setting of internal register, can be operated in RGB triple channel pattern with only and line output most-significant byte data; Such 36 sections CIS mode signals output just needs 12 WM8214.Can change the straight parameters such as value, inverse partially of mode of operation, gain, black level of IMAQ in real time through the serial line interface of WM8214.
Single-chip microcomputer is used for through accepting to dispose AD acquisition chip WM8214 mode of operation and parameter configuration from cameralink interface user command.Simultaneously user data is stored among the eeprom, possesses the outage memory function.Single-chip microcomputer also need be communicated by letter with FPGA, FPGA is set according to the user carry out corresponding image preliminary treatment.
Single-chip microcomputer adopts the PIC single-chip microcomputer PIC18F452 of high-performance RISC instruction, has extremely strong antijamming capability, can well adapt to the electromagnetic interference environment that exists in the verifier.Inner simultaneously integrated 256 byte eeprom, erasable number of times can reach 1,000,000 times.
FPGA is that IMAQ provides sequential, and pre-processing image data is exported with transmitting.Because every collection data line amount is 432*36*8bit=124416bit=121.5Kbit; The ram space that needs 122kbit; RAM adopts the M9K structure in the FPGA simultaneously, adopts the EP3C16Q240 chip of Cyclone III series, and inside is used for the 504Kbit ram space.It supports AS configuration and the configuration of JTAG on-line debugging, can develop debugging easily.
Camera link interface is the high-speed video interface that on Channel Link basis, develops, and adopts the LVDS differential signal transmission, and the reliability of data can effectively be provided.The core element comprises one and change string driver and a string changes and receiver.Driver is serialized as 4 LVDS data flow with 28 CMOS/TTL signals with the 7:1 mode.A phase-locked loop transfer clock is through the 5th LVDS link and other LVDS data flow parallel transmissions.Receiver receives 4 road LVDS data-signals and 1 road LVDS clock signal, data flow is changed back 28 CMOS/TT L parallel data.Channel Link maximum transmission rate can reach 2.38Gbits/ s.Can dispose base 3 passages according to actual data stream, medium 6 passages, full 8 channel patterns.
Corresponding LVDS chip DS90LV032 is used for the host computer triggering signal, and DS90LV019 is used for the inner uart conversion of signals of cameralink.DS90CR287 is used for 5 LVDS link signal conversions, supports that maximum clock frequency reaches 85MHZ.
It is 121.5MKB/S that digital data stream is arranged, so adopt medium 6 channel patterns, clock frequency 50MHZ.
FPGA entire system FBD such as Fig. 2 show that in the FPGA programming, FPGA is a core controller, are responsible for IMAQ, processing and cameralink protocol conversion.It comprises that CIS sequential, A/D gather modules such as sequential, PLL frequency multiplication, two-port RAM, MCU communication, cameralink interface.
Timing Design: FPGA is that CIS provides clock signal C CLK and gating signal SI.Like Fig. 2, output black level magnitude of voltage in 72-79 the CCLK after the rising edge of each SI, output valid pixel voltage behind the 84th CCLK.Owing to having adopted WM8214 to do the AD conversion, its triple channel is gathered timesharing output, and the data of sampling will be waited until the just output afterwards of 3 data in front last time, fVSMP=fCCLK=8MHZ.So, need VSMP and RSMP signal be provided at 84CCLK, 84+3=87 CCLK reading of data.
Data processing: verifier is to collecting the differentiation of pcb board image for ease, and it is very necessary that image is carried out preliminary treatment, can reduce the upper computer software burden.The image that collects is a gray level image, has noise naturally, and we can extend to 0 with the value below 10 gray values, and the part low value pixels of loss to a certain degree can reduce noise.Simultaneously, selected according to the user, image overall is carried out binaryzation, reduced the host computer internal memory cost, and native system can be accomplished easily.User data receives task and is accomplished by the self-defining communication protocol between FPGA and single-chip microcomputer.
Storage and cameralink send: in order to satisfy the speeds match that data acquisition and cameralink interface data send, need data are cushioned, adopt the two-port RAM ping-pong operation to carry out storage.It has independently read/write address line and data wire respectively, and inside possesses the read-write arbitration function, prevents read/write conflict.Utilize the IP kernel generation navigational aids of quartus II 8.0 can generate two-port RAM easily.The data volume of accomplishing delegation's collection is 124416bit, and the RAM of cycloneIII is the M9K structure, and each RAM size is chosen 1KByte, and 36 RAM that build together carry out storage.With the high status address of RAM two buffering areas, the view data of gathering is deposited among 36 RAM according to a definite sequence as ping-pong operation.
The Cameralink interface adopts the medium pattern, imitates data channel for totally 6, and each data channel is responsible for the transmission of 6 sections CIS images.The Cameralink interface sequence mainly provides pixel clock signal XCLK, line synchronizing signal LVAL and frame synchronizing signal FVAL signal; Because the collection of PCB image is relevant with physical length; The online pattern of sweeping of only working then only need provide clock signal XCLK and LVAL line synchronizing signal.Need to insert blank pixel before each line synchronizing signal LVAL, specifically according to the image pick-up card difference and respective settings, but XCLK must guarantee it is continuous.Pixel clock signal adopts 50MHZ, and the 6medium pattern can support that then data flow reaches 300MBPS.
Like Fig. 3, shown in 4, in the SCM program design, single chip part is responsible for the parameters such as the straight value partially of working method, configured gain, black level of CCD/CIS chips W M8214.Single-chip microcomputer is revised the internal register value through class SPI mode, changes each parameter.Simultaneously, single-chip microcomputer is communicated by letter with host computer through the inner uart interface of cameralink, need carry out data communication with FPGA simultaneously, the pretreated type of control FPGA image, so, 3 communication interfaces of the inner existence of single-chip microcomputer.Except that uart directly used the inner uart interface of PIC, all the other two interfaces carried out self-defined communication mode.After the user's modification parameter, it is inner integrated among the eeprom of 256 bytes that customer parameter is written to PIC18F452.During each opening initialization, read the data of eeprom and carry out system configuration.
This acquisition system is applied on the Asida verifier in experiment test, successfully through adopting the figure checking.PCB detection speed 12.4m/min, PCB width are 650mm, real inspection 0.15mm aperture stable performance.Can carry out real-time gain, the straight value partially of black level, binary image selection collecting test through the pc machine.Utilize reflection source to carry out the silk-screen scanning of PCB surface simultaneously, picture quality is better, and the intersegmental noise of each GTG is very little.
The utility model is the online modifiable high-performance CIS image capturing system of the parameter of core with FPGA.System adopts the integral type imageing sensor of a 658mm, and having avoided has increased accuracy of detection and reduced design complexities because of transducer splicing problem causes image noncontinuity problem.FPGA carries out preliminary treatment with the picture signal that collects, and is stored in the FPGA internal RAM and cushions, and transfers to host computer with cameralink interface LVDS differential mode, has improved the reliability of image transmission.If increase reflection source, the proper operation parameter is set, can realize the aperture of pcb board and the high precision collecting of silk-screen tomographic image, can be applied to the scanning collection of broadsheet bill simultaneously.PCB minimum detection aperture is 0.043mm, if adopt more high-resolution CIS, can detect more small-bore.
The above is the utility model preferred embodiment, and under the prerequisite of the inventive concept that does not break away from the utility model, any conspicuous replacement is all within the protection range of the utility model.
Claims (7)
1. CIS image capturing system based on FPGA; Comprise the CIS transducer; It is characterized in that: described CIS image capturing system also comprise the AD acquisition module that is connected with CIS transducer output, with the two-way FPGA data processing module that is connected of AD acquisition module, with the two-way LVDS modular converter that is connected of FPGA data processing module and single chip control module, with the two-way cameralink interface that is connected of LVDS modular converter; FPGA provides the work schedule of CIS; The image of CIS output is gathered through AD and is converted digital signal to, carries out preliminary treatment by FPGA, and stores in the internal RAM; According to the cameralink data format, export data to the cameralink interface with the form of difference through the LVDS chip.
2. the CIS image capturing system based on FPGA according to claim 1 is characterized in that: described single chip control module is connected with the LVDS modular converter is two-way.
3. the CIS image capturing system based on FPGA according to claim 2 is characterized in that: the output of described single chip control module is connected with the input of AD acquisition module.
4. the CIS image capturing system based on FPGA according to claim 3 is characterized in that: the single-chip microcomputer of described single chip control module is the PIC single-chip microcomputer.
5. the CIS image capturing system based on FPGA according to claim 1 is characterized in that: the output of described FPGA data processing module is connected with the CIS transducer.
6. the CIS image capturing system based on FPGA according to claim 5 is characterized in that: described FPGA data processing module is a Cyclone III FPGA data processing module.
7. the CIS image capturing system based on FPGA according to claim 6 is characterized in that: described FPGA comprises that CIS sequential, A/D gather sequential, PLL frequency multiplication, two-port RAM, MCU communication, cameralink interface module.
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| CN2012201285584U CN202524483U (en) | 2012-03-30 | 2012-03-30 | FPGA-based CIS image acquisition system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625056A (en) * | 2012-03-30 | 2012-08-01 | 广东正业科技股份有限公司 | FPGA (Field-Programmable Gate Array)-based CIS (Contact Image Sensor) image acquisition system and acquisition method thereof |
| CN109829394A (en) * | 2019-01-14 | 2019-05-31 | 上海思立微电子科技有限公司 | Shield lower fingerprint chip |
| CN110646441A (en) * | 2019-09-04 | 2020-01-03 | 深圳市智微智能科技开发有限公司 | PCB defect detection system and method based on FPGA |
-
2012
- 2012-03-30 CN CN2012201285584U patent/CN202524483U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625056A (en) * | 2012-03-30 | 2012-08-01 | 广东正业科技股份有限公司 | FPGA (Field-Programmable Gate Array)-based CIS (Contact Image Sensor) image acquisition system and acquisition method thereof |
| CN109829394A (en) * | 2019-01-14 | 2019-05-31 | 上海思立微电子科技有限公司 | Shield lower fingerprint chip |
| CN110646441A (en) * | 2019-09-04 | 2020-01-03 | 深圳市智微智能科技开发有限公司 | PCB defect detection system and method based on FPGA |
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Granted publication date: 20121107 Termination date: 20210330 |