CN102638649B - USB3.0 high-speed high-definition industrial camera - Google Patents
USB3.0 high-speed high-definition industrial camera Download PDFInfo
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Abstract
The invention belongs to the technical field of electronic communication and discloses a USB3.0 high-speed high-definition industrial camera. The camera comprises an optical lens, an industrial CCD (Charge Coupled Device), a high-precision CCD front end and a USB3.0 master control module, wherein the USB3.0 master control module comprises a USB3.0 microkernel processor, a camera controller and a real-time data storage area; the USB3.0 microkernel processor is an operation processing unit of the USB3.0 master control module and is connected with a host machine controller of a master control computer through an end point 0; the data input interface of the real-time data storage area is connected with the digital image signal output interface of a high-precision ADC (Analog to Digital Converter) of the CCD front end through a data bus; the data output interface of the real-time data storage area is connected with a USB3.0 real-time end point; and the output interface of the camera controller is used for outputting a camera control signal to a CCD front end controller through a camera control bus. The USB3.0 master control module is used for replacing signal transmitting devices, such as a DSP (Digital Signal Processor), an ARM (Advanced RISC Machine) and an FPGA (Field Programmable Gate Array), in the prior art, so that the USB3.0 high-speed high-definition industrial camera has the advantages of low transmission speed, low cost, simple circuit, stable and reliable system, simple interface and convenience in connection.
Description
Technical field
The present invention relates to camera field, particularly for the optical detection of high speed high definition and the field of image transmission of industrial detection, monitoring, specifically refer to USB3.0 high speed high definition industrial camera and USB3.0 video acquisition and transmission method.
Background technology
Industrial camera is widely used, and can be used for dimensional measurement, paper defects detection, luminous environment monitoring, quantity statistics, waste product sorting etc.Industrial camera data acquisition at present and transmission means are mainly to upload to computer by netting twine again by storage, processing, compression.Data compression can destroy original sampling data, is difficult to find interface easily to reach high-speed transfer and do not compress.The for example cable interface in common computer, its bandwidth only has 100Mbps.And just do not have on the high computer as common in 1394 interfaces, camalink interface of data transmission bauds at all.And if utilize the interface having in common computer just to have to add data processor and memory, cause cost to increase.
USB is a kind of interfacing that is applied in computer realm, has the advantages such as hot plug, portable, transmission speed is fast.Due to the various advantages of USB, various operating system is all supported this interfacing as windows series, linux series, and this makes the application of USB technology more extensive.Along with the development of USB technology and perfect, USB transmission speed is more and more faster, and the bit rate of USB3.0 has reached 5Gbps especially.Be applicable to very much the large transmission of video of data volume.
Summary of the invention
For the demand, the object of this invention is to provide a kind of transmission speed is fast, circuit is simple and reliable, measuring range is wide, certainty of measurement is high USB3.0 high speed high definition industrial camera and USB3.0 video acquisition and transmission method.
For achieving the above object, the invention provides a kind of USB3.0 high speed high definition industrial camera, comprise the optical lens for capture, optical lens capture is carried out to the industrial CCD of imaging, drive signal for generation of the CCD that drives industrial CCD output image signal, the high accuracy CCD front end of data image signal output is processed and analog picture signal is converted to the analog picture signal that receives industrial CCD output, described high accuracy CCD front end comprises for generation of CCD driving signal, the precision interval clock module of CDS clock and zero data cached collection control signal, for described industrial CCD output signal being carried out to the signal condition module of impedance transformation and DC level conversion, for the ccd output signal after described signal condition resume module being carried out to the CDS of correlated-double-sampling, for the VGA that the signal after described CDS correlated-double-sampling is amplified, be used for the black level offset compensation circuit of the dark current value of proofreading and correct the signal of exporting through VGA, with the high-precision adc that the image pickup signal after black level offset compensation is carried out to analog-to-digital conversion output, the CCD of described precision interval clock module drives signal output interface to drive signal input interface to be connected through a drive level conversion module and industrial CCD,
It is characterized in that, this industrial camera also comprises a USB3.0 main control module;
Described USB3.0 main control module comprises USB3.0 micro-kernel processor, generate the camera controller of camera control signal output according to USB3.0 micro-kernel processor instruction, for the real-time data memory district of caching image data, according to the data acquisition state machine of real-time data memory district WE described in zero data cached collection control signal control of precision interval clock module output, for with computer on USB3.0 console controller transmit image data the real-time end points of USB3.0 and with computer carry out USB3.0 control transmission end points 0, described USB3.0 micro-kernel processor is the operation processing unit of USB3.0 main control module, and it is connected with USB3.0 console controller on computer by end points 0, the Data Input Interface in real-time data memory district is connected with the data image signal output interface of the high-precision adc of CCD front end by data/address bus, and its data output interface connects the real-time end points of described USB3.0, described data acquisition state machine is connected by zero data cached collection control line with described precision interval clock module, the output interface of described camera controller is exported shooting control signal by shooting control bus to high accuracy CCD front end.
In above-mentioned USB3.0 high speed high definition industrial camera, described high accuracy CCD front end also comprises the CCD front controller of the parameter for CDS, VGA, precision interval clock module, black level offset compensation and high-precision adc are set; Described industrial CCD pixel is at least 1M; Precision interval clock module phase place in described high accuracy CCD front end is adjusted precision and is at least 10ns; High-precision adc in described high accuracy CCD front end is at least 8 ADC.
Further, described industrial CCD can be selected interline transfer type area array CCD; Zero described data cached collection control line comprises that row shifts synchronizing clock signals line, frame transfer synchronizing clock signals line, normal pixel index signal and data/address bus synchronizing clock signals line; Described shooting control bus comprises spi bus and start/stop holding wire.
In the present invention, it is serial as middle one such as KAI-1010M that described industrial CCD can be selected the KAI as ICX274AL chip, Kodak in the ICX2 of Sony Corporation series;
The major function of the picture signal processing of described high accuracy CCD front end can select various chips to realize, such as the AD99 of ADI company is serial as AD9927, and AD9923A etc.
The preferred AD9927 chip of the present invention, this chip internal is integrated with described precision interval clock module, CDS, VGA, black level offset compensation circuit, high-precision adc, CCD front controller, for forming complete high accuracy CCD front end, can select in addition a 74ACT04 chip as described drive level conversion module, and select any to there is the signal condition module of impedance transformation and DC level mapping function.Described drive level conversion module is for carrying out the driving signal of described high accuracy CCD front end output to output to after level translation the driving signal input of described industrial CCD;
Described USB3.0 main control module can be selected USB3014 chip; Described USB3.0 main control module arranges CCD front controller and the start/stop high accuracy CCD front end in described high accuracy CCD front end by described shooting control bus;
Micro-kernel processor in the spi bus that camera controller in USB3.0 main control module described in described shooting control bus comprises transmits to CCD front controller and described USB3.0 main control module is to the start/stop holding wire of CCD front controller transmission.
Zero described data cached collection control line comprises that row shifts synchronizing clock signals HD line, frame transfer synchronizing clock signals VD line, normal pixel index signal PBLK line and data/address bus synchronised clock CLK holding wire; Described data/address bus is for connecting the high-precision adc data output end of described high accuracy CCD front end and described USB3.0 main control module data input pin; Described data/address bus synchronised clock CLK frequency is identical with the Data Update frequency on data/address bus;
Described data acquisition state machine is for accepting the control of zero described data cached collection control line, described data acquisition state machine is according to the WE in the change operation real-time data memory district of state on zero data cached collection control line, when the data/address bus synchronised clock CLK on zero described data cached collection control line and normal pixel index signal PBLK are simultaneously effectively time, data acquisition state machine enables the WE in real-time data memory district, now the data on the data/address bus in zero described data cached acquisition interface are just written in described real-time data memory district, described data acquisition state machine shifts synchronizing clock signals HD according to the row in zero described data cached collection control line and frame transfer synchronizing clock signals VD carries out the synchronous of pixel column and picture frame, described real-time data memory district is for temporarily depositing the data that write from data/address bus, the real-time end points of described data mode machine, real-time data memory district and USB3.0 forms does not wait for data transmission channel, initiate the transfer of data from the real-time end points of USB3.0 to the computer being connected with USB3.0 main control module by not waiting for the USB3.0 main control module described in data transmission channel, in the time that the data length in the real-time end points of USB3.0 reaches the length of a packet, USB3.0 main control module is just initiated the transfer of data to the computer being connected with USB3.0 main control module, described USB3.0PHY engine is USB3.0 data transmitter/receiver circuits,
Compared with prior art, advantage of the present invention is:
1. transmission speed is fast; Outside the useless transmission such as protocol overhead, inter-packet gap, valid data transmission speed can reach 3.2Gbps.
2. cost is low, circuit is simple.In equipment of the present invention, there is no data processing device, there is no memory device.Whole circuit does minimum needs 3 chip blocks, is very classical Circnit Layout.
3. system stability is reliable.Circuit simply means that integrated level is high, and the simple maximum advantage of circuit is exactly failure rate is low, and chip is more, and fault is more.
4. measure accurately.Adopted, dark current is extremely low, and along with the decline of temperature, dark current size is pressed index decreased; Adopted 14 AD, conversion accuracy is high, and nonlinearity is little; Adopt the technology such as correlated-double-sampling, black level offset compensation, reduced other noises; Adopt high-frequency clock module, can accurately control correlated-double-sampling phase accuracy, guaranteed the high-quality of sampling.
5. easy to connect, support hot plug.
6. interface is simple.USB3.0 interface is all equipped with on common computer, in a few years.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention;
Fig. 2 is integral module schematic diagram of the present invention;
Fig. 3 is the circuit theory diagrams of one embodiment of the invention;
Fig. 4 is that the pixel of interline transfer type area array CCD shifts schematic diagram;
Fig. 5 is the pixel map of ICX274AL chip;
Fig. 6 zero state transitions that data cached acquisition method is taked mechanism figure
Fig. 7 is USB3.0 video acquisition and transmission operational flowchart.
Embodiment
In order more clearly to understand technology contents of the present invention, describe in detail especially exemplified by following examples.
Please refer to Fig. 1.It is overall structure schematic diagram of the present invention.USB3.0 high speed high definition industrial camera of the present invention, comprises optical lens, industrial CCD, high accuracy CCD front end, shooting control bus, zero data cached collection control line, data/address bus and USB3.0 main control module.Optical lens provides suitable luminous environment to image-forming component; Industrial CCD is for optical imagery; High accuracy CCD front end mainly produces and drives the CCD of industrial CCD output image signal to drive the analog picture signal of signal, the output of reception industrial CCD process and convert analog picture signal to data image signal output at this; USB3.0 main control module arranges CCD front-end control position and the start/stop high accuracy CCD front end in described high accuracy CCD front end by described shooting control bus; Zero data cached collection control line for control USB3.0 main control module on data/address bus data acquisition.USB3.0 main control module is for realizing image data acquiring with the control of communicating by letter, control high accuracy CCD front end and acceptance zero data cached collection control line of computer.
Please refer to Fig. 2, is integral module schematic diagram of the present invention.On the basis of Fig. 1, Fig. 2 has carried out refinement to high accuracy CCD front end, zero data cached acquisition interface and USB3.0 main control module.
High accuracy CCD front end comprises signal condition module, drive level conversion module, CDS, VGA, CCD front-end control position, precision interval clock module, black level offset compensation and high-precision adc; Signal condition module is for carrying out the analog picture signal of industrial CCD output impedance transformation and DC level conversion; Drive level conversion module is for driving the CCD of precision interval clock module output signal to carry out outputing to after level translation the driving signal input of industrial CCD; CDS is for carrying out correlated-double-sampling to the ccd output signal after described signal condition resume module; VGA is for amplifying the signal after described CDS correlated-double-sampling; Precision interval clock module is for generation of the driving signal of CCD; Black level offset compensation is for proofreading and correct the dark current value of the signal after out through VGA; High-precision adc is the AD converter of more than 8 sampling precision; CCD front controller is for arranging the parameter of CDS, VGA, precision interval clock module, black level offset compensation and high-precision adc.
Zero data cached collection control line comprises that row shifts synchronizing clock signals HD, frame transfer synchronizing clock signals VD, normal pixel index signal PBLK and data/address bus synchronised clock CLK; Data/address bus is for connecting the high-precision adc data output end of described high accuracy CCD front end and described USB3.0 main control module data input pin; Data/address bus synchronised clock CLK frequency is identical with the Data Update frequency on data/address bus;
Micro-kernel processor in the spi bus that camera controller in USB3.0 main control module described in shooting control bus comprises transmits to CCD front controller and described USB3.0 main control module is to the start/stop holding wire of CCD front controller transmission.
Described USB3.0 main control module comprises USB3.0 micro-kernel processor, generate the camera controller of camera control signal output according to USB3.0 micro-kernel processor instruction, for the real-time data memory district of caching image data, according to the data acquisition state machine of real-time data memory district WE described in zero data cached collection control signal control of precision interval clock module output, for with computer on USB3.0 console controller transmit image data the real-time end points of USB3.0 and with computer carry out USB3.0 control transmission end points 0, described USB3.0 micro-kernel processor is the operation processing unit of USB3.0 main control module, and it is connected with USB3.0 console controller on computer by end points 0, the Data Input Interface in real-time data memory district is connected with the data image signal output interface of the high-precision adc of CCD front end by data/address bus, and its data output interface connects the real-time end points of described USB3.0, described data acquisition state machine is connected by zero data cached collection control line with described precision interval clock module, the output interface of described camera controller is exported shooting control signal by shooting control bus to CCD front controller.
Camera controller is for controlling the control data transmission on shooting control bus; USB3.0 micro-kernel processor is the operation processing unit CPU of USB3.0 main control module; Data acquisition state machine is for accepting the control of zero data cached collection control line, data acquisition state machine is according to the WE in the change operation real-time data memory district of signal condition on zero data cached collection control line, when the data/address bus synchronised clock CLK on zero data cached collection control line and normal pixel index signal PBLK are simultaneously effectively time, data acquisition state machine enables the WE in real-time data memory district, and now the data on data/address bus are just written in described real-time data memory district; Data acquisition state machine shifts synchronizing clock signals HD according to the row in zero data cached collection control line and frame transfer synchronizing clock signals VD carries out the synchronous of pixel column and picture frame; Real-time data memory district is for temporarily depositing the data that write from data/address bus; The real-time end points of data mode machine, real-time data memory district and USB3.0 forms does not wait for data transmission channel; Initiate the transfer of data from the real-time end points of USB3.0 to the computer being connected with USB3.0 main control module by not waiting for data transmission channel USB3.0 main control module; In the time that the data length in the real-time end points of USB3.0 reaches the length of a packet, USB3.0 main control module is just initiated the transfer of data to the computer being connected with USB3.0 main control module.
Please refer to Fig. 3, is the circuit theory diagrams of the embodiment of the present invention, and in figure, 01 is optical lens, and U1 is industrial CCD; U2 is high accuracy CCD front end, and U3 is USB3.0 main control module, and U4 is drive level modular converter, R1, R2, M1, C1 and between connection be signal condition module.U1 has selected ICX274AL chip in the present embodiment, and this chip is the interline transfer type area array CCD that Sony Corporation produces, and pixel is 2.01M, and the highest frame frequency was 20 frame/seconds.U2 has selected AD9927 chip, and U3 has selected CYUSB3014 chip, and U4 has selected 74ACT04 chip.
Spi bus in Fig. 3 and start/stop holding wire are shooting control bus; CLK, PBLK, HD and VD holding wire in figure is zero data cached collection control line in zero data cached acquisition interface;
The AD9927 chip Embedded that U2 selects CDS, VGA, CCD front-end control position, precision interval clock module, black level offset compensation and high-precision adc; Wherein the phase place of CDS adjustment precision is 0.52ns, VGA gain multiplication factor is adjustable between 1.5～42, it is 0.52ns that the phase place of precision interval clock module is adjusted precision, and high-precision adc is 14 bit A/D converters, and integral nonlinearity, differential nonlinearity and peak value are non-linear little.CDS is for carrying out correlated-double-sampling to the ccd output signal after described signal condition resume module; VGA is for amplifying the signal after described CDS correlated-double-sampling; Precision interval clock module is for generation of the driving signal of CCD; Black level offset compensation is for proofreading and correct the dark current value of the signal after out through VGA; CCD front-end control position is for arranging the parameter of CDS, VGA, precision interval clock module, black level offset compensation and high-precision adc.
CYUSB3014 chip internal that U3 selects is integrated ARM926EJ is as USB3.0 micro-kernel processor; CYUSB3014 chip internal is integrated SPI controller, is here camera controller, and for controlling spi bus, the parameter that can arrange in the CCD front controller in U2 by spi bus arranges position; CYUSB3014 chip internal is integrated data acquisition state machine, data buffer zone and USB3.0 end points; In the present embodiment the data buffer zone of CYUSB3014 chip internal is marked off to one as real-time data memory district, the USB3.0 end points of CYUSB3014 chip internal is marked off to a part as the real-time end points of USB3.0.
CLK signal in Fig. 3 is data/address bus synchronised clock, and HD is for row shifts synchronised clock, VD is that frame transfer synchronised clock, PBLK are normal pixel index signal, and their form state transitions control bus;
In Fig. 3, the 16th pin of U1 is connected to the K4 pin of U2, the 8th pin of U1 is connected to the J3 pin of U2, the 5th pin of U1 is connected to the H3 pin of U2, the 6th pin of U1 is connected to the H4 pin of U2, the 7th pin of U1 is connected to the F3 pin of U2, and the 2nd pin of U1 is connected to the G4 pin of U2, and the 3rd pin of U1 is connected to the G3 pin of U2, the 4th pin of U1 is connected to the F4 pin of U2, and the 1st pin of U1 is connected to the E4 pin of U2; Above-mentioned connection is the vertical driving signal that U2 produces, and above-mentioned vertical driving signal level can directly be exported and supply with U1.
The 19th pin of U1 is connected to the 2nd pin of chip 74ACT04, and the 14th pin of U1 is connected to the 4th pin of U4, and the 20th pin of U1 is connected to the 6th pin of U4, and the 13rd pin of U1 is connected to the 8th pin of U4, and the 12nd pin of U1 is connected to the 10th pin of U4; U4 is drive level conversion module, and above-mentioned connection is the horizontal drive signals of U2 generation and after U4, supplies with U1.
The 1st pin of U4 is connected to the F2 pin of U2, and the 5th pin of U4 is connected to the G1 pin of U2, and the 5th pin of U4 is connected to the H2 pin of U2, and the 9th pin of U4 is connected to the J1 pin of U2, and the 11st pin of U4 is connected to the J2 pin of U2; U4 is drive level conversion module, and above-mentioned connection is the horizontal drive signals of U2 generation and carries out level conversion through U4.
The G11 pin of U2 is connected to the G4 pin of U3, and this is connected to U3 start/stop holding wire, for start/stop U2.
The L9 pin of U2 is connected to the C1 pin of U3, and the M10 pin of U2 is connected to the D5 pin of U3, and the M11 pin of U2 is connected to the D4 pin of U3, and these three lines are spi bus, and the parameter that the CCD front controller in U2 can be set by spi bus U3 arranges position.
The K7 pin of U2 is connected to the K8 pin of U3, the M12 pin of U2 is connected to the K7 pin of U3, and the H11 pin of U2 is connected to the J7 pin of U3, and the J11 pin of U2 is connected to the H7 pin of U3, these four lines are zero data cached collection control line, and U2 is by the data acquisition state machine of this control line control U3 inside.
14 bit data bus of U2 are connected in low 14 bit data bus of U3.Data on this data/address bus are the data after U2 sampling.
Refer to Fig. 4, this figure is the transfer schematic diagram of interline transfer type area array CCD.
Refer to Fig. 5, this figure is the pixel map of ICX274AL chip, and in figure, black is black pixel, and white is normal pixel.In horizontal transfer register, register number is more than one-row pixels number, and the part having more is referred to as mute pixel.ICX274AL has 1688 row, 1248 row pixels; Wherein front 10 row and rear 2 row are black pixel entirely, and in middle every one-row pixels, first 12 is black pixel, and latter 48 is black pixel.
CCD driving method is for being divided into CCD mono-two field picture pixel reading duration, pixel transfer phase and air transport refunding.The pixel transfer phase is divided into vertical transitions phase and horizontal transfer phase; The horizontal transfer phase is divided into mute pixel and shifts phase, black pixel transfer phase and normal pixel transfer phase; One two field picture carries out synchronously with frame synchronizing signal, and the pixel phase of shifting carries out synchronously with line synchronizing signal;
Pixel reading duration is sensitization electric charge to be read into the time program process register from photosensitive area; The pixel transfer phase be by the sensitization electric charge in register line by line another migrate out the process of CCD; The air transport refunding is the empty transfer process after all pixels have all shifted.Can be seen from the foregoing and appoint one-row pixels finally all will transfer in horizontal transfer register, this process is just called the vertical transitions phase, migrates out one by one CCD from horizontal transfer register, and this process is just called the horizontal transfer phase.Can be seen from the foregoing that in horizontal transfer register, register number is more than one-row pixels number, the part having more is referred to as mute pixel, and therefore this part shifts and is just called mute pixel and shifts the phase.Can be seen from the foregoing front 10 row and rear 2 row is black pixel entirely, and in middle every one-row pixels, first 12 is black pixel, and latter 48 is black pixel, and the process that shifts black pixel is exactly that black pixel shifts the phase, and in like manner the remaining normal pixel that is called shifts the phase.
The parameter that CCD drives comprises the number, the length in air transport refunding, the driving signal characteristic of each phase of the position of black pixel, mute pixel etc.Drive parameter to set, driving and sampling module are just followed the prescribed order and are produced the driving of CCD, and do not need controller to interfere.
Refer to Fig. 6, by zero data cached acquisition method is taked state transitions mechanism figure; In this figure, ccd image collection is divided into five states, is respectively frame and starts, go beginning, wait for normal pixel, wait for data/address bus synchronised clock and readout data bus.State transition triggering signal is each signal on zero data cached collection control line, is respectively frame transfer synchronised clock VD, row transfer synchronised clock HD, data/address bus synchronised clock CLK and normal pixel index signal PBLK.
Starting of piece image is to start with the trailing edge of frame transfer synchronised clock VD, and frame initial state is initial condition; After frame initial state, and then enter row initial state; After row initial state, can enter wait normal pixel state, this state is waited for the normal pixel arrival in period; In the time that normal pixel index signal PBLK becomes high level, represent that normal pixel has started; And then just enter the arrival of waiting for data/address bus synchronised clock CLK rising edge, in the time that CLK rising edge arrives, represent that the data on data/address bus are the data that obtain after just sampling; Now enter readout data bus state, now data acquisition state machine can enable writing of real-time data memory district and enables, and allows the data on data/address bus to write real-time data memory district; Automatically jump to afterwards and wait for data/address bus synchronised clock, now data acquisition state machine does not enable writing of real-time data memory district and enables, and allows the data on data/address bus cannot write real-time data memory district; So move in circles until the normal pixel row of a pixel column has gathered, now PBLK signal can become low level, this signal can make state skip to and wait for normal pixel state, when the improper pixel of one-row pixels is also over period, one-row pixels is also just over, and now HD signal can produce trailing edge and makes state skip to row initial state; So circulation several rows, all provisional capitals in a two field picture have been crossed, and a two field picture is also just over, and enters next frame image, and now VD signal produces trailing edge, and state is skipped to initial condition frame initial state, starts a new two field picture.
Refer to Fig. 7, the video acquisition of USB3.0 high speed high definition industrial camera of the present invention and transmission operations flows key step are as follows:
1. set and drive parameter; Set zero point and range;
2. start video camera;
3. image data; In the present embodiment, for starting pin, there is a rising edge in the G11 pin of AD9927, start AD9927 on this pin, starts driving and the sampling of CCD.
4. data are preserved, are shown and analyze; As found, 5. zero point and range are not suitable for, enter; As want cut-away view picture, enter 6.; As want arrestment, enter 7.; Otherwise get back to 3.;
5. revise zero point and range, enter 3.;
6. cut-away view picture, 3. stop data collection (note: now CCD and driving sampling module are still in running order, just sampling data out are not read), enter as restarted image data;
7. arrestment.
In the present invention, do not wait for data transmission channel and zero data cached acquisition interface no-float, avoided employing memory device data cached, do not need data compression process unit yet, therefore also do not need process chip, these two factors have greatly reduced hardware cost.
In this specification, the present invention describes with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore specification and accompanying drawing should be considered to illustrative but not determinate.
Claims (4)
1. a USB3.0 high speed high definition industrial camera, comprise the optical lens for capture, optical lens capture is carried out to the industrial CCD of imaging, drive signal for generation of the CCD that drives industrial CCD output image signal, the high accuracy CCD front end of data image signal output is processed and analog picture signal is converted to the analog picture signal that receives industrial CCD output, described high accuracy CCD front end comprises for generation of CCD driving signal, the precision interval clock module of CDS clock and zero data cached collection control signal, for described industrial CCD output signal being carried out to the signal condition module of impedance transformation and DC level conversion, for the ccd output signal after described signal condition resume module being carried out to the CDS of correlated-double-sampling, for the VGA that the signal after described CDS correlated-double-sampling is amplified, be used for the black level offset compensation circuit of the dark current value of proofreading and correct the signal of exporting through VGA, for the image pickup signal after black level offset compensation being carried out to the high-precision adc of analog-to-digital conversion output, an and drive level conversion module, the CCD of described precision interval clock module drives signal output interface to drive signal input interface to be connected through drive level conversion module and industrial CCD,
It is characterized in that, described high accuracy CCD front end also comprises the CCD front controller of the parameter for CDS, VGA, precision interval clock module, black level offset compensation and high-precision adc are set; The output interface of camera controller is exported shooting control signal by shooting control bus to CCD front controller;
This industrial camera also comprises a USB3.0 main control module;
Described USB3.0 main control module comprises USB3.0 micro-kernel processor, generate the camera controller of camera control signal output according to USB3.0 micro-kernel processor instruction, for the real-time data memory district of caching image data, according to the data acquisition state machine of real-time data memory district WE described in zero data cached collection control signal control of precision interval clock module output, for with computer on USB3.0 console controller transmit image data the real-time end points of USB3.0 and with computer carry out USB3.0 control transmission end points 0, described USB3.0 micro-kernel processor is the operation processing unit of USB3.0 main control module, and it is connected with USB3.0 console controller on computer by end points 0, the Data Input Interface in real-time data memory district is connected with the data image signal output interface of the high-precision adc of CCD front end by data/address bus, and its data output interface connects the real-time end points of described USB3.0, described data acquisition state machine is connected by zero data cached collection control line with described precision interval clock module, the output interface of described camera controller is exported shooting control signal by shooting control bus to high accuracy CCD front end.
2. USB3.0 high speed high definition industrial camera according to claim 1, is characterized in that,
Described industrial CCD pixel is at least 1M;
Precision interval clock module phase place in described high accuracy CCD front end is adjusted precision and is at least 10ns;
High-precision adc in described high accuracy CCD front end is at least 8 ADC.
3. USB3.0 high speed high definition industrial camera according to claim 1, is characterized in that,
Described industrial CCD is interline transfer type area array CCD;
Zero described data cached collection control line comprises that row shifts synchronizing clock signals line, frame transfer synchronizing clock signals line, normal pixel index signal and data/address bus synchronizing clock signals line;
Described shooting control bus comprises spi bus and start/stop holding wire.
4. USB3.0 high speed high definition industrial camera according to claim 1, is characterized in that, described industrial CCD is made up of ICX274AL chip; The precision interval clock module of described high accuracy CCD front end, CDS, VGA, black level offset compensation circuit, high-precision adc, CCD front controller are integrated in an AD9927 chip; Described drive level conversion module adopts 74ACT04 chip; Described USB3.0 main control module is made up of CYUSB3014 chip.
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| CN201210056565.2A CN102638649B (en) | 2012-03-06 | 2012-03-06 | USB3.0 high-speed high-definition industrial camera |
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| CN201210056565.2A CN102638649B (en) | 2012-03-06 | 2012-03-06 | USB3.0 high-speed high-definition industrial camera |
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| CN102638649A CN102638649A (en) | 2012-08-15 |
| CN102638649B true CN102638649B (en) | 2014-06-11 |
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| CN104104820B (en) * | 2014-07-03 | 2017-03-22 | 宁波术有电子科技有限公司 | Realization method of low-power image acquisition device |
| CN104113709A (en) * | 2014-07-15 | 2014-10-22 | 西安电子科技大学 | Correlated double sampling circuit and variable gain amplifier integrated circuit |
| CN108093202A (en) * | 2016-11-22 | 2018-05-29 | 天津长城科安电子科技有限公司 | Video monitoring system based on DSP |
| CN107426485A (en) * | 2017-04-18 | 2017-12-01 | 深圳博电诚科国际贸易有限公司 | Image acquisition and processing device, method and system |
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| KR100890710B1 (en) * | 2008-04-14 | 2009-03-27 | (주)엠엔씨테크날러지 | Omni-directional imaging apparatus |
| CN101738827A (en) * | 2009-12-24 | 2010-06-16 | 北京优纳科技有限公司 | usb digital industrial camera |
| CN201957164U (en) * | 2010-11-08 | 2011-08-31 | 北京星敏科信息技术有限公司 | Camera image transmitting device |
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| KR100890710B1 (en) * | 2008-04-14 | 2009-03-27 | (주)엠엔씨테크날러지 | Omni-directional imaging apparatus |
| CN101738827A (en) * | 2009-12-24 | 2010-06-16 | 北京优纳科技有限公司 | usb digital industrial camera |
| CN201957164U (en) * | 2010-11-08 | 2011-08-31 | 北京星敏科信息技术有限公司 | Camera image transmitting device |
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