CN202472634U

CN202472634U - Synchronous dynamic random access memory (SDRAM) controller capable of fast responding and writing data

Info

Publication number: CN202472634U
Application number: CN2012200474061U
Authority: CN
Inventors: 苏培源
Original assignee: Fuzhou Rockchip Electronics Co Ltd
Current assignee: Rockchip Electronics Co Ltd
Priority date: 2012-02-14
Filing date: 2012-02-14
Publication date: 2012-10-03
Anticipated expiration: 2022-02-14

Abstract

The utility model provides a synchronous dynamic random access memory (SDRAM) controller capable of fast responding and writing data. The controller comprises an automatic X-ray inspection (AXI) bus interface, a data caching area, a reading and writing order queue register, an arbiter, an address filtering module, an order/data processing unit and an SDRAM protocol controller. The AXI bus interface is respectively connected with the address filtering module and the data caching area. The address filtering module is connected with the arbiter connected with the reading and writing order queue register, the reading and writing order queue register is respectively connected with the address filtering module and the order/data processing unit, the data caching area is connected with the order/data processing unit connected with the SDRAM protocol controller. The address filtering module filters writing operation of the same address, so that the SDRAM controller capable of fast responding and writing data improves efficiency of data writing of the SDRAM controller under the condition of ensuring the data reading and writing consistency of the SDRAM controller.

Description

A kind of sdram controller of quick response write data

[technical field]

The utility model relates to the design field of SOC chip, particularly a kind of sdram controller of quick response write data.

[background technology]

The SDARM controller is the important module in the SOC chip, mainly is responsible for the storage of dynamic data in the SOC system.The AMBA3AXI bus is widely used in embedding in the SOC chip, supports the sdram controller of AMBA3AXI bus to be widely used in the SOC System on Chip/SoC at present.The data-handling capacity that improves the SDRAM bus is important indicator of design sdram controller.

The structure of present sdram controller; As shown in Figure 1; SDRAM comprises AXI EBI, data buffer area, read write command queuing register, moderator, command processing unit and SDRAM protocol controller; Wherein the AXI EBI mainly is used for the read write command on the AXI main equipment is converted to the sdram controller internal command and submits to the moderator arbitration, simultaneously data is write data buffer area, and it is medium pending that the instruction after the arbitration is put into the read write command queuing register.By the time after data processing was accomplished, the AXI EBI sent the response signal that transmission is accomplished to the AXI main equipment, if read command is returned read data simultaneously and given the AXI main equipment.In order to improve the execution efficient of SDRAM protocol controller, present sdram controller is generally supported the caching function of write data, and write order and read command are arbitrated according to the characteristic of SDRAM.

But present sdram controller is in application; If have a plurality of AXI main equipments simultaneously frequent carry out reading and writing data to sdram controller; The write data of a main equipment in wherein a plurality of AXI main equipments possibly deposited in always and can not get timely processing in the data buffer area; Can let the SDRAM protocol controller become very long toward the time of the outer SDRAM peripheral hardware write data of sheet like this, this AXI main equipment just can be received response signal after data are sent a very long time like this, can be in waiting status so always; Do not do further processing, influenced the execution efficient of this AXI main equipment.

[summary of the invention]

The technical matters that the utility model will solve is to provide a kind of sdram controller of quick response write data.

The utility model is achieved in that a kind of sdram controller of quick response write data, comprises AXI EBI, data buffer area, read write command queuing register, moderator, command processing unit and SDRAM protocol controller; Also comprise the address filtering module, said AXI EBI is connected with address filtering module, data buffer area respectively; Said address filtering module is connected with said moderator; Said moderator is connected with said read write command queuing register; Said read write command queuing register is connected with said command processing unit with said address filtering module respectively; Said data buffer area is connected with said command processing unit; Said command processing unit is connected with said SDRAM protocol controller.

Further, said address filtering module comprises at least one address comparator and at least one Read Controller; Said read write command queuing register is connected with said address comparator; Said address comparator is connected with said Read Controller; Said Read Controller is connected with said moderator; Said AXI EBI is connected with Read Controller with said address comparator respectively.

The advantage of the utility model is: the utility model improves on existing sdram controller, has added the address filtering module, and its AXI EBI is connected with address filtering module, data buffer area respectively; Said address filtering module is connected with said moderator; Said moderator is connected with said read write command queuing register; Said read write command queuing register is connected with said command processing unit with said address filtering module respectively; Said data buffer area is connected with said command processing unit; Said command processing unit is connected with said SDRAM protocol controller.Filter the write operation of identical address through the address filtering module, guaranteeing that sdram controller reads and writes data under the conforming situation, has improved the efficient of sdram controller write data.

[description of drawings]

Fig. 1 is the structural representation of sdram controller in the prior art.

Fig. 2 is the structural representation of the utility model sdram controller.

Fig. 3 is the structural representation of the address filtering module of the utility model sdram controller.

Fig. 4 is the principle of work block diagram of the utility model sdram controller.

[embodiment]

See also shown in Figure 2ly, the sdram controller of a kind of quick response write data of the utility model comprises AXI EBI 1, data buffer area 2, read write command queuing register 3, moderator 4, command processing unit 5 and SDRAM protocol controller 6; Also comprise address filtering module 7, said AXI EBI 1 is connected with address filtering module 7, data buffer area 2 respectively; Said address filtering module 7 is connected with said moderator 4; Said moderator 4 is connected with said read write command queuing register 3; Said read write command queuing register 3 is connected with said command processing unit 5 with said address filtering module 7 respectively; Said data buffer area 2 is connected with said command processing unit 5; Said command processing unit 5 is connected with said SDRAM protocol controller 6.

Wherein, as shown in Figure 3, said address filtering module 7 comprises at least one address comparator 71 and at least one Read Controller 72; N address comparator 71 and N Read Controller 72 are arranged among Fig. 3, and said N is the natural number more than or equal to 1, an one of which address comparator 71 corresponding Read Controllers 72; Said read write command queuing register 3 is connected with said address comparator 71; Said address comparator 71 is connected with said Read Controller 72; Said Read Controller 72 is connected with said moderator 4; Said AXI EBI 1 is connected with Read Controller 72 with said address comparator 71 respectively.

The principle of work of the utility model is following:

As shown in Figure 4, AXI main equipment 0, AXI main equipment 1...AXI main equipment n are linked to each other with said AXI EBI 1; And the SDRAM protocol controller of sdram controller 6 connected the SDRAM external equipment; Existing is example to have only AXI main equipment 0 to the sdram controller write data; Principle of work is: AXI main equipment 0 sends write order to AXI EBI 1, and AXI EBI 1 changes into the sdram controller internal command with write order and submits to moderator 4 arbitrations, and it is medium pending that the data that will write simultaneously are put into data buffer area 2; After moderator 4 arbitrations order is sent to read write command queuing register 3; Begin simultaneously the data in the data buffer area 2 are transferred to the SDRAM peripheral hardware through command processing unit 5 and SDRAM protocol controller 6, after data were successfully write the SDRAM peripheral hardware, AXI EBI 1 was replied OKAY (agreement) response to AXI main equipment 0; In Fig. 4; The common treatment scheme of its AXI main equipment 0 write data requests is: carry out WR0 earlier, then WR1, WR2 at last; WR0:AXI main equipment 0 sends one and writes request, and sends to sdram controller to write data; The WR1:SDRAM controller sends to write data in the outer SDRAM peripheral hardware of sheet, WR2: successfully write sheet outside behind the SDRAM when data, AXI slave unit interface is replied the OKAY response to AXI main equipment 0, represent that current write data transmits completion.

Show with AXI main equipment 0 to the sdram controller write data; AXI main equipment 0 has exchanges data with AXI main equipment 1 simultaneously; And AXI main equipment 1 also carries out read data; The data that then will write when AXI main equipment 0 are put into that data buffer area 2 is medium when pending, and AXI main equipment 0 has exchanges data with AXI main equipment 1, and can visit the address with a slice SDRAM this moment simultaneously.Suppose that AXI main equipment 0 writes one group of data in SDRAM, AXI main equipment 0 notice AXI main equipment 1 goes reading of data in the identical address after accomplishing.After obtaining notifying, passes through AXI main equipment 1 read channel read data in sdram controller of AXI bus immediately.This time might AXI the write data of last time also be kept in the data buffer area 2 of sdram controller and do not write in the SDRAM peripheral hardware, at this moment to utilize address filtering module 7 to filter the write operation of identical address; Address filtering module 7 is at first searched the write operation whether identical address is arranged in the inner data buffer area 2 and is not accomplished; The read command address that is about to AXI main equipment 0 port and AXI main equipment 1 port compares through address comparator 71 with the request of the writing corresponding address of reading and writing in the queuing register 3; If the address is inconsistent read command being delivered to moderator 4 through Read Controller 71 arbitrates; Carry out normal flow processing; If the address unanimity with current read command through Read Controller 71 deliver to the read-write queuing register 3; Current read command is pinned up to read-write queuing register 3 and all write operations of this address correlation and in the SDRAM peripheral hardware, is accomplished, and then carries out the operation of AXI main equipment 1 read command.

The above is merely the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.

Claims

1. a sdram controller that responds write data fast comprises AXI EBI, data buffer area, read write command queuing register, moderator, command processing unit and SDRAM protocol controller; It is characterized in that: also comprise the address filtering module, said AXI EBI is connected with address filtering module, data buffer area respectively; Said address filtering module is connected with said moderator; Said moderator is connected with said read write command queuing register; Said read write command queuing register is connected with said command processing unit with said address filtering module respectively; Said data buffer area is connected with said command processing unit; Said command processing unit is connected with said SDRAM protocol controller.

2. the sdram controller of a kind of quick response write data according to claim 1 is characterized in that: said address filtering module comprises at least one address comparator and at least one Read Controller; Said read write command queuing register is connected with said address comparator; Said address comparator is connected with said Read Controller; Said Read Controller is connected with said moderator; Said AXI EBI is connected with Read Controller with said address comparator respectively.