CN202421683U - Intermediate product of TFT (thin film transistor) array substrate, array substrate and display device - Google Patents
Intermediate product of TFT (thin film transistor) array substrate, array substrate and display device Download PDFInfo
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- CN202421683U CN202421683U CN2012200060403U CN201220006040U CN202421683U CN 202421683 U CN202421683 U CN 202421683U CN 2012200060403 U CN2012200060403 U CN 2012200060403U CN 201220006040 U CN201220006040 U CN 201220006040U CN 202421683 U CN202421683 U CN 202421683U
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Abstract
An embodiment of the utility model provides an intermediate product of a TFT (thin film transistor) array substrate, an array substrate and a display device, which relate to the field of display technology and solve the problem that ESD (electro-static discharge) is generated in the manufacturing process of array substrates. The intermediate product comprises at least one unit substrate, each unit substrate comprises an effective display area and a peripheral lead area, a plurality of grid line leads and at least one grid line connecting wire are formed in the peripheral lead area, and the grid line connecting wires are electrically connected with at least two of the grid line leads. The intermediate product is used for manufacturing the TFT array substrate.
Description
Technical field
The utility model relates to the display technique field, relates in particular to a kind of intermediate product, array base palte and display device of tft array substrate.
Background technology
In TFT-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD), ESD (Electro-Static Discharge, electrostatic breakdown) can damage the inner structure of tft array substrate.
Prior art is through forming short-circuited conducting sleeve in Array (array) technology, and wherein, Array technology is the technology that forms array base palte.As shown in Figure 1, comprise at least one cell substrate 100, each cell substrate 100 comprises: effective viewing area 02 and peripheral leads district 01; Wherein, in said effective viewing area 02, form horizontal vertical data line crossing and grid line (not indicating among the figure); In said peripheral leads district 01, forming promising data line provides the data cable lead wire 03 of data-signal and goes between 04 for grid line provides the grid line of grid line sweep signal; And data cable lead wire 03 is connected with short-circuited conducting sleeve 05 respectively with grid line lead-in wire 04.When electric current hour; Short-circuited conducting sleeve 05 is in cut-off state; When ESD taking place produce big electric current, short-circuited conducting sleeve 05 is in conducting state, at this moment; Electric current is diffused into each data lines through short-circuited conducting sleeve 05 or grid line forms equipotential on each data lines or grid line, has reduced the damage of high pressure ESD to single-wire.
Because the design of above-mentioned short-circuited conducting sleeve is just to form after display (Array) the substrate manufacture completion at thin film transistor (TFT), can only prevent ESD damage that is produced after this.But, in the Array technological process, do not form before the short-circuited conducting sleeve, owing to the big electric current that factors such as technology produce moment causes the insulation course between the different metal layer to puncture, influence the product yield through regular meeting.Therefore for being that ESD before short-circuited conducting sleeve does not form can't prevent in the Array technological process.
The utility model content
The embodiment of the utility model provides a kind of intermediate product, array base palte and display device of tft array substrate, to solve the problem that in the array base palte manufacture process, produces ESD.
For achieving the above object, the embodiment of the utility model adopts following technical scheme:
A kind of intermediate product of tft array substrate are provided; A kind of intermediate product of tft array substrate; Comprise at least one cell substrate, said cell substrate comprises effective viewing area and peripheral leads district, it is characterized in that; In said peripheral leads district, be formed with several grid line lead-in wire and at least one grid line connecting lines, at least two electrical connections in said grid line connecting line and said several grid line lead-in wires.
Be formed with several data cable lead wires and at least one data line connecting line in said peripheral leads district, at least two in said data line connecting line and said several data cable lead wires are electrically connected.
Said grid line connecting line is electrically connected with all grid line lead-in wires, and said data line connecting line is electrically connected with all data cable lead wires.
Said grid line connecting line is electrically connected with said data line connecting line.
Said grid line connecting line is electrically connected with said data line connecting line and is specially:
Said data line connecting line is electrically connected through via hole at the overlapping place with said grid line connecting line.
The width of said grid line connecting line or data line connecting line is not less than the width of grid line or data line.
All grid line lead-in wires are provided with layer with at least one grid line connecting line, and perhaps, all data cable lead wires and at least one data line connecting line are provided with layer.
A kind of array base palte is provided,, is provided with at least one grid line connecting line, at least one data line connecting line in the peripheral leads district of said array base palte; Wherein, said at least one grid line connecting line is the more piece state of disconnection, and each joint of grid line connecting line is connected with a grid line lead-in wire; Said at least one data line connecting line is the more piece state of disconnection, and each joint of data line connecting line is connected with a data cable lead wire; Said grid line lead-in wire does not have with said data cable lead wire and is electrically connected.
A kind of display device is provided, comprises above-described array base palte.
The intermediate product of the tft array substrate that the utility model embodiment provides, array base palte and display device; Comprise at least one cell substrate; This cell substrate comprises effective viewing area and peripheral leads district; Wherein, In said peripheral leads district, be formed with several grid lines or data cable lead wire and at least one grid line or data line connecting line, at least two electrical connections in said grid line or data line connecting line and said several grid lines or the data cable lead wire, said grid line connecting line is electrically connected through the hole at the overlapping place with said data line connecting line.Like this, through in the manufacture process of array base palte, form a kind of intermediate product of tft array substrate; Make all grid line lead-in wires all be electrically connected with the grid line connecting line; All data cable lead wires all are connected with the data line connecting line, and the grid line connecting line is realized being electrically connected with the data line connecting line, thereby in the manufacture process of array base palte; If producing the ESD electric current no longer is in each root grid line, to spread; But on whole unit substrate grid line layer and data line layer, diffuse to form equipotential, thus avoided the damage of high pressure ESD to single-wire, improved yield of products.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiment of the utility model, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of tft array substrate intermediate product in the prior art;
The structural representation of the tft array substrate intermediate product that Fig. 2 provides for the utility model embodiment;
The structural representation of the another kind of tft array substrate intermediate product that Fig. 3 provides for the utility model embodiment;
Fig. 4 is that tft array substrate intermediate product shown in Figure 3 are at the structural representation that breaks off the array base palte that forms behind the connecting line.
Embodiment
To combine the accompanying drawing among the utility model embodiment below, the technical scheme among the utility model embodiment is carried out clear, intactly description, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
Brief account is the manufacture craft of display panels once: generally at female array base palte and female color membrane substrates (wherein; Female array base palte is meant the array base palte before the cutting; Female color membrane substrates is meant the color membrane substrates before the cutting) on include a plurality of cell substrates, on each cell substrate, be formed with pattern separately; Female array base palte and female color membrane substrates make the cell substrate (subarray substrate) of female array base palte and cell substrate (sub-color membrane substrates) correspondence of female color membrane substrates be provided with through to box technology; Afterwards, again through cutting technique, and subsequent technique a plurality of display panels that complete, each display panels comprises: to sub-color membrane substrates behind the box and subarray substrate.
A cell substrate in female array base palte before Fig. 1-Fig. 4 all can represent to cut; Wherein, the subarray substrate after Fig. 4 can also represent to cut.
The utility model embodiment provides a kind of intermediate product of tft array substrate, and is as shown in Figure 2, comprising:
At least one cell substrate 10; This cell substrate 10 comprises effective viewing area 2 and peripheral leads district 1; Wherein, in this peripheral leads district 1, be formed with several grid line lead-in wire 4 and at least one grid line connecting lines 6, at least two electrical connections in said grid line connecting line 6 and said several grid lines lead-in wires 4.
Further, be formed with several data cable lead wires 3 and at least one data line connecting line 7 in this peripheral leads district 1, at least two in several data cable lead wires 3 of this data line connecting line 7 and this are electrically connected.
Like this; Through in the manufacture process of array base palte, form a kind of intermediate product of tft array substrate, make all grid line lead-in wires all be electrically connected with the grid line connecting line; All data cable lead wires all are electrically connected with the data line connecting line; Thereby in the manufacture process of array base palte, no longer be in each root grid line or data line, to spread, but diffuseing to form equipotential on the grid line layer of whole unit substrate or on the data line layer if produce the ESD electric current; Thereby avoided the damage of high pressure ESD, improved yield of products single-wire.
Further, as shown in Figure 3, grid line connecting line 6 is electrically connected with all grid line lead-in wires 4 in the cell substrate 10, and this data line connecting line 7 is electrically connected with all data cable lead wires 3.
Preferably, data line connecting line 7 is electrically connected through via hole at the overlapping place with grid line connecting line 6.Need to prove that the mode of above-mentioned electrical connection can be any electric connection mode.
Further preferred, data cable lead wire and at least one data line connecting line are provided with layer; Further preferred, the grid line lead-in wire is provided with layer with at least one grid line connecting line.
In all embodiment of the utility model; Be meant the thin film that utilizes same material to process with layer; Be provided with at least two kinds of patterns with layer; Be meant at least two kinds of pattern setting with the structure on the thin film, concrete, be on the thin film that same material is processed, to form said at least two kinds of patterns through composition technology.To such scheme; Said data cable lead wire and at least one data line connecting line are meant that with layer setting data cable lead wire and at least one data line connecting line are two kinds of patterns on data line layer; Concrete manufacturing process does; The data line metallic film that completes is formed data line layer through composition technology; This data line layer comprises: the pattern of the pattern of data cable lead wire, at least one data line connecting line also comprises the pattern of the source-drain electrode of data line pattern and thin film transistor (TFT) (thin film transistor (TFT) that the present invention mentions is the thin film transistor (TFT) in each pixel in effective viewing area of tft array substrate) certainly according to prior art.Same; Said grid line lead-in wire is meant that with layer setting the grid line lead-in wire is two kinds of patterns at grid line layer with at least one grid line connecting line with at least one grid line connecting line; Concrete manufacturing process does; The grid metallic film that completes is formed grid line layer through composition technology, and this grid line layer comprises: the pattern of grid line lead-in wire and the pattern of at least one grid line connecting line further comprise according to prior art: the pattern of the grid of grid line and thin film transistor (TFT).Like this, just need not to increase new operation, the mask plate that only need change in the composition technology gets final product.
Below data line connecting line 7 and grid line connecting line 6 electric connection mode are specified.
Because preferred data line connecting line 7 is the pattern on the data Layer; Grid line connecting line 6 is the pattern on the grid line layer; Again owing to gate insulation layer between data line layer and the grid line layer; So when making gate insulation layer, can on data line connecting line 7 and position that grid line connecting line 6 needs be connected, not deposit the gate insulation layer material, so that both directly are electrically connected.Owing to can the whole unit substrate covered when generally depositing the gate insulation layer material, preferred in such cases, data line connecting line 7 can be realized being electrically connected with grid line connecting line 6 through via hole 8; Obviously, above-mentioned via hole 8 is formed on this gate insulation layer through composition technology.
Like this, through in the manufacture process of array base palte, form a kind of intermediate product of tft array substrate; Make all grid line lead-in wires all be electrically connected with the grid line connecting line; All data cable lead wires all are electrically connected with the data line connecting line, and the grid line connecting line is electrically connected with the data line connecting line, thereby in the manufacture process of array base palte; If producing the ESD electric current no longer is in each root grid line, to spread; But form equipotential in whole unit substrate internal divergence, thus avoided the damage of high pressure ESD to single-wire, improved yield of products.
The intermediate product of above-mentioned tft array substrate, this tft array substrate are in the data line layer that completes, and the short-circuited conducting sleeve that needs in the middle of data line connecting line 7, grid line connecting line 6 and the prior art to form is all accomplished making.
In subsequent technique, also need on this tft array substrate, make passivation layer and pixel electrode layer; Wherein, pixel electrode layer need link to each other with the drain electrode of thin film transistor (TFT) through the via hole on the passivation layer.
Need to prove that the data line connecting line of this tft array substrate, grid line connecting line are the ESD that in the middle of Array technology, is produced in order to prevent; In fact; For in the tft array substrate that completes between each grid line lead-in wire and do not have electrical connection between each data cable lead wire; Therefore also need the data line connecting line be broken off in the position of every data cable lead wire both sides, and the grid line connecting line is broken off in the position of every grid line lead-in wire both sides.
Particularly, the manufacturing process of above-mentioned turn-off data line connecting line and grid line connecting line can be according to following mode:
As shown in Figure 4; On passivation layer, form in the drain electrode and pixel electrode of via hole with the connection thin film transistor (TFT); The position of the position of every data cable lead wire both sides, every grid line lead-in wire both sides also forms via hole 9 on this passivation layer; In concrete etching process; Etching liquid can flow into along the via hole 9 that on data line connecting line 7 and grid line connecting line 6, forms, thereby etches away the corresponding part of via hole on data line connecting line 7 and the grid line connecting line 69, makes both all break off on the position accordingly.At this moment, data line connecting line 7 breaks off with grid line connecting line 6, thereby has lost the effect that prevents ESD, still, because short-circuited conducting sleeve 5 has formed, prevents the generation of ESD so can remain valid.
Need to prove; The mode of above-mentioned turn-off data line connecting line and grid line connecting line is broken off through via etch; Present embodiment is not limited thereto, and can also data line connecting line and grid line connecting line be broken off through the mode of cut, finally behind the display pannel molding process; Through cutting technique, with remaining data line connecting line and the excision of grid line connecting line.
The utility model provides a kind of array base palte, and is as shown in Figure 4, in the peripheral leads district 1 of array base palte, is provided with at least one grid line connecting line 6, at least one data line connecting line 7; Wherein, at least one grid line connecting line 6 is the more piece state of disconnection, and each joint of this grid line connecting line 6 is connected with a grid line lead-in wire 4; At least one data line connecting line 7 is the more piece state of disconnection, and each joint of this data line connecting line 7 is connected with a data cable lead wire 3; Grid line lead-in wire 4 does not have electrical connection with data cable lead wire 3.
The array base palte that the utility model embodiment provides in the manufacture process of this array base palte, forms a kind of intermediate product of tft array substrate; Make all grid line lead-in wires all be electrically connected with the grid line connecting line; All data cable lead wires all are electrically connected with the data line connecting line, and the grid line connecting line is electrically connected with the data line connecting line, thereby in the manufacture process of array base palte; If producing the ESD electric current no longer is in each root grid line, to spread; But form equipotential in whole unit substrate internal divergence, thus avoided the damage of high pressure ESD to single-wire, improved yield of products.
The utility model provides a kind of display device, comprises the tft array substrate described in above arbitrary embodiment.
The above; Be merely the embodiment of the utility model; But the protection domain of the utility model is not limited thereto; Any technician who is familiar with the present technique field can expect changing or replacement in the technical scope that the utility model discloses easily, all should be encompassed within the protection domain of the utility model.Therefore, the protection domain of the utility model should be as the criterion with the protection domain of said claim.
Claims (9)
1. the intermediate product of a tft array substrate; Comprise at least one cell substrate; Said cell substrate comprises effective viewing area and peripheral leads district; It is characterized in that, in said peripheral leads district, be formed with several grid line lead-in wire and at least one grid line connecting lines, at least two electrical connections in said grid line connecting line and said several grid line lead-in wires.
2. the intermediate product of tft array substrate according to claim 1; It is characterized in that; Be formed with several data cable lead wires and at least one data line connecting line in said peripheral leads district, at least two in said data line connecting line and said several data cable lead wires are electrically connected.
3. the intermediate product of tft array substrate according to claim 2 is characterized in that,
Said grid line connecting line is electrically connected with all grid line lead-in wires, and said data line connecting line is electrically connected with all data cable lead wires.
4. according to the intermediate product of each described tft array substrate of claim 1-3, it is characterized in that said grid line connecting line is electrically connected with said data line connecting line.
5. the intermediate product of tft array substrate according to claim 4 is characterized in that, said grid line connecting line is electrically connected with said data line connecting line and is specially:
Said data line connecting line is electrically connected through via hole at the overlapping place with said grid line connecting line.
6. according to the intermediate product of claim 2 or 3 described tft array substrates, it is characterized in that the width of said grid line connecting line or data line connecting line is not less than the width of grid line or data line.
7. according to the intermediate product of claim 2 or 3 described tft array substrates, it is characterized in that all grid line lead-in wires are provided with layer with at least one grid line connecting line, perhaps, all data cable lead wires and at least one data line connecting line are provided with layer.
8. an array base palte is characterized in that, in the peripheral leads district of said array base palte, is provided with at least one grid line connecting line, at least one data line connecting line; Wherein, said at least one grid line connecting line is the more piece state of disconnection, and each joint of grid line connecting line is connected with a grid line lead-in wire; Said at least one data line connecting line is the more piece state of disconnection, and each joint of data line connecting line is connected with a data cable lead wire; Said grid line lead-in wire does not have with said data cable lead wire and is electrically connected.
9. a display device is characterized in that, comprises the array base palte described in the claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200060403U CN202421683U (en) | 2012-01-06 | 2012-01-06 | Intermediate product of TFT (thin film transistor) array substrate, array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012200060403U CN202421683U (en) | 2012-01-06 | 2012-01-06 | Intermediate product of TFT (thin film transistor) array substrate, array substrate and display device |
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| CN202421683U true CN202421683U (en) | 2012-09-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103217845A (en) * | 2013-04-22 | 2013-07-24 | 京东方科技集团股份有限公司 | Lower substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal displayer |
| CN104133307A (en) * | 2013-05-03 | 2014-11-05 | 启耀光电股份有限公司 | Display panel and display device |
| CN104900589A (en) * | 2015-06-16 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN104900633A (en) * | 2015-03-30 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate fabrication method, array substrate and display device |
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2012
- 2012-01-06 CN CN2012200060403U patent/CN202421683U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103217845A (en) * | 2013-04-22 | 2013-07-24 | 京东方科技集团股份有限公司 | Lower substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal displayer |
| WO2014172964A1 (en) * | 2013-04-22 | 2014-10-30 | 京东方科技集团股份有限公司 | Lower substrate and manufacturing method therefor, liquid crystal display panel, and liquid crystal display |
| CN104133307A (en) * | 2013-05-03 | 2014-11-05 | 启耀光电股份有限公司 | Display panel and display device |
| CN104133307B (en) * | 2013-05-03 | 2017-07-04 | 台湾巴可科技股份有限公司 | Display panel and display device |
| CN104900633A (en) * | 2015-03-30 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate fabrication method, array substrate and display device |
| WO2016155258A1 (en) * | 2015-03-30 | 2016-10-06 | Boe Technology Group Co., Ltd. | Array substrates, methods for fabricating the same, and display device containing the same |
| US20170104016A1 (en) * | 2015-03-30 | 2017-04-13 | Boe Technology Group Co., Ltd | Array substrates, methods for fabricating the same, and display device containing the same |
| US9806103B2 (en) * | 2015-03-30 | 2017-10-31 | Boe Technology Group Co., Ltd. | Array substrates, methods for fabricating the same, and display device containing the same |
| CN104900589A (en) * | 2015-06-16 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and display device |
| CN104900589B (en) * | 2015-06-16 | 2017-11-10 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120905 |