CN101644867B - Driving device of gate line of liquid crystal display - Google Patents
Driving device of gate line of liquid crystal display Download PDFInfo
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- CN101644867B CN101644867B CN2009101950848A CN200910195084A CN101644867B CN 101644867 B CN101644867 B CN 101644867B CN 2009101950848 A CN2009101950848 A CN 2009101950848A CN 200910195084 A CN200910195084 A CN 200910195084A CN 101644867 B CN101644867 B CN 101644867B
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Abstract
The invention relates to adriving device of gate line of liquid crystal display, comprising a plurality of shifting registers. Each shifting register comprises a clock input terminal, a voltage terminal, a setting terminal, a resetting terminal, a carry terminal and an output terminal. A plurality of shifting registers is successively connected together in series and each shifting register comprises an electric charge-sharing device. The output terminal of the shifting register is connected with the current gate line through the electric charge-sharing device and the electric charge-sharing device of each shifting register is successively conducted. When the output terminal of the shifting register is high level, the electric charge-sharing device is in a conducting state and the conducting time is less than or equal to the duration of high level.The driving device of gate line of liquid crystal display provided in the invention is able to output adjustable chamfering driving signal and solves the problem that the display quality of panel reduces caused by capacitance coupling and RC delay.
Description
Technical field
The present invention relates to a kind of driving device of gate line of LCD, particularly relate to a kind of driving device of gate line that improves the LCD of gate line drive signal.
Background technology
Along with the development of amorphous silicon technology, the technology that gate drivers is embedded in the liquid crystal panel has obtained broad research.Use this kind structure, can save gate driving IC, remove the module assembling procedure from, greatly reduce the cost of LCDs.
Fig. 1 is the gate drivers block diagram of prior art, sees also Fig. 1, existing gate drivers comprise a plurality of grades of ST1, ST2 ..., STn+1, interconnect with cascade system, the order export signal Gout1, Gout2 ..., Goutn+1.Clock signal C K and direct grid current reference voltage Vss are connected to each line shift register.Every grade of shift register comprises clock terminal CK, power supply voltage terminal GV, reseting terminal R, set terminal S, grid lead-out terminal OUT1 and carry lead-out terminal OUT2.
The set terminal S input initial pulse STV of the first shift register ST1, the set terminal S of all the other shift register ST2 to STn links to each other with the carry lead-out terminal OUT2 of previous shift register.Grid lead-out terminal OUT1 output gated sweep signal is connected to the reseting terminal R of lastrow, the input reset signal simultaneously to gate lines at different levels.STn+1 is the dummy shift register, and output signal provides reset signal mainly for lastrow STn to gate line, imports the reset signal of initial pulse STV as STn+1 simultaneously.
Under the control of clock signal, initial pulse signal STV triggers the first shift register ST1, output Gout1 after the latter is shifted, simultaneously by the OUT2 output carry signal triggering second shift register ST2, ST2 displacement output Gout2 passes through OUT2 output carry signal triggering the 3rd shift register ST3 and input reset signal to the first shift register simultaneously to ST1 ... shift registers at different levels are shifted successively and export the gated sweep signal, as shown in Figure 2.
Input signals such as above-mentioned clock signal all are to realize with the square wave form, the output signal that obtains also is square-wave signal, and along with panel size strengthens, signal delay (RC delay) phenomenon is more and more serious, the capacitance coupling effect of panel is also very important simultaneously, thereby causes that the panel display quality descends.
Summary of the invention
Technical matters to be solved by this invention provides a kind of driving device of gate line, can export adjustable top rake drive signal, solves the panel display quality decline problem that capacitive coupling and RC delay causes.
The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of driving device of gate line, comprise a plurality of shift registers, each shift register comprises clock input terminal, voltage terminal, set terminal, reseting terminal, carry terminal and lead-out terminal;
Described a plurality of shift register is chained together successively, wherein, the set terminal of first line shift register links to each other with inceptive impulse, the set terminal of all the other shift registers links to each other with the carry terminal of lastrow shift register, and the reseting terminal of each shift register links to each other with the carry terminal of next line shift register;
The clock input terminal of each shift register links to each other with clock cable, and voltage terminal links to each other with the DC reference voltage signal wire, and lead-out terminal links to each other with the current line gate line, and each shift register is shifted successively and exports the gate line drive signal;
Wherein, each shift register comprises that electric charge shares device, the lead-out terminal of described shift register is shared device by electric charge and is linked to each other with the current line gate line, the electric charge of each shift register is shared device conducting successively, when the lead-out terminal of described shift register is high level, described electric charge is shared device and is in conducting state, and ON time is smaller or equal to high level lasting time.
Above-mentioned driving device of gate line, it is the TFT device that described electric charge is shared device, described TFT device comprises grid, source electrode and drain electrode, the grid of described TFT device links to each other with shared control signal wire, source electrode links to each other with the DC reference voltage signal wire, and drain electrode links to each other with the lead-out terminal and the current line gate line of described shift register.
Above-mentioned driving device of gate line, it is the TFT device that described electric charge is shared device, described TFT device comprises grid, source electrode and drain electrode, the grid of described TFT device links to each other with shared control signal wire, source electrode links to each other with the charge share voltage signal wire, and drain electrode links to each other with the lead-out terminal and the current line gate line of described shift register, and the signal on described shared control signal wire and the charge share voltage signal wire is opposite.
The present invention contrasts prior art following beneficial effect: driving device of gate line provided by the invention, share device by electric charge and regulate the gate line drive signal, thereby obtain adjustable top rake drive signal, solve the panel display quality decline problem that capacitive coupling and RC delay causes.
Description of drawings
Fig. 1 is the gate drivers block diagram of prior art;
Fig. 2 is the gate driver voltage oscillogram of prior art;
Fig. 3 is the block diagram of gate drivers of the present invention;
Fig. 4 is that electric charge of the present invention is shared device (CS) structural representation;
Fig. 5 is the driving voltage waveform figure of Fig. 3;
Fig. 6 is the block diagram of the gate drivers of another embodiment of the present invention;
Fig. 7 is the driving voltage waveform figure of Fig. 6.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.
Fig. 3 is the block diagram of gate drivers of the present invention.
See also Fig. 3, driving device of gate line of the present invention comprise a plurality of shift register ST1, ST2 ..., STn+1, each shift register comprises clock input terminal CK, voltage terminal GV, set terminal S, reseting terminal R, carry terminal OUT1 and lead-out terminal OUT2.
The clock input terminal CK of each shift register links to each other with clock cable, and voltage terminal GV links to each other with DC reference voltage signal wire Vss, and lead-out terminal OUT1 links to each other with current line gate lines G outi, and i is a natural number;
Described a plurality of shift register is chained together successively, and wherein, the set terminal of first line shift register links to each other with inceptive impulse STV, and the set terminal of all the other shift registers links to each other with the carry terminal of lastrow shift register;
Gate drivers comprise a plurality of grades of ST1, ST2 ..., STn+1, interconnect with cascade system, the order export signal Gout1, Gout2 ..., Goutn+1.Clock signal C K and DC reference voltage Vss are connected to each line shift register.Every grade of shift register comprises clock terminal CK, power supply voltage terminal GV, reseting terminal R, set terminal S, grid lead-out terminal OUT1 and carry lead-out terminal OUT2.
The set terminal S input initial pulse STV of the first shift register ST1, the set terminal S of all the other shift register ST2 to STn links to each other with the carry lead-out terminal OUT2 of previous row shift register, OUT2 is connected to the reseting terminal R of lastrow shift register simultaneously, the input reset signal.Grid lead-out terminal OUT1 signal is to electric charge sharing means at different levels (CS), STn+1 is the dummy shift register, output signal provides reset signal mainly for lastrow shift register STn to gate line, imports the reset signal of initial pulse STV as STn+1 simultaneously.
In the prior art, the lead-out terminal OUT1 of the reseting terminal R of each shift register and the shift register of next line or carry terminal OUT2 link to each other, modulate owing to the signal on the lead-out terminal OUT1 having been carried out the top rake signal among the present invention, in order not influence reset function, the reseting terminal R of each shift register preferably links to each other with the carry terminal OUT2 of the shift register of next line.
The present invention has compared with prior art increased an electric charge sharing means (CS), and an electric charge is shared control signal (CSH).Wherein, the electric charge sharing means inserts DC reference voltage Vss, electric charge is shared control signal CSH and shift register grid output signal, shares through electric charge and realizes exporting gate line to after the top rake.The reset signal of shift register inserts the output signal OUT2 of next line shift register, to guarantee the device steady operation.
Fig. 4 is that electric charge of the present invention is shared device (CS) structural representation.
See also Fig. 4, it is a TFT that electric charge of the present invention is shared device, connects output signal OUT1 and DC reference voltage Vss, by sharing sharing of control signal (CSH) control electric charge.
When CSH was in high level, TFT opened, and Vss is input to OUT1, when the grid high level signal is exported, dragged down output voltage, thereby obtained the grid voltage Gout with top rake, during the output of grid low level, can keep the grid output signal to be in low level, filtered noise.
Wherein, share control signal CSH and obtain by clock control circuit, its pulse width can be controlled in the clock circuit by counting unit and adjust, thereby can adjust the top rake width as required.
The output waveform figure that Fig. 5 obtains for the present invention.As shown, obtained the output signal of band top rake,, can adjust the width of top rake by sharing the control of control signal CSH.
Fig. 6 is the block diagram of the gate drivers of another embodiment of the present invention; Fig. 7 is the driving voltage waveform figure of Fig. 6.
See also Fig. 6 and Fig. 7, the difference of this embodiment and a last embodiment is to provide separately an electric charge to share the original DC reference voltage Vss of supply voltage VSH replacement.When CSH was in high level, TFT opened, conducting VSH and OUT1, and both electric charges are shared, thereby obtain the grid voltage Gout with top rake, during the output of grid low level, can keep the grid output signal to be in low level, filter noise.The VSH waveform signal can be set in clock signal circuit, thereby can effectively adjust the state of top rake signal.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (3)
1. the driving device of gate line of a LCD comprises:
A plurality of shift registers, each shift register comprise clock input terminal, voltage terminal, set terminal, reseting terminal, carry terminal and lead-out terminal;
Described a plurality of shift register is chained together successively, wherein, the set terminal of first line shift register links to each other with inceptive impulse, the set terminal of all the other shift registers links to each other with the carry terminal of lastrow shift register, and the reseting terminal of each shift register links to each other with the carry terminal of next line shift register;
The clock input terminal of each shift register links to each other with clock cable, and voltage terminal links to each other with the DC reference voltage signal wire, and lead-out terminal links to each other with the current line gate line, and each shift register is shifted successively and exports the gate line drive signal;
It is characterized in that, described drive unit comprises that also a plurality of electric charges share device, and shared control signal, and described shared control signal obtains by clock control circuit, its pulse width is controlled in the clock circuit by counting unit and adjusts, thereby adjusts the top rake width as required; The lead-out terminal of described shift register is shared device by electric charge and is linked to each other with the current line gate line, a plurality of electric charges are shared device conducting successively, when the lead-out terminal of described shift register is high level, described electric charge is shared device and is in conducting state, and ON time is smaller or equal to high level lasting time.
2. the driving device of gate line of LCD according to claim 1, it is characterized in that, it is the TFT device that described electric charge is shared device, described TFT device comprises grid, source electrode and drain electrode, the grid of described TFT device links to each other with shared control signal wire, and source electrode links to each other with the DC reference voltage signal wire, and drain electrode links to each other with the lead-out terminal and the current line gate line of described shift register.
3. the driving device of gate line of LCD according to claim 2 is characterized in that, the signal on described shared control signal wire and the charge share voltage signal wire is opposite.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101950848A CN101644867B (en) | 2009-09-03 | 2009-09-03 | Driving device of gate line of liquid crystal display |
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| CN2009101950848A CN101644867B (en) | 2009-09-03 | 2009-09-03 | Driving device of gate line of liquid crystal display |
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| CN101644867A CN101644867A (en) | 2010-02-10 |
| CN101644867B true CN101644867B (en) | 2011-05-18 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI433092B (en) | 2010-12-15 | 2014-04-01 | Novatek Microelectronics Corp | Method and device of gate driving in liquid crystal display |
| CN102543010A (en) * | 2010-12-30 | 2012-07-04 | 联咏科技股份有限公司 | Gate driving method and device of liquid crystal display device |
| CN103177703B (en) * | 2013-03-27 | 2015-05-13 | 京东方科技集团股份有限公司 | Grid driving circuit, display panel and display device |
| CN104425035B (en) * | 2013-08-29 | 2017-07-28 | 北京京东方光电科技有限公司 | Shift register cell, shift register and display device |
| CN104391411B (en) * | 2014-12-16 | 2017-06-06 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel |
| CN104778937B (en) * | 2015-05-08 | 2017-09-22 | 京东方科技集团股份有限公司 | Gate driving circuit, array base palte and display device |
| CN104952409B (en) | 2015-07-07 | 2018-12-28 | 京东方科技集团股份有限公司 | Drive element of the grid and its driving method, gate driving circuit and display device |
| CN105118454A (en) | 2015-08-28 | 2015-12-02 | 深超光电（深圳）有限公司 | Liquid crystal display panel |
| CN105206248B (en) | 2015-11-09 | 2019-07-05 | 重庆京东方光电科技有限公司 | Display driver circuit, display device and display driving method |
| CN109389926B (en) * | 2017-08-11 | 2022-02-25 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and array substrate |
| CN108257578A (en) * | 2018-04-16 | 2018-07-06 | 京东方科技集团股份有限公司 | Shift register cell and its control method, gate drive apparatus, display device |
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| CN1282886A (en) * | 1993-12-27 | 2001-02-07 | 夏普公司 | Image display device and scanning circuit |
| JP2004078172A (en) * | 2002-06-15 | 2004-03-11 | Samsung Electronics Co Ltd | Shift register driving method, shift register, and liquid crystal display device provided with same |
| JP2006260621A (en) * | 2005-03-15 | 2006-09-28 | Casio Comput Co Ltd | Shift register circuit, its driving control method, and driving control apparatus |
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2009
- 2009-09-03 CN CN2009101950848A patent/CN101644867B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1282886A (en) * | 1993-12-27 | 2001-02-07 | 夏普公司 | Image display device and scanning circuit |
| JP2004078172A (en) * | 2002-06-15 | 2004-03-11 | Samsung Electronics Co Ltd | Shift register driving method, shift register, and liquid crystal display device provided with same |
| JP2006260621A (en) * | 2005-03-15 | 2006-09-28 | Casio Comput Co Ltd | Shift register circuit, its driving control method, and driving control apparatus |
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Owner name: NANJING CEC PANDA LCD TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SVA (GROUP) CO., LTD. Effective date: 20110616 |
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Free format text: CORRECT: ADDRESS; FROM: 200233 BUILDING 3, NO. 757, YISHAN ROAD, XUHUI DISTRICT, SHANGHAI TO: 210038 NO. 9, HENGYI ROAD, NANJING ECONOMIC AND TECHNOLOGICAL DEVELOPMENT ZONE, NANJING CITY, JIANGSU PROVINCE |
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Effective date of registration: 20110616 Address after: 210038 Nanjing economic and Technological Development Zone, Jiangsu Province, Hengyi Road, No. 9, No. Patentee after: Nanjing CEC Panda LCD Technology Co., Ltd. Address before: 200233, Shanghai, Yishan Road, No. 757, third floor, Xuhui District Patentee before: SVA (Group) Co., Ltd. |