CN202330526U - Input offset voltage test circuit of high-precision dynamic comparator - Google Patents
Input offset voltage test circuit of high-precision dynamic comparator Download PDFInfo
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- CN202330526U CN202330526U CN201120470466XU CN201120470466U CN202330526U CN 202330526 U CN202330526 U CN 202330526U CN 201120470466X U CN201120470466X U CN 201120470466XU CN 201120470466 U CN201120470466 U CN 201120470466U CN 202330526 U CN202330526 U CN 202330526U
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- comparer
- offset voltage
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- input offset
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Abstract
The utility model relates to an input offset voltage test circuit of a high-precision dynamic comparator. The input offset voltage test circuit comprises a comparator, a clock control SR (scanning radiometer) latch, a unit gain amplifier, a buffer and a second-order integrater, wherein the input end of the clock control SR latch is connected with the output end of the comparator; the input end of the unit gain amplifier is connected with the output end of the clock control SR latch; the input of the buffer is the output of the unit gain amplifier, so that the driving capacity and the loading capacity of the buffer are improved; and the input end of the second-order integrater is connected with the output end of the buffer, and the output end of the second-order integrater supplies feedback voltage to the comparator. According to the utility mode, an input offset voltage can be obtained by one-time simulation of the dynamic comparator, and the test precision can be artificially controlled, so that quickness and accurate adjustability of a test are realized.
Description
Technical field
The utility model relates to a kind of input offset voltage test circuit of Dynamic High-accuracy comparer.
Background technology
Dynamic comparer is widely used in analog to digital converter, and in the systems such as data acquisition, the high-precision dynamic comparer development of wherein low input offset voltage is particularly rapid, but corresponding emulation mode also exists significant limitation.Traditional emulation mode is: the open loop comparer of amplifier structure can obtain input offset voltage through DC scanning; Promptly at an input end input reference signal of open loop comparer; At direct current signal of other end input; Be made as variable, carry out parameter scanning then, the turning point voltage during output generation saltus step as a result and the difference of reference signal voltage are offset voltage.
Because comparer can't carry out DC scanning.Therefore, attempt in order to find actual misalignment threshold voltage must import various signals.The deviser must use repeatedly emulation and the method for approaching one by one obtains actual misalignment threshold voltage, has promptly just begun to pre-estimate the input offset voltage value what are, then in signal difference of input end input of comparer; If comparer can correctly be differentiated, that just explains signal difference greater than input offset voltage, and it is poor that just reduces input signal; Emulation is once more seen and can be compared, if can not compare; Explain that secondary input signal difference is littler than actual input offset voltage, comparer can't normally compare, and that signal difference of importing for the third time is just little than primary; Bigger than for the second time, so repeatedly, approach one by one and compare.
The method consumption energy consuming time very of this traditional measurement comparer input offset voltage.When the input offset voltage value can easily obtain, will accelerate to design the progress with emulation so, this also makes and finds seem especially important of an effective input offset voltage method of testing.
Summary of the invention
The purpose of the utility model provides a kind of input offset voltage test circuit of Dynamic High-accuracy comparer, can realize just can obtaining input offset voltage to an emulation of dynamic comparer.
The circuit of the utility model adopts following scheme to realize: a kind of test circuit of Dynamic High-accuracy comparer, it is characterized in that, and comprising: a comparer; One clock SR latch; Its input end is connected with the output terminal of said comparer; One unity gain amplifier, its input end is connected with the output terminal of said clock SR latch; One impact damper, its input end is connected with the output terminal of said unity gain amplifier; An and second-order integrator; Its input end is connected with the output terminal of said impact damper, and output terminal is that said comparer provides a feedback voltage
.
In the utility model one embodiment, comprise that further one is used to control the clock circuit of said comparator works.
The utlity model has following advantage:
1, succinct rapidity: can only pass through transient state emulation in the method for testing of conventional dynamic comparer, trial again and again, this method of testing of approaching one by one, this test circuit only needs emulation once just can obtain comparer input offset voltage accurately.
2, precision is adjustable: therefore will improve the precision of this method of testing, the peak-to-peak value of waveform size in the time of will reducing balance as much as possible.Because the cycle of clock is fixed, can change the integration slope through the gain size that second-order integrator is set.Gain is provided with more little, and peak-to-peak value is more little, and precision is high more.
Description of drawings
Fig. 1 is that the utility model embodiment test circuit connects synoptic diagram.
Fig. 2 is the simulation waveform figure of the utility model embodiment dynamic comparer when not having input offset voltage.
Simulation waveform figure when Fig. 3 is the utility model embodiment dynamic comparer input offset voltage.
Embodiment
Present embodiment provides a kind of input offset voltage test circuit of Dynamic High-accuracy comparer, and it comprises: a comparer; One clock SR latch; Its input end is connected with the output terminal of said comparer; One unity gain amplifier, its input end is connected with the output terminal of said clock SR latch; One impact damper, its input end is connected with the output terminal of said unity gain amplifier; An and second-order integrator; Its input end is connected with the output terminal of said impact damper, and output terminal is that said comparer provides a feedback voltage
.
Further specify below in conjunction with the realization principle of accompanying drawing the utility model.
As shown in Figure 1, the output signal of clock SR latch
and
receive the input end of desirable unity gain amplifier.Desirable unity gain amplifier
; As
is high; Then amplifier is exported high level; Be supply voltage VDD; As
is high, and then unity gain amplifier is output as negative VDD.Second-order integrator is according to the positive and negative forward integration and the reverse integral of carrying out of impact damper output signal.Clock is the clock of control comparator works, and when establishing clock and transferring high level to by low level, comparer begins normal comparison.
The hypothesis comparer does not have input offset voltage now; And it is to be lower than reference voltage that the output signal of second-order integrator
(Voltage Feedback) has just begun;
is high;
is low; Just the output signal of unity gain amplifier
is greater than zero, and second-order integrator is carried out the forward integration.When the rising edge of clock arrives; If
surpassed the reference voltage of positive input; So; The output generation saltus step of comparer;
is low;
is high; Make
less than zero, second-order integrator transfers reverse integral to by the forward integration.When next rising edge clock comes interim; Second-order integrator is through the reverse integral of a clock period;
is less than reference voltage; Saltus step takes place again in the output of comparer, and second-order integrator has begun the forward integration again, carries out so repeatedly; Whole loop reaches steady state (SS), and simulation waveform figure is as shown in Figure 2.
If comparer has input offset voltage; Suppose to have the input offset voltage
of individual forward at the IP of comparer end; So; When effective clock edge is come interim; The input signal of comparer IN end must be greater than
, and the output result of comparer just saltus step can take place.That is to say and be equivalent to actual reference voltage
.In the time of balance, explain that the output signal of second-order integrator has passed through new reference line.Article two, the difference of reference voltage line
is exactly the input offset voltage of comparer.
Temporarily next when effective clock, as long as the output signal of second-order integrator is greatly perhaps littler than actual reference voltage, and the output of comparer will change.Usually; We get peak-to-peak value half as new reference voltage line, like
of Fig. 3.Can there be deviation in such value, like
among Fig. 3.The maximal value of this deviation is the half the of peak-to-peak value.Therefore to improve the precision of this method of testing, the peak-to-peak value of waveform size in the time of will reducing balance as much as possible.Because the cycle of clock is fixed, can change the integration slope through the gain size that second-order integrator is set.Gain is provided with more little, and peak-to-peak value is more little, and precision is high more, but integrating rate is slow, and simulation time has extended, and therefore, has trade-off relation aspect simulation accuracy and the simulation time.
What deserves to be mentioned is that the test circuit of the utility model can be widely used in Cadence, ADS; Hspice; Multiple IC design platform such as Pspice, wherein the i.e. also ideal model of side circuit of second-order integrator module and unity gain module is lower to the requirement of test macro; Simulation time greatly reduces simultaneously, needs also lower to hardware such as servers.
The above is merely the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.
Claims (2)
1. the input offset voltage test circuit of a Dynamic High-accuracy comparer is characterized in that, comprising:
One comparer;
One clock SR latch; Its input end is connected with the output terminal of said comparer;
One unity gain amplifier, its input end is connected with the output terminal of said clock SR latch;
One impact damper, its input end is connected with the output terminal of said unity gain amplifier;
And
One second-order integrator; Its input end is connected with the output terminal of said impact damper, and its output terminal is that said comparer provides a feedback voltage
.
2. the input offset voltage test circuit of Dynamic High-accuracy comparer according to claim 1 is characterized in that: comprise that further one is used to control the clock circuit of said comparator works.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120470466XU CN202330526U (en) | 2011-11-24 | 2011-11-24 | Input offset voltage test circuit of high-precision dynamic comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120470466XU CN202330526U (en) | 2011-11-24 | 2011-11-24 | Input offset voltage test circuit of high-precision dynamic comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202330526U true CN202330526U (en) | 2012-07-11 |
Family
ID=46442502
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201120470466XU Expired - Fee Related CN202330526U (en) | 2011-11-24 | 2011-11-24 | Input offset voltage test circuit of high-precision dynamic comparator |
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|---|---|
| CN (1) | CN202330526U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112394217A (en) * | 2020-10-22 | 2021-02-23 | 国网浙江省电力有限公司电力科学研究院 | High-speed precise signal processing system and method for monitoring high-frequency partial discharge |
| CN116125256A (en) * | 2023-04-17 | 2023-05-16 | 上海灵动微电子股份有限公司 | Parameter testing method and system for comparator |
-
2011
- 2011-11-24 CN CN201120470466XU patent/CN202330526U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112394217A (en) * | 2020-10-22 | 2021-02-23 | 国网浙江省电力有限公司电力科学研究院 | High-speed precise signal processing system and method for monitoring high-frequency partial discharge |
| CN112394217B (en) * | 2020-10-22 | 2022-05-17 | 国网浙江省电力有限公司电力科学研究院 | High-speed precise signal processing system and method for monitoring high-frequency partial discharge |
| CN116125256A (en) * | 2023-04-17 | 2023-05-16 | 上海灵动微电子股份有限公司 | Parameter testing method and system for comparator |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120711 Termination date: 20141124 |
|
| EXPY | Termination of patent right or utility model |