CN112394217A - High-speed precise signal processing system and method for monitoring high-frequency partial discharge - Google Patents
High-speed precise signal processing system and method for monitoring high-frequency partial discharge Download PDFInfo
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- CN112394217A CN112394217A CN202011142618.3A CN202011142618A CN112394217A CN 112394217 A CN112394217 A CN 112394217A CN 202011142618 A CN202011142618 A CN 202011142618A CN 112394217 A CN112394217 A CN 112394217A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/145—Indicating the presence of current or voltage
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- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
- Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
- Y04S40/126—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wireless data transmission
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Abstract
The invention discloses a high-speed precise signal processing system and method for monitoring high-frequency partial discharge, and belongs to the technical field of partial discharge detection of power equipment. A high-speed precise signal processing system for monitoring high-frequency partial discharge comprises an antenna, a filtering amplification circuit, a zero bias detector, a precise high-speed composite amplifier circuit, a comparator circuit, a monostable trigger circuit and a transistor reset integrator circuit; the invention processes the partial discharge signal through the precise high-speed composite amplifier circuit, limits the partial discharge offset within a certain range, thereby improving the signal precision, and ensures that the sensitivity of the detector is not reduced due to the load because the input of the partial discharge offset presents high impedance. On the premise of ensuring large bandwidth and high precision, the requirements on high-speed direct conversion and high-speed signal processing are met. The invention adds T feedback, and reduces useless bias voltage of input bias current amplified by the feedback resistor under the condition of certain input signal frequency.
Description
Technical Field
The invention relates to a high-speed precise signal processing system and method for monitoring high-frequency partial discharge, and belongs to the technical field of partial discharge detection of power equipment.
Background
The measurement of partial discharges is a common means of monitoring the insulation condition of high voltage equipment. The existing detection methods are mainly divided into wired and wireless methods, wherein the wireless measurement method has strong attraction and expandability.
However, the existing wireless monitoring technology detects the arrival time difference of the partial discharge signal through a plurality of sensors distributed in space, has high requirements on the sampling speed, is accompanied by high power consumption and high cost, and has low detection precision.
Disclosure of Invention
In view of the drawbacks of the prior art, the present invention is directed to a signal processing system having a precise high-speed composite amplifier circuit, a comparator circuit, a transistor reset integrator circuit with T feedback; the requirements of large bandwidth and high precision can be met, and effective detection and processing of high-frequency partial discharge signals are realized; the high-speed precise signal processing system and the method for monitoring the high-frequency partial discharge can effectively reduce power consumption and cost and have high detection precision.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a high-speed precise signal processing system for monitoring high-frequency partial discharge,
the circuit comprises an antenna, a filtering amplification circuit, a zero bias detector, a precise high-speed composite amplifier circuit, a comparator circuit, a monostable trigger circuit and a transistor reset integrator circuit;
the filtering and amplifying circuit is used for filtering a large amount of noise interference in the measuring process;
the zero bias detector is an energy sensing element and is used for coupling the power emitted by the output end of the power amplifier and outputting the power to the back-end processor for monitoring and adjustment, and the zero bias detector can generate a baseband output voltage which is in direct proportion to the radio frequency input power;
the precise high-speed composite amplifier circuit is used for limiting partial discharge offset below a certain range so as to enable the circuit to reach direct current precision;
the comparator circuit is used for setting the threshold value of the comparator to be obviously higher than the level of background noise so as to ensure that the possibility of false triggering is reduced;
the monostable trigger circuit is used for counting partial discharge signals;
the transistor reset integrator circuit is a high-input-impedance, high-speed and precise integrator, and has very low direct current drift between received partial discharge signals, and comprises a T-shaped feedback circuit, wherein under the condition that the frequency of input signals is certain, the feedback resistance is far smaller than that of a feedback resistance in a common integrator circuit under the same condition, so that useless bias voltage of the input bias current amplified by the feedback resistance is reduced;
the antenna detects a device partial discharge signal, and the partial discharge signal is amplified and filtered through the filtering and amplifying circuit; filtering a large amount of noise interference in the measurement process to avoid the distortion of the measurement signal;
then sending the processed signal to a zero bias detector;
the zero bias detector outputs corresponding baseband output voltage to the precise high-speed composite amplifier circuit;
the precise high-speed composite amplifier circuit amplifies an input detection signal and outputs the detection signal to the comparator circuit and the transistor reset integrating circuit;
the transistor reset integrator circuit is triggered to work by setting the threshold voltage of the comparator circuit, so that the monitoring of the high-frequency partial discharge is realized.
The invention is provided with a signal processing system of a precise high-speed composite amplifier circuit, a comparator circuit and a transistor reset integrator circuit with T feedback; the requirements of large bandwidth and high precision can be met, and effective detection and processing of high-frequency partial discharge signals are realized; the power consumption and the cost can be effectively reduced, and the detection precision of the high-frequency partial discharge is improved.
The invention processes the partial discharge signal through the precise high-speed composite amplifier circuit, limits the partial discharge offset within a certain range, thereby improving the signal precision, and ensures that the sensitivity of the detector is not reduced due to the load because the input of the partial discharge offset presents high impedance. On the premise of ensuring large bandwidth and high precision, the requirements on high-speed direct conversion and high-speed signal processing are met.
The invention sets a comparator circuit between the precise high-speed composite amplifier circuit and the transistor reset integrator circuit, enables the integrator circuit through the comparator, and when the received signal is reduced below the threshold value of the comparator, the integrator circuit enters the holding mode, thereby greatly prolonging the service life of the battery, obviously reducing the power supply current of the sensor node and increasing the working time of the sensor.
The transistor reset integrator circuit of the invention is a high-input impedance, high-speed and precise integrator, and has very low direct current drift between received partial discharge signals. And T feedback is added, so that the resistance value of the feedback resistor is reduced under the condition that the frequency of an input signal is constant, and useless bias voltage of the input bias current amplified by the feedback resistor is reduced.
The T-type integrating circuit is compatible with the characteristic that the common integrating circuit is connected with an adjustable balance resistor and a bleeder resistor is added to reduce the influence of input offset voltage on the system function, and can greatly reduce the useless bias of input bias current on signal output under the condition of inputting signals with the same frequency.
As a preferable technical measure:
the filtering and amplifying circuit comprises a band-pass filter, a band-stop filter and a low-noise amplifier. The method is mainly used for filtering a large amount of noise interference in the measurement process so as to avoid the distortion of a measurement signal.
The frequency range of the radiative partial discharge is typically between 50-800MHz, with most of the energy below 300 MHz. Therefore, the measurement band is selected within this range.
The band-pass filter is used for eliminating all interference and noise except a 30-320MHz partial discharge measurement frequency band;
the band elimination filter is used for eliminating coherent interference (mainly from FM broadcasting, digital television and DAB transmission) in the range of 70-250 MHz;
the low-noise amplifier is used for improving the signal-to-noise ratio of signal output, so that the high sensitivity of the sensor is ensured.
As a preferable technical measure:
the zero bias detector comprises a resistor thirty, a diode I, a diode II, a resistor forty and a capacitor ten;
the input end of the zero bias detector circuit is connected with one end of a resistor thirty, the anode of a diode I and the cathode of a diode II;
the negative electrode of the diode I is connected with one end of the resistor forty, one end of the capacitor ten and the output end of the circuit;
the other end of the resistor thirty, the anode of the diode two, the other end of the resistor forty and the other end of the capacitor ten are all grounded.
As a preferable technical measure:
the precise high-speed composite amplifier circuit comprises an operational amplifier I, an operational amplifier II, a field effect transistor I, a triode II, a capacitor I, a capacitor II, a resistor I, a resistor II, a resistor III, a resistor IV, a resistor V, a resistor VI, a resistor seven, a resistor eight and a resistor nine;
the circuit is built around a 500 muA 105MHz bipolar operational amplifier I, and closed loop voltage gain is set through the resistance values of a resistor III and a resistor IV.
As a preferable technical measure:
the first field effect transistor is a junction field effect transistor, and the input stage of a transistor source electrode follower provides high impedance and low noise input; the first field effect transistor is biased to be 500 muA through a first reference current source and a second reference current source;
this arrangement typically causes voltage and temperature drift, so it is stabilized by using an 18 μ a, 3 μ V offset precision op amp two, which provides dc compensation for the bias voltages of the fet one and op amp one;
the operational amplifier monitors the dc component of this voltage through a low pass filter to ensure that the detected partial discharge signal is completely removed and compared to the input dc voltage through the same filter;
then, the output of the operational amplifier II adjusts the direct current level of the summing point of the operational amplifier I into the bias voltage of the field effect transistor I, so that the output direct current offset error is equal to the output direct current offset error of the operational amplifier II multiplied by the closed-loop gain of the operational amplifier I;
voltage offset and temperature drift are also limited to the second operational amplifier; therefore, partial discharge offset is limited below a certain range, so that the circuit reaches the direct current precision.
As a preferable technical measure:
the input end of the precise high-speed composite amplifier circuit is connected with the grid of the first field effect transistor and one end of the first resistor;
the source electrode of the first field effect transistor is connected with the input pin + of the first operational amplifier and the collector electrode of the first triode;
the base electrode of the first triode is connected with one end of the resistor eight and the collector electrode of the second triode;
the emitter of the first triode is connected with one end of the resistor nine and the base of the second triode;
the other end of the resistor nine and the emitting electrode of the triode II are connected with external negative voltage;
the drain electrode of the field effect transistor I and the other end of the resistor eight are connected with an external positive voltage;
the other end of the resistor I is an input pin of an operational amplifier II and one end of the capacitor I;
the output end of the operational amplifier II and the other end of the capacitor I are connected with one end of the resistor II;
the other end of the second resistor is connected with one end of the third resistor, one end of the fourth resistor and an input pin of the first operational amplifier;
the output end of the operational amplifier II, the other end of the resistor III and one end of the resistor V are connected with the input ends of the transistor reset integrator circuit and the amplifier circuit;
the other end of the resistor five is connected with one end of the resistor six and one end of the resistor seven;
the other end of the resistor seven is an input pin + of the operational amplifier II and one end of the capacitor II;
the other end of the second capacitor, the other end of the sixth resistor and the other end of the fourth resistor are grounded.
As a preferable technical measure:
the comparator circuit comprises an amplifier III, a comparator IV, a capacitor III, a resistor eleven, a resistor twelve, a resistor thirteen, a resistor fourteen and a resistor fifteen;
the comparator circuit is a low-power-consumption high-speed comparator, firstly, an input signal is amplified through a high-speed in-phase amplifier III, so that the threshold value of the comparator is allowed to be set to be obviously higher than the level of background noise, and the possibility of false triggering is reduced;
activating the transistor reset integrator circuit and triggering the monostable trigger circuit by setting the threshold voltage of the comparator section (by adjusting resistor fourteen and resistor fifteen);
when receiving the partial discharge pulse each time, the monostable trigger circuit outputs the pulse to the microcontroller to provide digital counting;
the input end of the comparator circuit is connected with an input pin + of the amplifier III;
an output pin of the amplifier III is connected with one end of the resistor twelve and one end of the resistor eleven;
the other end of the resistor eleven is connected with an input pin-of the amplifier III and one end of the resistor eleven. The other end of the resistor twelve is connected with one end of the resistor thirteen and an input pin + of the comparator four. The other end of the resistor thirteen and an output pin of the comparator four are connected with the input end of the monostable trigger circuit and the input end of the transistor reset integrator circuit;
an input pin of the comparator IV is connected with the fourteen resistor, the fifteen resistor and one end of the capacitor III;
the other end of the resistor fourteen is connected with an external positive voltage. The other end of the resistor fifteen, the other end of the resistor ten and the other end of the capacitor three are grounded.
As a preferable technical measure:
the monostable trigger circuit is used for counting the partial discharge signals, and when receiving the partial discharge pulse each time, the monostable trigger circuit provides digital counting for the output pulse of the microcontroller.
The monostable is set to a duration of 5 mus to ensure that the microcontroller has sufficient time to acknowledge the signal.
The transistor reset integrator circuit comprises a switch, an amplifier five, an amplifier six, an amplifier eight, a comparator seven, a field effect transistor four, a transistor five, a transistor six, a capacitor five, a capacitor six, a capacitor seven, a resistor seventeen, a resistor eighteen, a resistor nineteen, a resistor twenty-one, a resistor twenty-two, a resistor twenty-three, a resistor twenty-four, a resistor twenty-five, a resistor twenty-six, a resistor twenty-seven, a resistor twenty-eight, a resistor twenty-nine and a resistor thirty.
The four field effect transistors, the seventeen resistor, the five amplifier and the five capacitor form a precise input integrator.
Since the common mode input voltage is a dc constant of about 0V, fet four is resistively biased. The summing junction of the four gates of the fet is monitored by an amplifier six and compared to ground to provide dc stability. The voltage at the four gates of the fet with respect to the source is then output and provides a total dc offset equal to that of amplifier six. And the resistance twenty-nine, the resistance thirty and the capacitance seven form the T-shaped feedback circuit, under the condition that the frequency of the input signal is constant, the feedback resistance is far smaller than that of a common integrating circuit under the same condition, and useless bias voltage of the input bias current amplified by the feedback resistance is reduced. Thus, the circuit is a high-input-impedance, high-speed, precise integrator, and has very low DC drift between the received partial discharge signals.
Since the operational amplifier inevitably has the influence of offset voltage and bias current, if the operational amplifier is operated in an ideal model, the output of the integral output is saturated due to continuous charging of the integral capacitor by the input offset voltage. For this phenomenon, a commonly used solution is to connect a bleed-off resistor for discharging the integrating capacitor in parallel at two ends of the integrating capacitor, so as to ensure that the voltage of the integrating capacitor is not saturated.
The bleeder resistor has another function of clamping the DC gain of the input bias DC. Because the gain of the ideal integrator to the direct current voltage is infinite, the existence of the input bias current can certainly cause the final saturation of the output of the integrator, after the resistors are added, the gain of the circuit to the direct current can be controlled and reduced by adjusting the proportion of the two resistors.
The integration time constant is much larger than T (T is the time period of the incoming signal) and the integration is established. Therefore, the value of the bleeder resistance cannot be too small, and is generally 100K-1M.
In addition, an adjustable balance resistor is connected to the same-phase end of the integrating circuit, so that the influence of offset voltage and bias current on an integration result is reduced, and the reference value of the balance resistor is the ratio of the two bleeder resistors.
The integrator reset function is implemented by comparator seven and transistors five and six. When the precision integrator output voltage exceeds the threshold level of op-amp two (set by resistor twenty-three and resistor twenty-four), the output is driven high, thereby activating transistor five and transistor six. Transistor five discharges the second capacitor for feedback, effectively resetting the integrator, while transistor one adjusts the threshold of comparator four to near 0V, ensuring the integrator is fully reset. The output of the integrator is inverted to a forward voltage by an inverting (2 times) amplifier five and scaled to a 3V supply range to ensure analog-to-digital converter dynamic range with partial discharge.
The input end of the transistor reset integrator circuit is connected with one end of the resistor seventeen. One end of the resistor seventeen is connected with one end of the switch. The other end of the switch is connected with one end of a resistor eighteen, one end of a resistor twenty-nine, a grid electrode of a field effect tube four, one end of a capacitor five and a drain electrode of a transistor five. And the source of the transistor five is connected with the other end of the capacitor five, the other end of the resistor thirty, an input pin of the comparator seven, the output end of the amplifier five and one end of the resistor twenty-six. And the drain electrode of the field effect transistor IV is connected with an external positive voltage. And the emitter of the field effect transistor IV is connected with an input pin-of the amplifier V and one end of the resistor nineteen. The other end of the resistor eighteen is connected with one end of the capacitor six and an input pin-of the amplifier six.
The other end of the resistor twenty-nine is connected with one end of the resistor thirty and one end of the capacitor seven. The other end of the capacitor six and the output end of the amplifier six are connected with one end of the resistor twenty. The other end of the resistor twenty is connected with an input pin + of the amplifier five and one end of the connecting resistor twenty one. And the input pin + of the amplifier six is connected with one end of the resistor twenty two. The grid of the transistor five is connected with the output end of the comparator seven and the grid of the transistor six. And an input pin + of the seventh comparator is connected with one end of the twenty-third resistor, one end of the twenty-fourth resistor and one end of the twenty-fifth resistor. The other end of the resistor twenty-four is connected with an external negative voltage VEE. The other end of the resistor twenty-five is connected with the source electrode of the transistor six. The other end of the resistor twenty six is connected with one end of the resistor twenty seven and the input interface-of the amplifier eight. And the output end of the amplifier eight and the other end of the resistor twenty-seven are connected with the input end of the microcontroller. And the input interface + of the amplifier eight is connected with one end of the resistor twenty-eight. The drain of the transistor six, the other end of the resistor nineteen, the other end of the resistor twenty-one, the other end of the resistor twenty-two, the other end of the resistor twenty-three, the other end of the resistor twenty-eight and the other end of the capacitor seven are all grounded.
As a preferable technical measure: the system also comprises a microcontroller with an analog-to-digital conversion function and a communication module;
the microcontroller with the analog-digital conversion function is used for converting the sensor adjusting signal into a digital signal and transmitting the digital signal to a computer, and simultaneously recording the number of partial discharge times.
And the communication module is used for sending the signal to a remote computer.
And the computer is used for receiving and processing the partial discharge signals detected in real time.
As a preferable technical measure:
a high-speed precise signal processing method for monitoring high-frequency partial discharge,
the method comprises the following steps:
the method comprises the steps of firstly, detecting partial discharge signals of the equipment through an antenna, amplifying the partial discharge signals through a filtering and amplifying circuit, and filtering. And filtering a large amount of noise interference in the measurement process to avoid the distortion of the measurement signal. The processed signal is then sent to a zero bias detector.
And step two, coupling the power emitted by the output end of the amplifier through a zero bias detector, outputting a baseband output voltage which is in direct proportion to the radio frequency input power, and sending the baseband output voltage to the precise high-speed composite amplifier.
And step three, amplifying the input detection signal through a precise high-speed composite amplifier circuit, and outputting the detection signal to a comparator circuit and a transistor reset integrator circuit.
And step four, triggering the transistor reset integrator circuit to work by setting the threshold voltage of the comparator circuit. When the existence of partial discharge is detected, the comparator circuit outputs a signal to control the switch to be closed, and integration is started.
When there is no partial discharge, i.e. the received signal falls below the threshold set by the comparator circuit, the comparator circuit outputs a signal, controlling the switch to open, thereby avoiding integration when only noise is present.
And fifthly, integrating the signal through a transistor reset integrator circuit integrating circuit, outputting a microcontroller with an analog-to-digital conversion function, converting the signal into a digital signal and transmitting the digital signal to a computer, and detecting the local discharge signal.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention processes the partial discharge PD signal through the precise high-speed composite amplifier circuit, limits the partial discharge PD imbalance within a certain range, thereby improving the signal precision, and ensures that the sensitivity of the detector is not reduced due to the load because the input of the partial discharge PD presents high impedance. On the premise of ensuring large bandwidth and high precision, the requirements on high-speed direct conversion and high-speed signal processing are met.
2. The invention sets a comparator circuit between the precise high-speed composite amplifier circuit and the transistor reset integrator circuit, and enables the transistor reset integrator circuit through the comparator circuit, when the received signal is reduced below the threshold value of the comparator, the integrator circuit enters the holding mode, and the service life of the battery can be greatly prolonged, thereby obviously reducing the power supply current of the sensor node and increasing the working time of the sensor.
3. The transistor reset integrator circuit of the invention has high input impedance, high speed and precise integrator, and very low direct current DC drift between received partial discharge PD signals. And T feedback is added, so that the resistance value of the feedback resistor is reduced under the condition that the frequency of an input signal is constant, and useless bias voltage of the input bias current amplified by the feedback resistor is reduced.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a signal processing circuit according to the present invention;
FIG. 2 is a schematic diagram of a zero bias detector circuit according to the present invention;
FIG. 3 is a schematic diagram of a precision high-speed composite amplifier circuit according to the present invention;
FIG. 4 is a schematic diagram of a comparator circuit according to the present invention;
fig. 5 is a schematic diagram of a transistor reset integrator circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
As shown in fig. 1, a high-speed precision signal processing system for monitoring a high-frequency partial discharge,
the circuit comprises an antenna, a filtering amplification circuit, a zero bias detector, a precise high-speed composite amplifier circuit, a comparator circuit, a monostable trigger circuit and a transistor reset integrator circuit;
the filtering and amplifying circuit comprises a band-pass filter, a band-stop filter and a low noise amplifier LNA. The method is mainly used for filtering a large amount of noise interference in the measurement process so as to avoid the distortion of a measurement signal. The frequency range of the radiating partial discharge PD is typically between 50-800MHz, while most of the energy is below 300 MHz. Therefore, the measurement band is selected within this range. The band-pass filter is used for eliminating all interference and noise except for a 30-320MHz partial discharge PD measurement frequency band. The band reject filter is used to eliminate coherent interference in the 70-250MHz range (mainly from FM broadcasts, digital television and DAB transmissions). The low-noise amplifier is used for improving the signal-to-noise ratio of signal output, so that the high sensitivity of the sensor is ensured.
The zero bias detector is an energy sensing element and is mainly used for coupling the power emitted by the output end of the power amplifier and outputting the power to the back-end processor for monitoring and adjusting. Which can produce a baseband output voltage proportional to the RF input power. As shown in fig. 2, the circuit includes a resistor thirty RS, a diode one D1, a diode two D2, a resistor forty RL, and a capacitor ten CL. Input terminal V of zero-bias detector circuitLENThe resistor is connected with one end of the thirty RS resistor, the anode of the diode I D1 and the cathode of the diode II D2. The cathode of the diode one D1 is connected to one end of the resistor forty RL and one end of the capacitor decacl and the output terminal VDET of the circuit. The other end of the resistor thirty RS, the anode of the diode two D2, the other end of the resistor forty RL and the other end of the capacitor decacl are all grounded.
The precise high-speed composite amplifier circuit comprises an operational amplifier I U1, an operational amplifier II U2, a field-effect tube I Q1, a triode I Q2, a PNP triode II Q3, a capacitor I C1, a capacitor II C2, a resistor I R1, a resistor II R2, a resistor III R3, a resistor IV R4, a resistor V R5, a resistor VI R6, a resistor VII R7, a resistor VIII R8 and a resistor IX R9, as shown in FIG. 3.
The circuit is built around a 500 muA, 105MHz bipolar operational amplifier, U1, with closed loop voltage gain set by the resistance sizes of R3 and R4. The fet-Q1 is a JFET with a high impedance, low noise input stage. Q1 is biased to 500 μ A by reference current sources Q2 and Q3. This arrangement typically causes voltage and temperature drift, so by using an 18 μ A, 3 μ V lossThe tuned precision op-amp two U2 stabilizes, which provides dc compensation for the bias voltages of Q1 and U1. The U2 monitors the DC component of this voltage through low pass filters (R7 and C2) to ensure that the detected partial discharge PD signal is completely removed and compared to the input DC voltage through the same filters (R1 and C1). The output of U2 then adjusts the DC level of the DC of the U1 summing junction to V of Q1GSThe voltage is biased, resulting in an output DC offset error equal to the output DC offset error of U2 multiplied by the closed loop gain of U1. The voltage offset and temperature drift are also limited to U2. Therefore, partial discharge PD offset is limited below a certain range, and the circuit reaches the direct current precision.
The input end of the precision high-speed composite amplifier circuit is connected with the grid of the field effect transistor I Q1 and one end of the resistor I R1. The source of the fet one Q1 is connected to the input pin + of the op amp one U1 and the collector of the transistor one Q2. The base of the first transistor Q2 is connected with one end of the resistor eight R8 and the collector of the second transistor Q3. The emitter of the first transistor Q2 is connected with one end of a resistor nine R9 and the base of a second transistor Q3. The other end of the resistor nine R9 and the emitter of the transistor two Q3 are connected with the external negative voltage VEE. The drain of the first field effect transistor Q1 and the other end of the resistor eight R8 are connected with an external positive voltage VCC. The other end of the first resistor R1 is the input pin of the second operational amplifier U2 and one end of the first capacitor C1. The output end of the operational amplifier II U2 and the other end of the capacitor I C1 are connected with one end of the resistor II R2. The other end of the second resistor R2 is connected with one end of the third resistor R3, one end of the fourth resistor R4 and the input pin-of the first operational amplifier U1. The output end of the operational amplifier two U2, the other end of the resistor three R3 and one end of the resistor five R5 are connected with the input end NIAmp of the transistor reset integrator circuit and the amplifier circuit. The other end of the resistor five R5 is connected with one end of the resistor six R6 and one end of the resistor seven R7. The other end of the resistor seven R7 is connected with an input pin + of an operational amplifier two U2 and one end of a capacitor two C2. The other end of the capacitor two C2, the other end of the resistor six R6 and the other end of the resistor four R4 are grounded.
As shown in fig. 4, the comparator circuit includes an amplifier three U3, a comparator four U4, a field effect transistor one Q1, a capacitor three C3, a resistor ten R10, a resistor eleven R11, a resistor twelve R12, a resistor thirteen R13, a resistor fourteen R14, and a resistor fifteen R15. The comparator is a low power consumption high speed type comparator, the input signal is first amplified by a high speed in-phase amplifier tri U3, thereby allowing the comparator threshold to be set to a level significantly above the noise floor, ensuring a reduction in the possibility of false triggering. The integration circuit TRI is activated and the monostable flip-flop is triggered by setting the threshold voltage of the comparator section (by adjusting resistors tetradecr 14 and R15). Each time a partial discharge PD pulse is received, the monostable trigger circuit outputs a pulse to the microcontroller providing a digital count.
The comparator circuit input NI Amp is connected to the input pin + of the amplifier tri U3. The output pin of the amplifier three U3 is connected with one end of a resistor twelve R12 and a resistor eleven R11. The other end of the resistor eleven R11 is connected to the input pin-of the amplifier three U3 and one end of the resistor eleven R10. The other end of the resistor twelve R12 is connected with one end of a resistor thirteen R13 and an input pin + of a comparator four U4. The other end of the resistor thirteen R13 and an output pin of the comparator four U4 are connected with the input end of the monostable trigger circuit and the input end FRI S1 end of the transistor reset integrator circuit. And an input pin of the comparator four U4 is connected with one end of a resistor fourteen R14, a resistor fifteen R15 and a capacitor three C3. The other end of the resistor fourteen R14 is connected to an external positive voltage VCC. The other end of the resistor fifteen R15, the other end of the resistor ten R10 and the other end of the capacitor three C3 are both grounded.
The monostable trigger circuit is used for counting the partial discharge PD signals, and when the partial discharge PD pulse is received each time, the monostable trigger circuit outputs the pulse to the microcontroller to provide digital counting. The monostable is set to a duration of 5 mus to ensure that the microcontroller has sufficient time to acknowledge the signal.
The transistor reset integrator circuit (TRI) includes, as shown in fig. 5, a switch S1, an amplifier five U5, an amplifier six U6, an amplifier eight U8, a comparator seven U7, a field-effect transistor four Q4, a MOS transistor five Q5, a MOS transistor six Q6, a capacitor five C5, a capacitor six C6, a capacitor seven C7, a resistor seventeen R17, a resistor eighteen R18, a resistor nineteen R19, a resistor twenty R20, a resistor twenty-one R21, a resistor twenty-two R22, a resistor twenty-three R23, a resistor twenty-four R24, a resistor twenty-five R25, a resistor twenty-six R26, a resistor twenty-seven R27, a resistor twenty-eight R28, a resistor twenty-nine R29, and a resistor thirty R30.
The FETs four Q4, R17, U5 and C5 form a precision FET input integrator. Since the common mode input voltage is a direct current DC constant of about 0V, the fet quad Q4 is resistance biased. The summing junction of the gates of fet four Q4 is monitored by amplifier six U6 and compared to ground to provide DC stability. VGS for fet four Q4 is then output and provides a total DC offset equal to that of amplifier six U6. And the resistance twenty-nine R29, the resistance thirty R30 and the capacitor seven C7 form a T-shaped feedback circuit, and under the condition that the frequency of an input signal is constant, the feedback resistance is far smaller than that of a common integrating circuit under the same condition, so that useless bias voltage of the input bias current amplified by the feedback resistance is reduced. Thereby making the circuit a high input impedance, high speed, precision integrator,
the invention changes the signal feedback part of the existing bleeder resistor into T-type feedback.
The invention connects a discharge resistor twenty-nine R29 and a resistor thirty R30 for discharging the integrating capacitor C7 in parallel at two ends of the integrating capacitor, thus ensuring that the voltage of the integrating capacitor is not saturated.
The main significance of the T-type feedback is to apply the gain A of the direct currentDGain of alternating current AvAnd the relevance of the gain operation of the two is reduced. In the T-type feedback integration circuit, for the AC signal, the AC gain Av(2 pi f C7)/R29, note that the capacitive reactance X of the capacitor to ground C7cThe resistance is much smaller than that of the resistor thirty R30, that is, the alternating current signal forms a ground loop instead of forming a secondary feedback circuit through the resistor thirty R30. For a direct current signal, under the condition that the frequency of an input signal is constant, the feedback resistance of a direct current gain is far smaller than that of a common integrating circuit under the same condition, and the most direct performance of the difference in the circuit is that the useless bias voltage of the input bias current amplified by the feedback resistance is reduced.
Therefore, the T-shaped integrating circuit is compatible with the characteristic that the common integrating circuit is connected with the adjustable balance resistor and the bleeder resistor is added to reduce the influence of input offset voltage on the system function, and can greatly reduce useless bias of input bias current on signal output under the condition of inputting signals with the same frequency.
There is very low DC drift between the received partially discharged PD signals. The integrator reset function is implemented by comparator seven U7 and transistors Q5 and Q6. When the precision integrator output voltage exceeds the-1.5V threshold level of U2 (set by resistors twenty-three R23 and R24), the output is driven high, thereby activating Q5 and Q6. Q5 discharges feedback capacitor C2, effectively resetting the integrator, while Q2 adjusts the threshold of comparator four U4 to near 0V, ensuring that the integrator is fully reset.
The inverting (2 times) amplifier five U5 inverts the integrator output to a forward voltage and scales it to a 3V supply range to ensure analog to digital converter dynamic range with partial discharge PD.
The input end NIAmp of the integrator circuit is connected with one end of a resistor seventeen R17. One end of the resistor seventeen R17 is connected to one end of the switch S1. The other end of the switch S1 is connected with one end of a resistor eighteen R18, one end of a resistor twenty-nine R29, the gate of a field effect transistor four-Q4, one end of a capacitor five-C5 and the drain of a MOS transistor five-Q5. The source of the MOS transistor five Q5 is connected with the other end of the capacitor five C5, the other end of the resistor thirty R30, the input pin of the comparator seven U7, the output end of the amplifier five U5 and one end of the resistor twenty-six R26.
The drain of the fet four Q4 is connected to an external positive voltage VCC. The emitter of the four field effect transistor four Q4 is connected with the input pin-of the five U5 of the amplifier and one end of the nineteen R19. The other end of the resistor eighteen R18 is connected with one end of the capacitor six C6 and the input pin-of the amplifier six U6. The other end of the resistor twenty-nine R29 is connected with one end of a resistor thirty R30 and one end of a capacitor seven C7. The other end of the capacitor six C6 and the output end of the amplifier six U6 are connected with one end of a resistor twenty R20. The other end of the resistor twenty R20 and the input pin + of the amplifier five U5 are connected with one end of the R21. The input pin + of amplifier six U6 is connected to one end of resistor 22. The grid of the MOS transistor five Q5 is connected with the output end of the seven U7 of the comparator and the grid of the MOS transistor six Q6. An input pin + of the seven U7 comparator is connected with one end of a resistor twenty-three R23, one end of a resistor twenty-four R24 and one end of a resistor twenty-five R25. The other end of the resistor twenty-four R24 is connected with an external negative voltage VEE. The other end of the resistor twenty-five R25 is connected with the source electrode of the MOS transistor six Q6. The other end of the resistor twenty-six R26 is connected to one end of a resistor twenty-seven R27 and an input interface of the amplifier eight U8. The output of the amplifier eight U8 and the other end of the resistor twenty-seven R27 are connected to the input of the microcontroller. The + input interface of the amplifier eight U8 is connected with one end of a resistor twenty-eight R28. The drain of the MOS transistor six Q6, the other end of the resistor nineteen R19, the other end of the resistor twenty-one R21, the other end of the resistor twenty-two R22, the other end of the resistor twenty-three R23, the other end of the resistor twenty-eight R28 and the other end of the capacitor seven C7 are grounded.
The microcontroller ADC with the analog-to-digital conversion function is used for converting the sensor adjusting signal into a digital signal and transmitting the digital signal to the PC, and simultaneously recording the number of times of partial discharge PD.
And the communication module is used for sending the signal to a remote PC. And the PC is used for receiving and processing the partial discharge signals detected in real time.
A method for monitoring a high-speed precision signal processing system for high-frequency partial discharge applied to the present invention,
a high-speed precise signal processing method for monitoring high-frequency partial discharge specifically comprises the following steps:
the method comprises the steps of firstly, detecting partial discharge signals of the equipment through an antenna, amplifying the partial discharge signals through a filtering and amplifying circuit, and filtering. And filtering a large amount of noise interference in the measurement process to avoid the distortion of the measurement signal. The processed signal is then sent to a zero bias detector.
And step two, coupling the power emitted by the output end of the amplifier through a zero bias voltage detector, outputting a baseband output voltage which is in direct proportion to the radio frequency RF input power, and sending the baseband output voltage to the precise high-speed composite amplifier.
And thirdly, amplifying the input detection signal through a precise high-speed composite amplifier circuit, and outputting the detection signal to a high-speed comparator circuit and an integrating circuit TRI.
And step four, triggering the integrator circuit TRI to work by setting the threshold voltage of the comparator part. When the presence of the partial discharge PD is detected, the comparator output controls the switch S1 to close, and the TRI starts integrating. When there is no partial discharge PD, i.e. the received signal falls below the comparator threshold, the output of the comparator controls switch S1 to open, thereby avoiding integration when only noise is present.
And fifthly, integrating the signal through a TRI integrating circuit, outputting a microcontroller (ADC) with an analog-to-digital conversion function, converting the signal into a digital signal and transmitting the digital signal to a PC (personal computer), and detecting the local discharge signal.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A high-speed precise signal processing system for monitoring high-frequency partial discharge is characterized in that,
the circuit comprises an antenna, a filtering amplification circuit, a zero bias detector, a precise high-speed composite amplifier circuit, a comparator circuit, a monostable trigger circuit and a transistor reset integrator circuit;
the filtering and amplifying circuit is used for filtering a large amount of noise interference in the measuring process;
the zero bias detector is used for coupling the power emitted by the output end of the power amplifier and outputting the power to the back-end processor for monitoring and adjusting, and the zero bias detector can generate a baseband output voltage which is in direct proportion to the radio frequency input power;
the precise high-speed composite amplifier circuit is used for limiting partial discharge offset below a certain range so as to enable the circuit to reach the direct current precision, and comprises a T-shaped feedback circuit;
the comparator circuit is configured to set the comparator threshold to a level significantly above the noise floor;
the monostable trigger circuit is used for counting partial discharge signals;
the transistor resets the integrator circuit, so that the circuit is a high-input-impedance, high-speed and precise integrator;
the antenna detects a device partial discharge signal, and the partial discharge signal is amplified and filtered through the filtering and amplifying circuit;
then sending the processed signal to a zero bias detector;
the zero bias detector outputs corresponding baseband output voltage to the precise high-speed composite amplifier circuit;
the precise high-speed composite amplifier circuit amplifies an input detection signal and outputs the detection signal to the comparator circuit and the transistor reset integrating circuit;
the transistor reset integrator circuit is triggered to work by setting the threshold voltage of the comparator circuit, so that the monitoring of the high-frequency partial discharge is realized.
2. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 1,
the filtering amplification circuit comprises a band-pass filter, a band-stop filter and a low-noise amplifier;
the band-pass filter is used for eliminating all interference and noise except a 30-320MHz partial discharge measurement frequency band;
the band elimination filter is used for eliminating coherent interference in the range of 70-250 MHz;
the low noise amplifier is used for improving the signal-to-noise ratio of the signal output.
3. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 2,
the zero bias detector comprises a resistor thirty, a diode I, a diode II, a resistor forty and a capacitor ten;
the input end of the zero bias detector circuit is connected with one end of a resistor thirty, the anode of a diode I and the cathode of a diode II;
the negative electrode of the diode I is connected with one end of the resistor forty, one end of the capacitor ten and the output end of the circuit;
the other end of the resistor thirty, the anode of the diode two, the other end of the resistor forty and the other end of the capacitor ten are all grounded.
4. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 3,
the precise high-speed composite amplifier circuit comprises an operational amplifier I, an operational amplifier II, a field effect transistor I, a triode II, a capacitor I, a capacitor II, a resistor I, a resistor II, a resistor III, a resistor IV, a resistor V, a resistor VI, a resistor seven, a resistor eight and a resistor nine;
and the closed-loop voltage gain is set through the resistance values of the third resistor and the fourth resistor.
5. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 4,
the first field effect transistor is a junction field effect transistor, and the input stage of a transistor source electrode follower provides high impedance and low noise input; the first field effect transistor is biased to be 500 muA through a first reference current source and a second reference current source;
stabilizing by using a precision operational amplifier II with the offset of 18 muA and 3 muV, and providing direct current compensation for the bias voltage of the field effect transistor I and the operational amplifier I;
the operational amplifier monitors the dc component of this voltage through a low pass filter and compares it with the input dc voltage through the same filter;
and the output of the second operational amplifier adjusts the direct current level of the first summing point of the first operational amplifier into the bias voltage of the first field effect transistor.
6. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 5,
the input end of the precise high-speed composite amplifier circuit is connected with the grid of the first field effect transistor and one end of the first resistor;
the source electrode of the first field effect transistor is connected with the input pin + of the first operational amplifier and the collector electrode of the first triode;
the base electrode of the first triode is connected with one end of the resistor eight and the collector electrode of the second triode;
the emitter of the first triode is connected with one end of the resistor nine and the base of the second triode;
the other end of the resistor nine and the emitting electrode of the triode II are connected with external negative voltage;
the drain electrode of the field effect transistor I and the other end of the resistor eight are connected with an external positive voltage;
the other end of the resistor I is an input pin of an operational amplifier II and one end of the capacitor I;
the output end of the operational amplifier II and the other end of the capacitor I are connected with one end of the resistor II;
the other end of the second resistor is connected with one end of the third resistor, one end of the fourth resistor and an input pin of the first operational amplifier;
the output end of the operational amplifier II, the other end of the resistor III and one end of the resistor V are connected with the input ends of the transistor reset integrator circuit and the amplifier circuit;
the other end of the resistor five is connected with one end of the resistor six and one end of the resistor seven;
the other end of the resistor seven is an input pin + of the operational amplifier II and one end of the capacitor II;
the other end of the second capacitor, the other end of the sixth resistor and the other end of the fourth resistor are grounded.
7. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 1,
the comparator circuit comprises an amplifier III, a comparator IV, a capacitor III, a resistor eleven, a resistor twelve, a resistor thirteen, a resistor fourteen and a resistor fifteen;
amplifying the input signal by a high speed in-phase amplifier three, thereby allowing the comparator threshold to be set to a level significantly above the noise floor;
activating the transistor reset integrator circuit and triggering the monostable trigger circuit by setting a threshold voltage of the comparator section;
when receiving the partial discharge pulse each time, the monostable trigger circuit outputs the pulse to the microcontroller to provide digital counting;
the input end of the comparator circuit is connected with an input pin + of the amplifier III;
an output pin of the amplifier III is connected with one end of the resistor twelve and one end of the resistor eleven;
the other end of the resistor eleven is connected with an input pin-of the amplifier III and one end of the resistor eleven; the other end of the resistor twelve is connected with one end of a resistor thirteen and an input pin + of a comparator four; the other end of the resistor thirteen and an output pin of the comparator four are connected with the input end of the monostable trigger circuit and the input end of the transistor reset integrator circuit;
an input pin of the comparator IV is connected with the fourteen resistor, the fifteen resistor and one end of the capacitor III;
the other end of the resistor fourteen is connected with an external positive voltage; the other end of the resistor fifteen, the other end of the resistor ten and the other end of the capacitor three are grounded.
8. A high-speed precision signal processing system for monitoring high-frequency partial discharges according to claim 1,
the monostable trigger circuit is used for counting the partial discharge signals, and the monostable trigger circuit provides digital counting for the output pulse of the microcontroller every time when the partial discharge pulse is received;
monostable is set to a duration of 5 mus;
the transistor reset integrator circuit comprises a switch, an amplifier five, an amplifier six, an amplifier eight, a comparator seven, a field effect transistor four, a transistor five, a transistor six, a capacitor five, a capacitor six, a capacitor seven, a resistor seventeen, a resistor eighteen, a resistor nineteen, a resistor twenty-one, a resistor twenty-two, a resistor twenty-three, a resistor twenty-four, a resistor twenty-five, a resistor twenty-six, a resistor twenty-seven, a resistor twenty-eight, a resistor twenty-nine and a resistor thirty;
the field effect transistor four, the resistor seventeen, the amplifier five and the capacitor five form a precise FET input integrator;
monitoring the summing point of the four gates of the field effect transistor through an amplifier six and comparing the summing point with the ground to provide direct current stability; then, outputting the voltage of the four grid electrodes of the field effect transistor relative to the source electrode, and providing total direct current offset equal to the six amplifier;
the resistor twenty-nine, the resistor thirty and the capacitor seven form the T-shaped feedback circuit;
the reset function of the integrator is realized by a seventh comparator, a fifth transistor and a sixth transistor; when the output voltage of the precision integrator exceeds the threshold level of the second operational amplifier, the output is driven to be high level, so that a fifth transistor and a sixth transistor are activated; the fifth transistor discharges a second capacitor for feedback;
the input end of the transistor reset integrator circuit is connected with one end of the resistor seventeen; one end of the resistor seventeen is connected with one end of the switch; the other end of the switch is connected with one end of a resistor eighteen, one end of a resistor twenty-nine, a grid electrode of a field effect tube four, one end of a capacitor five and a drain electrode of a transistor five; the source of the transistor five is connected with the other end of the capacitor five, the other end of the resistor thirty, an input pin of the comparator seven, the output end of the amplifier five and one end of the resistor twenty-six; the drain electrode of the field effect tube IV is connected with an external positive voltage; an emitter of the field effect transistor IV is connected with an input pin-of the amplifier V and one end of the resistor nineteen; the other end of the resistor eighteen is connected with one end of the capacitor six and an input pin-of the amplifier six;
the other end of the resistor twenty-nine is connected with one end of the resistor thirty and one end of the capacitor seven; the other end of the capacitor six and the output end of the amplifier six are connected with one end of the resistor twenty; the other end of the resistor twenty is connected with an input pin + of the amplifier five and one end of the connecting resistor twenty one; the input pin + of the amplifier six is connected with one end of a resistor twenty-two; the grid electrode of the transistor five is connected with the output end of the comparator seven and the grid electrode of the transistor six; an input pin + of the comparator VII is connected with one end of a resistor twenty-three, one end of a resistor twenty-four and one end of a resistor twenty-five; the other end of the resistor twenty-four is connected with an external negative voltage; the other end of the resistor twenty five is connected with the source electrode of the transistor six; one end of a resistor twenty-seven at the other end of the resistor twenty-six and an input interface-of the amplifier eight; the output end of the amplifier eighth and the other end of the resistor twenty-seventh are connected with the input end of the microcontroller; the input interface + of the amplifier VIII is connected with one end of a resistor twenty-eight; the drain of the transistor six, the other end of the resistor nineteen, the other end of the resistor twenty-one, the other end of the resistor twenty-two, the other end of the resistor twenty-three, the other end of the resistor twenty-eight and the other end of the capacitor seven are all grounded.
9. A high-speed precision signal processing system for monitoring high-frequency partial discharge according to any one of claims 1 to 8, further comprising a microcontroller having analog-to-digital conversion function, a communication module;
the microcontroller with the analog-digital conversion function is used for converting the sensor adjusting signal into a digital signal and transmitting the digital signal to a computer, and simultaneously recording the number of partial discharge times;
the communication module is used for sending signals to a remote computer;
and the computer is used for receiving and processing the partial discharge signals detected in real time.
10. A high-speed precise signal processing method for monitoring high-frequency partial discharge is characterized in that,
the method comprises the following steps:
the method comprises the following steps that firstly, partial discharge signals of equipment are detected through an antenna, and are amplified and filtered through a filtering and amplifying circuit; filtering a large amount of noise interference in the measurement process; then sending the processed signal to a zero bias detector;
coupling the power emitted by the output end of the amplifier through a zero bias detector, outputting a baseband output voltage which is in direct proportion to the radio frequency input power, and sending the baseband output voltage to the precise high-speed composite amplifier;
amplifying the input detection signal through a precise high-speed composite amplifier circuit, and outputting the detection signal to a comparator circuit and a transistor reset integrator circuit;
step four, triggering the transistor reset integrator circuit to work by setting the threshold voltage of the comparator circuit; when the partial discharge is detected, the comparator circuit outputs a signal to control the switch to be closed, and integration is started; when partial discharge does not exist, namely the received signal is reduced to be lower than a threshold value set by the comparator circuit, the comparator circuit outputs a signal and controls the switch to be switched off, so that integration when only noise exists is avoided;
and fifthly, integrating the signal through a transistor reset integrator circuit integrating circuit, outputting a microcontroller with an analog-to-digital conversion function, converting the signal into a digital signal and transmitting the digital signal to a computer, and detecting the local discharge signal.
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