CN202309521U - Control circuit for single-inductance dual-output switching power supply - Google Patents
Control circuit for single-inductance dual-output switching power supply Download PDFInfo
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- CN202309521U CN202309521U CN2011203601878U CN201120360187U CN202309521U CN 202309521 U CN202309521 U CN 202309521U CN 2011203601878 U CN2011203601878 U CN 2011203601878U CN 201120360187 U CN201120360187 U CN 201120360187U CN 202309521 U CN202309521 U CN 202309521U
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Abstract
The utility model discloses a control circuit for a single-inductance dual-output switching power supply. The control circuit is provided with a primary loop control module, a secondary loop control module, a gating signal generating module, a driving module, a power level module and a voltage sampling module, wherein the outputs of the primary loop control module and the secondary loop control module are connected with the gating signal generating module; the output of the gating signal generating module is connected with the driving module; the output of the driving module is connected with the power level module; the output of the power level module is connected with the voltage sampling module, the primary loop control module and the secondary loop control module; the output of the voltage sampling module is connected with the primary loop control module and the secondary loop control module; the primary loop control module and the secondary loop control module comprise vibrators, oblique wave compensating circuits, current detection circuits, two error amplifiers and two pulse width modulators; the gating signal generating module comprises four phase inverters, seven two-input NAND gates, one two-input NOR gates, two buffers and two D trigger; the power level module comprises four switch tubes and inductors; and the voltage sampling module comprises six resistors and two capacitors.
Description
Technical field
The utility model relates to power supply changeover device, especially a kind of control circuit of single inductance dual output Switching Power Supply.
Background technology
Along with the development of electronic equipment and the increase of complexity, the inner unit module of complete machine gets more and more, and different module supply power voltage and power reguirements are different often.For example the mainboard of computer for distinct devices such as internal memory, hard disk, CPU and video cards, just need provide the supply power voltage of 3.3V, 5V, 12V respectively.For example current again smart mobile phone, except the RF module requires low noise and high power supply voltage rejection ratio, need be with outside the LDO power supply, all the other most of modules consider that from efficient majority all adopts the DC-DC Switching Power Supply, supply power voltage does not wait from 1.5V to 15V.This shows that the research of multi-output dc-DC circuit has great significance for current power management industrial circle.
The traditional design multiple-output electric power is to single channel output translator of the independent use of the output voltage of each grade, though can be good at satisfying the requirement and the simplicity of design of load like this, can cause the increase of Financial cost and electric supply installation volume.And because each DC-DC converter is independently, if their frequency of oscillation is variant, beat frequency just possibly takes place disturb, the frequency of occurrences is the voltage ripple of the difference of each frequency of oscillation on output voltage.PMU is current popular a solution.Through integrated a plurality of DC-DC converters in chip piece, thus the output of realization multiple voltage.No matter PMU on precision, volume still are conversion efficiency, all has good performance, but needs a plurality of inductance, and inductance is also the most difficult being integrated of area occupied maximum often, certainly will waste the PCB area like this and improve cost.
It is a kind of novel switched power supply architecture that single inductance dual output (SIDO) or single inductance are exported (SIMO) Switching Power Supply more, and each exports the branch road time-sharing work, utilizes single inductance to realize multichannel output, is suitable as very much the power supply of many-valued electrical voltage system.The time-sharing work of output branch road has brought two benefits: at first an inductance is shared on the road of each output, has significantly reduced the quantity of required inductance, significantly dwindles the final volume and weight of multi-output switch power source system.Secondly can realize accurately control separately to each output branch road.But also there is negative effect in time-sharing work: owing to share an inductance, have serious cross influence between the road of each output, the output current of certain output branch road changes the output current that can have influence on other output branch roads usually.The light ripple coefficient of respectively exporting branch road output that then increases of the problem of cross influence, heavy then destroy the stability of whole system, make the Switching Power Supply can't operate as normal.
The negative effect that single inductance multi-output switching power supply is brought for fear of cross influence; The Dongsheng Ma of Hong Kong University of Science and Thchnology is operated under DCM (discontinuous conduction mode) and PCCM (pseudo-continuous conduction mode) pattern SIMO Boost (boosting) Switching Power Supply; The Dead Time at two-way output junction place that utilizes adjacent work is as transition; Play the effect of isolation, effectively avoided the cross influence between the road of output.But DCM SIMO Switching Power Supply load capacity is less, and current ripples is big on the inductance simultaneously, causes output ripple bigger; Though PCCM SIMO Switching Power Supply inductance average current is bigger, load capacity is stronger, and PCCM utilizes the restraint of labour pattern to suppress to export the cross influence between the branch road, in case mode of operation can't guarantee that output still can exist between the branch road and influences each other.Therefore; DCM SIMO and PCCMSIMO Switching Power Supply all are the cross influences that has suppressed to a certain extent between the output branch road; In case and it is excessive or control out of control fundamentally to eliminate load variations; Be easy to make the mode of operation of Switching Power Supply to change, produce the cross influence between the output branch road.
Advantages such as to have load capacity strong owing to be operated in Switching Power Supply under the CCM pattern, and output voltage ripple is little, so the more and more scholars application of time-sharing multiplexing technology under the CCM Switching Power Supply that begin one's study.But the SIMO Switching Power Supply if certain road load changes, cause the inductive current on this road to depart from set point, and this variation will continue and have influence on the work of next branch road, cause cross influence under the CCM pattern.
The Zhang Lin of Southeast China University etc. has proposed a kind of minute period control method, and the SIMO Boost Switching Power Supply of continuous conduction mode is studied and designed at the control loop that independently charges and discharge under the switching sequence.End of term work week when this control method is exported on every road increases a calibration cycle, is used for proofreading and correct inductive current, to eliminate the cross influence between the output branch current.But this method is mainly by three shortcomings: at first be the efficient that pure resistive correction branch road has reduced Switching Power Supply; Next is the switch periods that calibration cycle has changed Switching Power Supply; The characteristic that is this control method has at last determined each road load of Switching Power Supply to equate or to be more or less the same.These several drawbacks limit proofread and correct the application of branch road control method in the SIMO Switching Power Supply.
Summary of the invention
The utility model is for overcoming the deficiency of prior art; On the basis of existing technology; A kind of control circuit of single inductance dual output Switching Power Supply has been proposed; Voltage and reference voltage through with each road output relatively produce the duty cycle signals of control major loop and secondary loop, realize the continuous conduction mode multichannel output of no cross influence down.
The technical scheme of the utility model is: a kind of control circuit of single inductance dual output Switching Power Supply, integrated two DC-DC converters in chip piece, the output that produces two kinds of voltages; The shared inductance of two output branch roads; Adopt master, the inferior loop control technology of time-sharing multiplex, the timesharing actuating switch is set, a clock cycle is divided into a plurality of unit at each output of exporting branch road; In each clock cycle division unit; Separately one tunnel output is controlled, it is characterized in that: be provided with major loop and time loop control module, gating signal generation module, driver module, power stage module and voltage sample module, major loop is connected the gating signal generation module with time loop control module output; The output of gating signal generation module connects driver module; Driver module output connects the power stage module, and the output of power stage module connects voltage sample module and major loop and time loop control module, and the output of voltage sample module connects major loop and time loop control module; Wherein:
Major loop comprises oscillator, oblique wave compensation circuit, current detection circuit, first error amplifier, second error amplifier, first pulse-width modulator and second pulse-width modulator with time loop control module; The oscillator clock signal is to slope compensation circuit; Be input to an input of first pulse-width modulator and second pulse-width modulator after the triangular signal stack of the sensed current signal of current detection circuit output and slope compensation circuit output respectively; Another input of first pulse-width modulator and second pulse-width modulator connects the output of first error amplifier and second error amplifier respectively; The normal phase input end of first error amplifier connects first reference voltage; The inverting input of first error amplifier connects first sampled voltage; The normal phase input end of second error amplifier connects second reference voltage, and the inverting input of second error amplifier connects second sampled voltage;
The gating signal generation module comprises first～the 44 inverter, first～the 77 two input nand gate, one two input NOR gate, first, second 2 buffers, first, second 2 d type flip flops; The output of first pulse-width modulator of major loop and time loop control module is connected the input of first inverter and an input of second liang of input nand gate respectively, and the output of second pulse-width modulator connects the input and the first d type flip flop data input pin of the input of second inverter, first liang of input nand gate respectively; The output of first inverter connects another input of first liang of input nand gate, the input of an input, the second d type flip flop input end of clock and the 3rd liang of input nand gate of two input NOR gates respectively, and the output of second inverter connects another input of another input of second liang of input nand gate, the 3rd liang of input nand gate and another input of two input NOR gates respectively; The output of first, second two input nand gate connects two inputs of the 4th liang of input nand gate respectively; The output of the 3rd liang of input nand gate connects the input and the 3rd inverter input of the 5th liang of input nand gate; Another input of the 5th liang of input nand gate connects the 4th inverter input and the second d type flip flop output respectively; The output of the 4th liang of input nand gate connects the input of first buffer; The output of first buffer connects the first d type flip flop input end of clock; The Enable Pin of first, second d type flip flop is with connecing outside enable signal, and the first d type flip flop output connects the second d type flip flop data input pin, and the output of the 3rd, the 4th inverter connects two inputs of the 6th liang of input nand gate respectively; Five, the output of the 6th liang of input nand gate connects two inputs of the 7th liang of input nand gate respectively, and the output of the 7th liang of input nand gate connects the input of second buffer;
Driver module comprises dead band control circuit and drive circuit; Be known circuit; Driver module is provided with 2 inputs; Is connected with output and the output of two input NOR gates of second buffer in the gating signal generation module respectively, four outputs of driver module are exported the first main switch gating signal, the second main switch gating signal, the inferior switch first branch road gating signal and the inferior switch second branch road gating signal respectively;
The power stage module comprises 4 switching tube MP1, MN1, MP2 and MP3 and inductance L; The grid of switching tube MP1 connects the first main switch gating signal of driver module output; The grid of switching tube MN1 connects the second main switch gating signal of driver module output; The grid of switching tube MP2 connects the inferior switch first branch road gating signal of driver module output, and the grid of switching tube MP2 connects the inferior switch second branch road gating signal of driver module output; The source electrode of switching tube MP1 connects the input of this single inductance dual output Switching Power Supply time-sharing multiplex control circuit; The input of current detection circuit in an end and the major loop that the drain electrode of the drain electrode of switching tube MP1 and switching tube MN1 is connected inductance L and time loop control module; The source ground of switching tube MN1; The other end of inductance L connects the source electrode of switching tube MP2 and switching tube MP3, and the drain electrode of switching tube MP2 and switching tube MP3 is respectively two outputs of first branch road and the second branch road output voltage;
The voltage sample module comprises 6 resistance R 1, R2, R3, R4, RL1 and RL2,2 capacitor C 1 and C2; One end of capacitor C 1, resistance R L1 and resistance R 1 all connects the drain electrode of switching tube MP2; One end of the other end of capacitor C 1, resistance R L1 and resistance R 2 all is connected to ground, and the other end of resistance R 1 and resistance R 2 all is connected to the inverting input of first error amplifier in major loop and time loop control module; One end of capacitor C 2, resistance R L2 and resistance R 3 all is connected to the drain electrode of switching tube MP3; One end of the other end of capacitor C 2, resistance R L2 and resistance R 4 all is connected to ground, and the other end of resistance R 3 and resistance R 4 all is connected to the inverting input of second error amplifier in major loop and time loop control module.
Advantage of the utility model and remarkable result
(1) in a clock cycle; Switching tube MP1, MN1, MP2 and MP3 are produced a gating signal respectively; In the time that MP1 opens; MP2 and MP3 are opened at times, in each part, separately one tunnel output is controlled, can reduce multichannel output cross influence so to a certain extent.
(2) adopt time-sharing multiplexing technology to realize single inductance dual output; Voltage and reference voltage through with each road output relatively produce the duty cycle signals of control major loop and secondary loop; Realize the continuous conduction mode multichannel output of no cross influence down; Control circuit is fairly simple, and this patent is based on switching mode simultaneously, and efficient is than higher.
Description of drawings
Fig. 1 is the utility model circuit block diagram;
Fig. 2 is the utility model circuit theory diagrams;
Fig. 3 is the circuit diagram of gating signal generation module in the utility model;
Fig. 4 is the sequential chart of gating signal generation module and driver module interior section pin in the utility model.
Embodiment
Referring to Fig. 1, Fig. 2; The utility model is provided with major loop and time loop control module, gating signal generation module, driver module, power stage module and voltage sample module; Major loop is connected the gating signal generation module with time loop control module output; The output of gating signal generation module connects driver module; Driver module output connects the power stage module, and the output of power stage module connects voltage sample module and major loop and time loop control module, and the output of voltage sample module connects major loop and time loop control module.Produce the pulse signal of two different duty through major loop and time loop control module; Pulse signal is input to two gating signals of generation in the gating signal generation module; Then two gating signals are input to the gating signal that driver module produces main switch (MP1, MN1) and time switch (MP2, MP3); The mode of using switch is kept required output voltage and load current to first branch road and the charging of second branch road, realizes the continuous conduction mode multichannel output of no cross influence down.Reach the stable voltage of output two-way and the purpose of regulating load size of current at last.
Major loop comprises oscillator, oblique wave compensation circuit, current detection circuit, error amplifier 1, error amplifier 2, pulse-width modulator 1 and second pulse-width modulator 2 with time loop control module; The oscillator clock signal is to slope compensation circuit; The input signal of current detection circuit is the electric current of inductance L; Be input to an input of pulse-width modulator 1 and pulse-width modulator 2 after the triangular signal stack of the sensed current signal of current detection circuit output and slope compensation circuit output respectively; Another input of pulse-width modulator 1 and pulse-width modulator 2 connects the comparison signal of the output of error amplifier 1 and error amplifier 2 respectively; Wherein, the normal phase input end of error amplifier 1 connects reference voltage Vref 1, and the inverting input of error amplifier 1 connects the sampled voltage V01 of voltage sample module; Reference voltage Vref 1 compares through error amplifier 1 with sampled voltage V01, and the output signal is to pulse-width modulator 1; The normal phase input end of second error amplifier connects reference voltage Vref 2; The inverting input of error amplifier 2 connects the sampled voltage V02 of voltage sample module; Reference voltage Vref 2 compares through error amplifier 2 with sampled voltage V02, and the output signal is to pulse-width modulator 2; The output signal B of the output signal A of pulse-width modulator 1 and pulse-width modulator 2 is input in the gating signal generation module.
As shown in Figure 3; The gating signal generation module comprises 4 inverter inv1, inv2, inv3 and inv4; 7 two input nand gate nand1, nand2, nand3, nand4, nand5, nand6 and nand7; One two input NOR gate nor1,2 buffer buffer1 and buffer2, d type flip flop 1 and d type flip flop 2.The output terminals A of pulse-width modulator 1 is connected to the input of inverter inv1 and the input of two input nand gate nand2; The output B of pulse-width modulator 2 is connected to input and the data input pin D of d type flip flop 1 of input, the two input nand gate nand1 of inverter inv2; The output of inverter inv1 is connected respectively to input and the input end of clock CLK of d type flip flop 2 of an input, the two input nand gate nand3 of another input, the two input NOR gate nor1 of two input nand gate nand1; The output of inverter inv2 is connected respectively to another input of two input nand gate nand2, another input of two input NOR gate nor1 and another input of two input nand gate nand3; The output of two input nand gate nand1 and nand2 is connected respectively to two inputs of two input nand gate nand4; The output of nand4 is connected to the input of buffer buffer1; The output of buffer1 is connected to the input end of clock CLK of d type flip flop 1; The output Q of d type flip flop 1 is connected to the data input pin D of d type flip flop 2; The input EN that enables of d type flip flop 1 and d type flip flop 2 is imported by outside enable signal; The Q of d type flip flop 2 end output signal R is input to the input of two input nand gate nand5 and the input of inverter inv4; The output of two input nand gate nand3 is connected to another input of two input nand gate nand5 and the input of reverser inv3; The output of inverter inv3 and inv4 is connected respectively to two inputs of two input nand gate nand6, and the output of two input nand gate nand5 and nand6 is connected respectively to two inputs of two input nand gate nand7, and the output of two input nand gate nand7 is connected to the input of buffer buffer2; Output signal (A+B) the ⊙ R of buffer buffer2 is input in the driver module, and the output signal A*B of two input NOR gate nor1 also is input in the driver module.
Like Fig. 2, driver module comprises dead band control circuit and drive circuit, is known circuit.Driver module is provided with 2 inputs; Is connected with output (A+B) ⊙ R and the output terminals A * B of two input NOR gate nor1 of buffer buffer2 in the gating signal generation module respectively, four outputs of driver module are exported the first main switch gating signal PD, the second main switch gating signal ND, the inferior switch first branch road gating signal D1 and the inferior switch second branch road gating signal D2 respectively.
The power stage module comprises 4 switching tube MP1, MN1, MP2 and MP3 and inductance L; The grid of switching tube MP1 connects the first main switch gating signal PD of driver module output; The grid of switching tube MN1 connects the second main switch gating signal ND of driver module output; The grid of switching tube MP2 connects the inferior switch first branch road gating signal D1 of driver module output, and the grid of switching tube MP2 connects the inferior switch second branch road gating signal D2 of driver module output; The source electrode of switching tube MP1 connects the input Vin of this single inductance dual output Switching Power Supply time-sharing multiplex control circuit; The input of current detection circuit in an end and the major loop that the drain electrode of the drain electrode of switching tube MP1 and switching tube MN1 is connected inductance L and time loop control module; The source ground of switching tube MN1; The other end of inductance L connects the source electrode of switching tube MP2 and switching tube MP3, and the drain electrode of switching tube MP2 and switching tube MP3 is respectively two the output VOUT1 and the VOUT2 of first branch road and the second branch road output voltage.
The voltage sample module comprises 6 resistance R 1, R2, R3, R4, RL1 and RL2,2 capacitor C 1 and C2; One end of capacitor C 1, resistance R L1 and resistance R 1 all connects the drain electrode (VOUT1) of switching tube MP2; One end of the other end of capacitor C 1, resistance R L1 and resistance R 2 all is connected to ground; The other end of resistance R 1 and resistance R 2 is exported V01, is connected to the inverting input of first error amplifier in major loop and time loop control module; One end of capacitor C 2, resistance R L2 and resistance R 3 all is connected to the drain electrode (VOUT2) of switching tube MP3; One end of the other end of capacitor C 2, resistance R L2 and resistance R 4 all is connected to ground; The other end of resistance R 3 and resistance R 4 is exported V02, is connected to the inverting input of second error amplifier in major loop and time loop control module.
The operation principle of the utility model circuit is following:
The voltage sample module is supposed VOUT1＜VOUT2 through sampling resistor R1, R2, R3, R4 sample the output voltage VO UT1 and the VOUT2 of first branch road and second branch road, and the output voltage of voltage sample module is V01 and V02; Wherein V01 is the sampled voltage of first branch road, and V02 is the sampled voltage of second branch road, and the inverting input and the reference voltage V ref1 that V01 are input to error amplifier 1 compare; When the V01 value bigger than the Vref1 value, error amplifier 1 output low level, when the V01 value littler than the Vref1 value; Error amplifier 1 output high level, in like manner, the inverting input and the reference voltage V ref2 that V02 are input to error amplifier 2 compare; When the V02 value bigger than the Vref2 value; Error amplifier 2 output low levels, when the V02 value littler than the Vref2 value, error amplifier 2 output high level.Major loop time loop control module is typical peak electricity flow pattern control loop; The purpose of slope compensation is in order to prevent subharmonic oscillation; The output signal of error amplifier 1 and error amplifier 2 is input to respectively in pulse-width modulator 1 and the pulse-width modulator 2; Simultaneously current detecting to the signal of inductive current also be input in pulses width modulator 1 and the pulse-width modulator 2 with slope compensation signal; Pulse-width modulator 1 output has the a-signal of certain duty ratio, and pulse-width modulator 2 is also exported the B signal that certain duty ratio is arranged, and a-signal and B signal are input to the gating signal generation module.
The gating signal generation module carries out two input signals to export after some logical operations through some logical circuits, and Fig. 4 is the sequential chart of gating signal generation module and driver module interior section pin.T1, T2, T3, T4, T5, T6 are six clock cycle, TI=T2=T3=T4=T5=T6=T, and wherein at T1, the T2 d1 that the duty ratio of a-signal all is in the cycle, the duty ratio of B signal all is d2; Duty ratio at T3, T4 a-signal in the cycle all is d3, and the duty ratio of B signal all is d4; Duty ratio at T4, T5 a-signal in the cycle all is d5, and the duty ratio of B signal all is d6.When each clock cycle began, main switch PMOS power tube gating signal was that low level is opened major loop power tube MP1.
In cycle, the duty ratio d1 of a-signal is greater than the duty ratio d2 of B signal, through exporting A, B (A and B) signal behind the gating signal generation module at T1, T2; The AB signal is input to driver module; Main switch PMOS power tube gating signal PD, main switch power NMOS gating signal ND and A, B signal are similar to identical, and main switch PMOS power tube gating signal PD control MP1 pipe is opened in the time at 0～d1 of a clock cycle, and inductive current is risen; Close the inductance afterflow in time at d1～T; Main switch power NMOS gating signal ND control MN1 pipe is closed in the time at 0～d1, opens in the time at d1～T.Through output (A+B) ⊙ R behind the gating signal generation module (A or B again with R with or) signal, (A+B) ⊙ R signal is input to driver module, inferior switch second branch road gating signal D2 of output is approximate identical with (A+B) ⊙ R signal.The inferior switch first branch road gating signal D1 is with (A+B) ⊙ R signal is approximate opposite; Inferior switch second branch road gating signal D2 control MP3 pipe is opened in the time at 0～d2 of a clock cycle; Inductive current charges to second branch road; The second branch road output voltage is risen, close in the time at d2～T, the second branch road output voltage descends; Inferior switch first branch road gating signal D1 control MP2 pipe is closed in the time at 0～d2; Open in the time at d2～T, inductive current charges to first branch road in the time at d2～d1, and the first branch road output voltage is risen; D1～T in the time MP1 close, the first branch road output voltage is descended.So; In cycle, the first branch road output load current is at first second branch road to be charged when the clock cycle begins greater than the second branch road load current at T1, T2; Then first branch road is charged, keep first branch road and second branch road required output voltage and load current.
At T3, T4 in the cycle; Circuit load changes and causes first via output load current less than the second branch road load current, and the duty ratio d3 of a-signal is less than the duty ratio d4 of B signal, through exporting A, B signal behind the gating signal generation module; A, B signal are input to driver module; Main switch PMOS power tube gating signal PD, main switch power NMOS gating signal ND and the A of output, B signal are similar to identical, and main switch PMOS power tube gating signal PD control MP1 pipe is opened in the time at 0～d4 of a clock cycle, and inductive current is risen; Close the inductance afterflow in time at d4～T; Main switch power NMOS gating signal ND control MN1 pipe is closed in the time at 0～d4, opens in the time at d4～T.Through output (A+B) ⊙ R signal behind the gating signal generation module, (A+B) ⊙ R signal is input to driver module, and the inferior switch second branch road gating signal D2 of output is approximate identical with (A+B) ⊙ R signal; The inferior switch first branch road gating signal D1 is with (A+B) ⊙ R signal is approximate opposite; But because the delay of d type flip flop, saltus step takes place in judgement symbol for having prolonged a clock cycle after, the following switch first branch road gating signal D1, the inferior switch second branch road gating signal D2 identical in the sequential in T3 cycle and T1, T2 cycle; At T4 in the cycle; Inferior switch first branch road gating signal D1 control MP2 pipe is opened in the time at 0～d3 of a clock cycle, and inductive current charges to first branch road, and the first branch road output voltage is risen; Close in the time at d3～T, the first branch road output voltage descends; Inferior switch second branch road gating signal D2 control MP3 pipe is closed in the time at 0～d3; Open in the time at d3～T, second branch road is charged, the second branch road output voltage is risen at d3～d4 time internal inductance electric current; D4～T in the time MP1 close, the second branch road output voltage is descended.So in the cycle, the first branch road output load current is greater than the second branch road load current at T3; Be at first second branch road to be charged when the clock cycle begins, then first branch road charged, at T4 in the cycle; The second branch road output load current is greater than the first branch road load current; Be at first first branch road to be charged when the clock cycle begins, then second branch road charged, keep first branch road and second branch road required output voltage and load current.
In like manner, in the cycle, circuit load changes and causes first via output load current greater than the second branch road load current at T5, T6; The duty ratio d5 of a-signal is greater than the duty ratio d6 of B signal; Through exporting A, B signal behind the gating signal generation module, A, B signal are input to driver module, and the main switch PMOS power tube gating signal PD of output, main switch power NMOS gating signal ND and A, B signal are similar to identical; Main switch PMOS power tube gating signal PD control MP1 pipe is opened in the time at 0～d5 of a clock cycle; Inductive current is risen, close the inductance afterflow at d5～T in the time; Main switch power NMOS gating signal ND control MN1 pipe is closed in the time at 0～d5, opens in the time at d5～T.Through output (A+B) ⊙ R signal behind the gating signal generation module, (A+B) ⊙ R signal is input to driver module, and the inferior switch second branch road gating signal D2 of output is approximate identical with (A+B) ⊙ R signal; The inferior switch first branch road gating signal signal D1 is with (A+B) ⊙ R signal is approximate opposite; But because the delay of d type flip flop, saltus step takes place in judgement symbol for having prolonged a clock cycle after, the following switch first branch road gating signal D1, the inferior switch second branch road gating signal D2 identical in the sequential in T5 cycle with the T4 cycle; At T6 in the cycle; Inferior switch second branch road gating signal D2 control MP3 pipe is opened in the time at 0～d6 of a clock cycle, and inductive current charges to second branch road, and the second branch road output voltage is risen; Close in the time at d6～T, the second branch road output voltage descends; Inferior switch first branch road gating signal D1 control MP2 pipe is closed in the time at 0～d6; Open in the time at d6～T, first branch road is charged, the first branch road output voltage is risen at d6～d5 time internal inductance electric current; D5～T in the time MP2 close, the first branch road output voltage is descended.So in the cycle, the second branch road output load current is greater than the first branch road load current at T5; Be at first first branch road to be charged when the clock cycle begins, then second branch road charged, at T6 in the cycle; The first branch road output load current is greater than the second branch road load current; Be at first second branch road to be charged when the clock cycle begins, then first branch road charged, keep first branch road and second branch road required output voltage and load current.
Claims (1)
1. the control circuit of a single inductance dual output Switching Power Supply; Integrated two DC-DC converters in chip piece, the output that produces two kinds of voltages, the shared inductance of two output branch roads; Output at each output branch road is provided with the timesharing actuating switch; A clock cycle is divided into a plurality of unit, in each clock cycle division unit, separately one tunnel output is controlled; It is characterized in that: be provided with major loop and time loop control module, gating signal generation module, driver module, power stage module and voltage sample module; Major loop is connected the gating signal generation module with time loop control module output, and the output of gating signal generation module connects driver module, and driver module output connects the power stage module; The output of power stage module connects voltage sample module and major loop and time loop control module, and the output of voltage sample module connects major loop and time loop control module; Wherein:
Major loop comprises oscillator, oblique wave compensation circuit, current detection circuit, first error amplifier, second error amplifier, first pulse-width modulator and second pulse-width modulator with time loop control module; The oscillator clock signal is to slope compensation circuit; Be input to an input of first pulse-width modulator and second pulse-width modulator after the triangular signal stack of the sensed current signal of current detection circuit output and slope compensation circuit output respectively; Another input of first pulse-width modulator and second pulse-width modulator connects the output of first error amplifier and second error amplifier respectively; The normal phase input end of first error amplifier connects first reference voltage; The inverting input of first error amplifier connects first sampled voltage; The normal phase input end of second error amplifier connects second reference voltage, and the inverting input of second error amplifier connects second sampled voltage;
The gating signal generation module comprises first～the 44 inverter, first～the 77 two input nand gate, one two input NOR gate, first, second 2 buffers, first, second 2 d type flip flops; The output of first pulse-width modulator of major loop and time loop control module is connected the input of first inverter and an input of second liang of input nand gate respectively, and the output of second pulse-width modulator connects the input and the first d type flip flop data input pin of the input of second inverter, first liang of input nand gate respectively; The output of first inverter connects another input of first liang of input nand gate, an input, the input end of clock of second d type flip flop and an input of the 3rd liang of input nand gate of two input NOR gates respectively, and the output of second inverter connects another input of another input of second liang of input nand gate, the 3rd liang of input nand gate and another input of two input NOR gates respectively; The output of first, second two input nand gate connects two inputs of the 4th liang of input nand gate respectively; The output of the 3rd liang of input nand gate connects the input and the 3rd inverter input of the 5th liang of input nand gate; Another input of the 5th liang of input nand gate connects the 4th inverter input and the second d type flip flop output respectively; The output of the 4th liang of input nand gate connects the input of first buffer; The output of first buffer connects the first d type flip flop input end of clock; The Enable Pin of first, second d type flip flop is with connecing outside enable signal, and the first d type flip flop output connects the second d type flip flop data input pin, and the output of the 3rd, the 4th inverter connects two inputs of the 6th liang of input nand gate respectively; Five, the output of the 6th liang of input nand gate connects two inputs of the 7th liang of input nand gate respectively, and the output of the 7th liang of input nand gate connects the input of second buffer;
Driver module comprises dead band control circuit and drive circuit; Be known circuit; Driver module is provided with 2 inputs; Is connected with output and the output of two input NOR gates of second buffer in the gating signal generation module respectively, four outputs of driver module are exported the first main switch gating signal, the second main switch gating signal, the inferior switch first branch road gating signal and the inferior switch second branch road gating signal respectively;
The power stage module comprises 4 switching tube MP1, MN1, MP2 and MP3 and inductance L; The grid of switching tube MP1 connects the first main switch gating signal of driver module output; The grid of switching tube MN1 connects the second main switch gating signal of driver module output; The grid of switching tube MP2 connects the inferior switch first branch road gating signal of driver module output, and the grid of switching tube MP2 connects the inferior switch second branch road gating signal of driver module output; The source electrode of switching tube MP1 connects the input of this single inductance dual output Switching Power Supply time-sharing multiplex control circuit; The input of current detection circuit in an end and the major loop that the drain electrode of the drain electrode of switching tube MP1 and switching tube MN1 is connected inductance L and time loop control module; The source ground of switching tube MN1; The other end of inductance L connects the source electrode of switching tube MP2 and switching tube MP3, and the drain electrode of switching tube MP2 and switching tube MP3 is respectively two outputs of first branch road and the second branch road output voltage;
The voltage sample module comprises 6 resistance R 1, R2, R3, R4, RL1 and RL2,2 capacitor C 1 and C2; One end of capacitor C 1, resistance R L1 and resistance R 1 all connects the drain electrode of switching tube MP2; One end of the other end of capacitor C 1, resistance R L1 and resistance R 2 all is connected to ground, and the other end of resistance R 1 and resistance R 2 all is connected to the inverting input of first error amplifier in major loop and time loop control module; One end of capacitor C 2, resistance R L2 and resistance R 3 all is connected to the drain electrode of switching tube MP3; One end of the other end of capacitor C 2, resistance R L2 and resistance R 4 all is connected to ground, and the other end of resistance R 3 and resistance R 4 all is connected to the inverting input of second error amplifier in major loop and time loop control module.
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| CN2011203601878U CN202309521U (en) | 2011-09-23 | 2011-09-23 | Control circuit for single-inductance dual-output switching power supply |
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| CN2011203601878U CN202309521U (en) | 2011-09-23 | 2011-09-23 | Control circuit for single-inductance dual-output switching power supply |
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