CN102577060B - Controlling power loss in a switched-capacitor power converter - Google Patents
Controlling power loss in a switched-capacitor power converter Download PDFInfo
- Publication number
- CN102577060B CN102577060B CN201080034630.0A CN201080034630A CN102577060B CN 102577060 B CN102577060 B CN 102577060B CN 201080034630 A CN201080034630 A CN 201080034630A CN 102577060 B CN102577060 B CN 102577060B
- Authority
- CN
- China
- Prior art keywords
- scb
- gate drive
- drive signal
- voltage
- loss
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 105
- 230000009466 transformation Effects 0.000 claims description 18
- 230000001965 increasing effect Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000005259 measurement Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- IYLGZMTXKJYONK-ACLXAEORSA-N (12s,15r)-15-hydroxy-11,16-dioxo-15,20-dihydrosenecionan-12-yl acetate Chemical compound O1C(=O)[C@](CC)(O)C[C@@H](C)[C@](C)(OC(C)=O)C(=O)OCC2=CCN3[C@H]2[C@H]1CC3 IYLGZMTXKJYONK-ACLXAEORSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Inverter Devices (AREA)
Abstract
The invention relate to a system that implements a switched-capacitor power converter which is configured to actively control power loss while converting an input voltage to an output voltage. This system includes one or more switched-capacitor blocks (SCBs), wherein each SCB includes a first capacitor and a set of switching devices configured to couple a constant-potential terminal and a time-varying-potential terminal of the first capacitor between the input voltage, the output voltage and a reference voltage. The system also includes a clocking circuit which produces gate drive signals for switching transistors in the one or more SCBs. The system additionally includes a controller configured to actively control the gate drive signals from the clocking circuit to substantially minimize the power loss for the switched-capacitor power converter.
Description
Technical field
The disclosed embodiments relate in general to for DC power transfer being become to the technology of different voltage.More specifically, the disclosed embodiments relate to the technology in the power loss of switched capacitor power inverter for ACTIVE CONTROL.
Background technology
High efficiency switched capacitor power inverter comprises being driven to generate by resonant clock control circuit and is almost input voltage V
lOthe output voltage V of twice
hIone or more switching capacity modules (switched-capacitor block, SCB).In order to work under the highest possible efficiency, switched capacitor power inverter need to make the minimum power losses during voltage transformation is processed.These power losss both comprised (1) conduction loss in SCB, also comprised (2) switching loss in SCB and resonance clock control circuit.
Fortunately, these losses can by change by resonant clock control circuit, be generated, for driving the gate drive voltage V of the switching transistor of SCB
gcontrol.More specifically, increase V
gincrease switching loss, and reduce conduction loss simultaneously.On the contrary, reduce V
gincrease conduction loss and reduce switching loss.Therefore, can adjust V
gto realize the balance between switching loss and conduction loss, this balance makes the minimum power losses in power inverter.
Regrettably, the relative value of conduction loss and switching loss is because the working point of power inverter is along with time variation changes.More specifically, the relative value of conduction loss and switching loss can be along with root mean square output current I
rMSwith input voltage V
lOvariation and change.As a result, make the V of minimum power losses
gvalue is because the changing operate-point of power inverter changes.
Therefore, needed is for to have considered that the mode of variation of the working point of power inverter is controlled at the method and apparatus of the power loss of switched capacitor power inverter.
Summary of the invention
The disclosed embodiments relate to for realizing the system of the switched capacitor power inverter that is configured to ACTIVE CONTROL power loss when converting input voltage to output voltage.This system comprises one or more switching capacity modules (SCB), wherein each SCB comprise the first capacitor and be configured to by the constant potential terminal of the first capacitor and time power transformation position terminal be coupled to one group of switching device between input voltage, output voltage and reference voltage.This system also comprises and produces the clock control circuit at the transistorized gate drive signal of these one or more SCB for switch.This system also comprises in addition and is configured to ACTIVE CONTROL from the gate drive signal of clock control circuit so that the power loss of switched capacitor power inverter minimized controller substantially.
In certain embodiments, controller is configured to carry out ACTIVE CONTROL gate drive signal by controlling the voltage of gate drive signal, the voltage that wherein increases gate drive signal reduces the conduction loss in these one or more SCB, but be increased in the switching loss in clock control circuit, and on the contrary, the voltage that reduces gate drive signal reduces the switching loss in clock control circuit, but is increased in the conduction loss in these one or more SCB.
In certain embodiments, controller is configured to carry out ACTIVE CONTROL gate drive signal by controlling the frequency of gate drive signal, the frequency that wherein increases gate drive signal reduces the conduction loss in these one or more SCB, but be increased in the switching loss in these one or more SCB and clock control circuit, and on the contrary, the frequency that reduces gate drive signal reduces the switching loss in these one or more SCB and clock control circuit, but is increased in the conduction loss in these one or more SCB.
In certain embodiments, the frequency of controlling gate drive signal comprises that one or more tapped inductor (tapped inductor) of using in clock control circuit control the frequency of clock control circuit.
In certain embodiments, controller is configured to carry out ACTIVE CONTROL gate drive signal by controlling the quantity of the SCB that gate drive signal driving, the quantity that wherein increases SCB reduces the conduction loss in SCB, but be increased in the switching loss in these one or more SCB and clock control circuit, and on the contrary, the quantity that reduces SCB reduces the switching loss in these one or more SCB and clock control circuit, but is increased in the conduction loss in SCB.
In certain embodiments, the voltage of controlling gate drive signal comprises: determine that wherein this function is used predetermined parameter as the voltage of the gate drive signal of the input voltage of switched capacitor power inverter and the function of output current; And then with determined voltage, produce gate drive signal.
In certain embodiments, the voltage of control gate drive signal comprises: measure the power loss in switched capacitor power inverter; And by measured power loss as for for control gate drive signal voltage control system input so that the power loss of switched capacitor power inverter substantially minimize.
In certain embodiments, control system usage ratio-integration-differential (PID) control technology is controlled the voltage of gate drive signal.
In certain embodiments, system is controlled the voltage of gate drive signal in the following manner: first carry out power measurement to produce one or more measurement components of power loss.Then, system operation parameter model is to carry out one or more parametrization components of rated output loss based on one or more measured inputs and one or more parameter.Then system estimates the power loss in switched capacitor power inverter based on measuring component and parametrization component.Finally, system by estimated power loss as for for control gate drive signal voltage control system input so that the power loss of switched capacitor power inverter substantially minimize.
In certain embodiments, clock control circuit is the resonant oscillator circuit that comprises at least one inductance and at least one electric capacity.
Accompanying drawing explanation
Fig. 1 shows voltage changer according to an embodiment of the invention.
Fig. 2 A shows the structure of switching capacity module (SCB) according to an embodiment of the invention.
Fig. 2 B shows according to an embodiment of the invention the structure of SCB that can cascade.
Fig. 3 has provided the flow chart that voltage transformation is processed has according to an embodiment of the invention been shown.
Fig. 4 shows resonant clock control circuit according to an embodiment of the invention.
Fig. 5 shows according to an embodiment of the invention the circuit for the power loss of control switch condenser type power inverter.
Fig. 6 has provided and has illustrated according to an embodiment of the invention as gate drive voltage V
gthe chart of power loss of function.
Fig. 7 shows according to an embodiment of the invention the alternative circuit for the power loss of control switch condenser type power inverter.
Fig. 8 A provided according to the power inverter optimization of the disclosed embodiments and that do not optimize as root mean square output current I
rMSthe chart of power loss of function.
Fig. 8 B provided according to the power inverter optimization of the disclosed embodiments and that do not optimize as root mean square output current I
rMSthe chart of power conversion efficiency of function.
Embodiment
Provide following description so that those skilled in the art can realize and use the disclosed embodiments, and following description is to provide under the situation of specific application and requirement thereof.The various modifications of the disclosed embodiments will be apparent for a person skilled in the art, and in the situation that do not depart from the spirit and scope of the disclosed embodiments, can be applied to other embodiment and application in this defined General Principle.Thereby the disclosed embodiments are not limited to shown embodiment, but should meet the widest scope consistent with principle disclosed herein and feature.
Data structure described in these specific descriptions and code are stored on computer-readable recording medium conventionally, and this computer-readable recording medium can be to store the code that used by computer system and/or random devices or the medium of data.Computer-readable recording medium comprises, but be not limited to, volatile memory, nonvolatile memory, magnetic and light storage device are (for example, disk drive, tape, CD (compact disk), DVD (digital versatile disc or digital video disc)), maybe can store now known or later by other media of the code of developing and/or data.
Method described in these specific descriptions and processing can be implemented as code and/or the data that can be stored in above-described computer-readable recording medium.When computer system reads and while carrying out the code be stored on computer-readable recording medium and/or data, computer system is carried out and is implemented as data structure and code and is stored in method and the processing in computer-readable recording medium.In addition described method, and processing can be contained in hardware module.For example, hardware module can include, but not limited to application-specific integrated circuit (ASIC) (ASIC) chip, field programmable gate array (FPGA) and present other programmable logic devices known or that later develop.When hardware module is activated, hardware module is carried out method and the processing being contained in hardware module.
voltage changer
Fig. 1 shows efficient switch condenser type power inverter 100 according to an embodiment of the invention.In shown embodiment, the oscillator supply power voltage V that resonant clock control circuit 106 receives from oscillator voltage source
oSC, and the two phase place clock of four kinds of forms of generation, i.e. C
l, C
h, P
land P
h.These two phase place clock signals are controlled at driver output V in contrary clock phase
hItwo switching capacity modules (SCB) 102 and 104.At forward duration of work, SCB 102 and 104 is by lower output voltage V
lO100 convert higher output voltage V to
hI112, its progressive 2V that equals
lO-V
b.More specifically, in the first clock phase, SCB 102 provides and equals 2V
lO-IR
o1-VB (R wherein
o1be the effective resistance of SCB 102, I is output current) output voltage V
hI112, and SCB 104 and V
hI112 decoupling zeros.Similarly, in second clock phase place, SCB 104 provides and equals 2V
lO-IR
o2-VB (R wherein
o2be the effective resistance of SCB 104, I is output current) output voltage V
hI112, and SCB 102 and V
hI112 decoupling zeros.Note, a purposes of output capacitor 108 be for two SCB not during driver output by energy supply to output.
switching capacity module
Fig. 2 shows the structure of switching capacity module (SCB) 102 according to an embodiment of the invention.SCB 102 comprises capacitor 210 (also referred to as " pump capacitor (pump capacitor) ") and one group of switching device 202,204,206 and 208.In shown embodiment, switching device 202,204,206 and 208 is power metal-oxide-semiconductor field effect transistor (MOSFET).Note, Fig. 2 also shows each the direction of body diode (body diode) in MOSFET 202,204,206 and 208.
Fig. 2 also shows the connection of MOSFET 202,204,206 and 208 in addition.More specifically, MOSFET 202 is at clock input C
hcontrol under the constant potential terminal of capacitor 210 is couple to V
lO110; MOSFET 206 is at clock input C
lcontrol under the time power transformation position terminal of capacitor 210 is couple to reference voltage V
b113; MOSFET 204 is at clock input P
hcontrol under the constant potential terminal of capacitor 210 is couple to V
hI112; And MOSFET 208 is at clock input P
lcontrol under the time power transformation position terminal of capacitor 210 is couple to V
lO110.
In the first clock phase, constant potential terminal and the V of capacitor 210
lO110 couple, and time power transformation position terminal and the V of capacitor 210
b113 couple.This makes to be charged to V at the voltage at capacitor 210 two ends
lO-V
b.In second clock phase place, constant potential terminal and the V of capacitor 210
hI112 couple, and time power transformation position terminal and the V of capacitor 210
lO110 couple.By this way, the voltage at capacitor 210 two ends is superimposed on V
lOon 110 to produce output voltage V
hI112=2V
lO-V
b-I
or
o, I wherein
oit is output current.
In an embodiment of the present invention, capacitor 210 use parallel capacitor groups realize, and wherein each capacitor is the ceramic mould capacitor of 100 μ F.Capacitor group time power transformation position terminal at V
bwith V
lObetween conversion.Therefore, for the time power transformation position terminal of capacitor group is couple to V
lOthe grid of MOSFET 208 drive and must there is at least V
g+ V
lOvoltage transitions, V wherein
gto make R
ds(on) reach the required gate drive voltage of its minimum conducting resistance.Similarly, the constant potential terminal of capacitor 210 is at V
lOwith V
hIbetween conversion.Therefore the MOSFET 202 and 204, being connected with the constant potential terminal of capacitor group there is no need to be converted to V
lOunder.These gate drive signals can be setovered with at V by input voltage
lO+ V
b+ V
gwith V
hI+ V
b+ V
gbetween conversion.Note, drive the required energy of each grid and (V
lO+ V
g)
2be directly proportional.
Fig. 2 B shows and how just can in the situation that having added two switching devices and three capacitors, obtain higher than V
hIvoltage.More specifically, Fig. 2 B comprises the whole circuit shown in Fig. 2, and comprises in addition two transistors 222 and 224 and three capacitors 230,232 and 234.Note, the lower end of capacitor 230 attaches to node A 201.During system works, node A 201 is from V
lObe transformed into V
hI.Transistor 222 at node A 201 in V
lOtime conducting, this impels capacitor 230 to be charged to V
hI-V
lO.Then, transistor 224 reaches V at node A 201
hItime conducting.This impels output voltage V
xH236 reach V
hI+ V
lO.By this way, the circuit shown in Fig. 2 B is serving as voltage tripler effectively.For a person skilled in the art, quadrupler etc. can be constructed to the conversion of Fig. 2 B by again applying from Fig. 2 A.Note, because the circuit shown in Fig. 2 B is reversible, so can be by V
bon arbitrfary point regard input as, and remaining naming a person for a particular job is output.For example,, if V
lOinput and V
bearth potential, V
hIoutput and the V of 2 times are provided
xH236 provide the output of 3 times.As selection, if V
hIinput, V
loutput and the V of 1/2 times are provided
xHthe output of 3/2 times is provided.Similarly, if V
xHinput, V
hIoutput and the V of 2/3 times are provided
lOthe output of 1/3 times is provided.
voltage transformation is processed
Fig. 3 has provided the flow chart that voltage transformation is processed has according to an embodiment of the invention been shown.This flow chart has been contained the work of the system shown in Fig. 1.During operation, system receives input voltage V
lO(step 302).Then, system generates and has the clock signal (step 304) of nonoverlapping clock phase (comprising the first phase place and the second phase place) substantially with resonant clock control circuit.
These clock signals are applied in first group of switching device (in SCB 102), make the constant potential terminal of the first capacitor in the first phase place and input voltage couples and time power transformation position terminal and the reference voltage of the first capacitor couple, and in the second phase place the first capacitor constant potential terminal and output voltage couples and time power transformation position terminal and the input voltage of the first capacitor couple (step 306).
These clock signals are also applied in second group of switching device (in SCB 104), make the constant potential terminal of the second capacitor in the first phase place and output voltage couples and time power transformation position terminal and the input voltage of the second capacitor couple, and in the second phase place the second capacitor terminal and input voltage couples and the second capacitor time power transformation position terminal with couple (step 308).Finally, output capacitor 108 is used to carry out many functions, comprises output voltage is carried out to filtering (step 310).
resonant clock control circuit
Fig. 4 shows resonant clock control circuit according to an embodiment of the invention.With reference to the lower portion of Fig. 4, the resonant clock control circuit on basis comprises two complementary circuit parts that produce contrary clock phase.The first circuit part comprises inductor 402 and FET 410, and produces output
the second complementary circuit partly comprises inductor 404 and FET 408, and produces output
wherein
with
contrary clock phase is provided.Note, FET 408 and 410 is cross-coupled, thereby obtains FET 408 and 410 control inputs separately from the output of complementary circuit part.Be also noted that, the grid capacitance of each FET concentrates in together with the output load capacitance of contrary clock phase.(be also noted that, load capacitance is grid capacitance in SCB.)
At the duration of work of this resonant clock control circuit, energy is vibration back and forth between inductive circuit element and capacitance circuit element, there is no significant conduction loss or switching loss.More specifically, in the first circuit part, energy is in inductor 402 and output
load capacitance between vibrate, wherein this load capacitance concentrates in together with the grid capacitance of relative FET 408.Similarly, in second circuit part, energy is in inductor 404 and output
load capacitance between vibrate, wherein this load capacitance concentrates in together with the grid capacitance of relative FET 410.
The upper portion of Fig. 4 shows and generates output
with
corresponding circuit.In output
with
on voltage follow output
with
on voltage, but be biased with the voltage level in higher.This is by using two bootstrap capacitor C
b1414 and C
b2the FET 422 and 420 of 412 and two cross-coupled realizes, and the FET 422 of these two cross-coupled and 420 is clamped on V by the clock output of rising in a phase place
lO, then in another phase place with V
lOpositively biased in-migration follow clock output.In output
with
on the voltage level of rising can be used to drive the MOSFET 202 and 204 shown in Fig. 2.As discussed above mentioned, these MOSFET need to be at V
lOwith V
hI+ V
gbetween conversion gate drive signal.As shown in the upper portion of Fig. 4, dotted line frame A can be again stacking to provide Fig. 2 B " superelevation " (XH) to export.
Note, Zener diode (Zener diode) 418 and 416 (for example, this Zener diode 418 and 416 can be the Zener diode of 19V) is respectively coupled to output
with
and between ground, with protective circuit during powering up, avoid the impact of large transient voltage.Be also noted that, transistor 420 and 422 can be to have and V
lOthe anode coupling and with
or
the common diode of the negative electrode coupling replaces.
minimum power consumption
Some embodiment of the present invention passes through for given output current I
rMSwith input voltage V
lOoptimize gate drive voltage V
gthereby, be minimized in the power loss in switched capacitor power inverter.As mentioned above, the power loss in switched capacitor power inverter both comprised that (1), by the conduction loss of switching capacity module (SCB), also comprised (2) switching loss in SCB and resonance clock control circuit.
Conduction loss by SCB is by I
rMS 2r
oprovide, wherein I
rMSroot mean square output current, R
oit is the output resistance of SCB.Note output resistance R
obe subject to the conducting resistance R of switch FET
ds (on)institute arranges, wherein gate drive voltage V
glarger, conducting resistance is just less.
In switched capacitor power inverter, there are two main switching loss sources.Within first source comes across resonant clock control circuit, come from the grid circulation that makes SCB FET.Loss in Fig. 2 A in the SCB FET grid in left side and square V of grid voltage
g 2be directly proportional.On the contrary, the loss in the SCB on right side FET grid and (V
g-V
lO)
2be directly proportional, because the source of the FET in left side and input voltage V
lOrelevant.Other switching losses are caused by the charging and discharging of drain electrode-source capacitance of FET.These other switching loss and V
lO 2be directly proportional.
Note, by increasing grid, drive V
g, switching loss increases, however conduction loss reduces.Therefore, for given output current I
rMSwith input voltage V
lOexistence drives the optimum grid of minimum power losses.
Be used for controlling V
ggood mode be by controlling the input voltage of resonant oscillator.For example, Fig. 5 has provided the chart of the parameter optimization device circuit that Buck converter 502 is shown, and wherein this Buck converter 502 is according to being used for arranging V by Buck converter 502
oSCthe set point V calculating of 509 level
sP503 control oscillator voltage V
oSC509.Parameter optimization device 504 is according to I
rMS506 and V
lO511 measured value calculates V
sP503 optimal value is so that the minimum power losses in switched capacitor power inverter 506, as shown in Figure 5.Note amplitude V
gwith V
oSC509 are directly proportional.
Buck converter or linear regulator can be according to switching capacity module V
hI513 output generates controllable V
oSC.Compare with linear regulator, using the advantage of Buck converter is higher efficiency.The shortcoming of Buck converter comprises that parts are more, circuit board space is more and cost is higher.And Buck converter need to isolate to prevent uncontrolled vibration between the switchable inductor of main body (buck) and the inductor of resonant clock control circuit.A kind of is that large output capacitance is positioned over by the small resistor R shown in Fig. 5 for isolating the method for Buck converter
iSOLin the output of 515 main bodys that separate with the input of resonant oscillator.
A kind of technology for minimum power consumption is from being characterized by V for specific circuit design by total losses
oSC, I
rMSand V
lOfunction start.Power loss can be measured in laboratory with the difference of power stage by measuring power input.By these data, for the I for given
rMSand V
lOmake the V of minimum power
oSCor V
sPcan be determined also parameterized.For example, simple parametrization is provided by following formula:
(V
SP)
opt＝K
A+K
BV
LO+K
CI
RMS (1)
Wherein K item is by the determined parameter of the loss recording.
Then parameter optimization device 504 in Fig. 5 passes through periodically (for example, each second) and measures V
lOand I
rMS, use formula (1) to calculate optimum set point (V
sP)
optcarry out work, wherein V
sPvia Buck controller, controlling V
oSC.Therefore work as V
lOand I
rMSduring change, V
oSCbe updated periodically so that the loss of switched capacitor power inverter minimizes.
The another kind of technology for minimum power consumption is initiatively to measure power loss, P
loss=P
iN-P
oUT, and realization makes this loss minimized servo (servo).For example, this minimize servo can be by V within a period
sPbe set to a certain nominal value, and within the next period, by V
sPbe set to V
sP+ Δ, wherein Δ is microvariations.For example, Fig. 6 shows the power loss measured value that comprises the multipair measured value being separated by Δ.More specifically, Fig. 6 shows as oscillator set point V
sPthe power loss P of function
loss, wherein show the multipair measured value being separated by Δ.Note, power loss the poor ε of power loss measured value while being zero in minimum value.
For every a pair of measured value, the variation ε of power loss can measure as follows
ε＝P
Loss(V
SP)-P
Loss(V
SP+Δ) (2)
The variation ε of power loss is the error signal in the servo input of feed-in PID, and wherein the set point V of nominal is adjusted on this PID servo period ground
sPε is controlled to zero.When ε is zero, switched capacitor power inverter will be worked under its minimum power loss.The proportional-integral-differential of standard (PID) is servo can be used to adjustable ratio, integration and differentiation gain minimum power consumption.
Fig. 7 shows for realizing PID servo to pass through control for generating V
oSCthe set point of Buck controller make the schematic diagram of optimizer of the minimum power losses of switched capacitor power inverter.Compare with the parameter optimization device in Fig. 5, the servo advantage of PID of the minimum power in Fig. 7 is not need to characterize in advance and parametrization switched capacitor power inverter.Equally, to circuit to the variation of circuit (circuit-to-circuit) or insensitive to parameterized model.The shortcoming of this technology is to measure input RMS electric current I according to the needs of circuit
rMSdetermine input power, this may affect power loss significantly.
As compromise, can use the solution of mixing, wherein some feature (for example, the switching loss of the drain-source electric capacity of SCBFET) is parameterized, and other features (for example, the loss of conduction loss and resonant oscillator) are directly measured.Except not being directly measures power loss, but come outside estimating power loss according to measured value and parameterized combination, the implementation of this mixing is servo by the PID as minimum power, work.
other mechanism for minimum power consumption
Replace by controlling V
oSCcarry out minimum power consumption, other implementations can be for example by changing the effective quantity n of parallel SCB or passing through to adjust oscillator frequency f
oSCcarry out minimum power.In order to improve the conduction loss in SCB, many SCB can be connected in parallel, this makes conduction loss reduce with factor n, and switching loss is increased with factor n.Therefore, another kind of possible implementation is that the SCB that only enables optimal number by the load current for given carrys out minimum power.
Equally, adjust f
oSCthe effective mode of another kind of minimum power consumption, because the switching loss of oscillator is with f
oSCincrease and increase and output resistance with f
oSCreduce and reduce.Note oscillator frequency f
oSCwith
proportional, so by initiatively changing the inductance L of oscillator or the grid capacitance C of SCB FET, can make minimum power losses.
Can V will be adjusted
oSC, f
oSCor the technology of the quantity of SCB is all used so that total minimum power losses jointly.
the benefit of optimizing
Use the benefit of optimizer from Fig. 8 A and 8B, to find out.More specifically, Fig. 8 A shows power loss and Fig. 8 B shows efficiency with respect to the figure of output current, and existing utilize (solid line) of optimizer also has (dotted line) that does not utilize optimizer.Note, do not utilize optimizer (fixing V
oSC) performance at the electric current place being indicated by arrow, be optimum.
Dotted line in Fig. 8 A and 8B is indicated respectively for specific I
rMSand V
lOthe use of optimizing is V fixedly
oSCthe power loss in switched capacitor power inverter and efficiency.On the contrary, solid line shows the power loss that obtains by using optimizer and the improvement of efficiency.
Under very high output current, optimizer increases V
oSCthereby, reduce R
oand conduction loss, this has surpassed the switching loss increasing.On the contrary, under very light load, optimizer reduces V
oSC, impel R
oincrease with conduction loss, but reduced significantly switching loss.
Description about embodiment just provides for the purpose of illustration and description above.That they do not wish limit or this description is defined in to disclosed form.Therefore, it should be apparent to those skilled in the art that many changes and variation.In addition, above disclosure is not intended to limit this description.The scope of this description is limited by appending claims.
Claims (13)
1. the method in the power loss of switched capacitor power inverter for ACTIVE CONTROL, described method comprises:
Make the work of described switched capacitor power inverter, wherein said switched capacitor power inverter comprises one or more switching capacity modules (SCB) and produces the clock control circuit for the transistorized gate drive signal of one or more SCB described in switch;
When the work of described switched capacitor power inverter, ACTIVE CONTROL from the described gate drive signal of described clock control circuit so that the power loss of described switched capacitor power inverter substantially minimize;
Wherein described in ACTIVE CONTROL, gate drive signal comprises the voltage of controlling described gate drive signal; And
The voltage of wherein controlling described gate drive signal comprises: the power loss of measuring described switched capacitor power inverter, by measured power loss with opposing for controlling the input of control system of the voltage of described gate drive signal, so that the power loss of described switched capacitor power inverter minimizes substantially.
2. method according to claim 1,
Wherein said one or more SCB comprises a plurality of SCB; And
Wherein described in ACTIVE CONTROL, gate drive signal also comprises: the quantity that controls the SCB that described gate drive signal driving, the quantity that wherein increases described SCB reduces the conduction loss in described SCB, but be increased in the switching loss in described one or more SCB and described clock control circuit, and the quantity that wherein reduces described SCB reduces the switching loss in described one or more SCB and described clock control circuit, but be increased in the conduction loss in described SCB.
3. method according to claim 1, the voltage of wherein controlling described gate drive signal comprises:
The voltage of described gate drive signal is defined as to the input voltage of described switched capacitor power inverter and the function of output current, and wherein said function is used predetermined parameter; And
With determined voltage, produce described gate drive signal.
4. method according to claim 1, the voltage of wherein controlling described gate drive signal comprises:
Carry out power measurement to produce one or more measurement components of described power loss;
Operation parameter model is to carry out one or more parametrization components of rated output loss based on one or more measurement components and one or more parameter;
Based on described measurement component and described parametrization component, estimate the power loss of described switched capacitor power inverter; And
By estimated power loss with opposing for controlling the input of control system of the voltage of described gate drive signal, so that the power loss of described switched capacitor power inverter minimizes substantially.
5. method according to claim 1, wherein said clock control circuit is the resonant oscillator circuit that comprises at least one inductance and at least one electric capacity.
6. the method in the power loss of switched capacitor power inverter for ACTIVE CONTROL, described method comprises:
Make the work of described switched capacitor power inverter, wherein said switched capacitor power inverter comprises one or more switching capacity modules (SCB) and produces the clock control circuit for the transistorized gate drive signal of one or more SCB described in switch;
When the work of described switched capacitor power inverter, ACTIVE CONTROL from the described gate drive signal of described clock control circuit so that the power loss of described switched capacitor power inverter substantially minimize;
Wherein described in ACTIVE CONTROL, gate drive signal comprises that one or more tapped inductor of using in described clock control circuit are to control the frequency of described clock control circuit.
7. be configured to ACTIVE CONTROL and relate to a switched capacitor power inverter that input voltage is converted to the power loss of output voltage, comprising:
One or more switching capacity modules (SCB), wherein each SCB comprise the first capacitor and be configured to by the constant potential terminal of described the first capacitor and time power transformation position terminal be coupled to one group of switching device between described input voltage, described output voltage and reference voltage;
Produce the clock control circuit at the transistorized gate drive signal of described one or more SCB for switch; And
Be configured to ACTIVE CONTROL from the described gate drive signal of described clock control circuit so that the power loss of described switched capacitor power inverter minimized controller substantially;
Wherein said controller is configured to carry out gate drive signal described in ACTIVE CONTROL by controlling the voltage of described gate drive signal;
Wherein when controlling the voltage of described gate drive signal, described controller is configured to: the power loss of measuring described switched capacitor power inverter, by measured power loss with opposing for controlling the input of control system of the voltage of described gate drive signal, so that the power loss of described switched capacitor power inverter minimizes substantially.
8. switched capacitor power inverter according to claim 7,
Wherein said one or more SCB comprises a plurality of SCB; And
Wherein said controller is also configured to carry out gate drive signal described in ACTIVE CONTROL by controlling the quantity of the SCB that described gate drive signal driving, the quantity that wherein increases described SCB reduces the conduction loss in described SCB, but be increased in the switching loss in described one or more SCB and described clock control circuit, and the quantity that wherein reduces described SCB reduces the switching loss in described one or more SCB and described clock control circuit, but be increased in the conduction loss in described SCB.
9. switched capacitor power inverter according to claim 7, wherein, when controlling the voltage of described gate drive signal, described controller is configured to:
The voltage of described gate drive signal is defined as to the input voltage of described switched capacitor power inverter and the function of output current, and wherein said function is used predetermined parameter; And
With determined voltage, produce described gate drive signal.
10. switched capacitor power inverter according to claim 7, wherein, when controlling the voltage of described gate drive signal, described controller is configured to:
Carry out power measurement to produce one or more measurement components of described power loss;
Operation parameter model is to calculate one or more parametrization components of described power loss based on one or more measurement components and one or more parameter;
Based on described measurement component and described parametrization component, estimate the power loss of described switched capacitor power inverter; And
By estimated power loss with opposing for controlling the input of control system of the voltage of described gate drive signal, so that the power loss of described switched capacitor power inverter minimizes substantially.
11. switched capacitor power inverters according to claim 7, wherein said clock control circuit is the resonant oscillator circuit that comprises at least one inductance and at least one electric capacity.
12. 1 kinds are configured to ACTIVE CONTROL and relate to the switched capacitor power inverter that input voltage is converted to the power loss of output voltage, comprising:
One or more switching capacity modules (SCB), wherein each SCB comprise the first capacitor and be configured to by the constant potential terminal of described the first capacitor and time power transformation position terminal be coupled to one group of switching device between described input voltage, described output voltage and reference voltage;
Produce the clock control circuit at the transistorized gate drive signal of described one or more SCB for switch; And
Be configured to ACTIVE CONTROL from the described gate drive signal of described clock control circuit so that the power loss of described switched capacitor power inverter minimized controller substantially;
Wherein said controller is configured to gate drive signal described in ACTIVE CONTROL and comprises: described controller is configured to use the one or more tapped inductor in described clock control circuit to control the frequency of described clock control circuit, the frequency that wherein increases described gate drive signal reduces the conduction loss in described one or more SCB, but be increased in the switching loss in described one or more SCB and described clock control circuit, and the frequency that wherein reduces described gate drive signal reduces the switching loss in described one or more SCB and described clock control circuit, but be increased in the conduction loss in described one or more SCB.
13. 1 kinds of power supplys, comprising:
The battery of input voltage is provided;
The output of output voltage is provided; And
Be configured to the switched capacitor power inverter of ACTIVE CONTROL power loss when converting described input voltage to described output voltage, wherein said switched capacitor power inverter comprises,
One or more switching capacity modules (SCB), wherein each SCB comprise the first capacitor and be configured to by the constant potential terminal of described the first capacitor and time power transformation position terminal be coupled to one group of switching device between described input voltage, described output voltage and reference voltage;
Produce the clock control circuit at the transistorized gate drive signal of described one or more SCB for switch; And
Be configured to ACTIVE CONTROL from the described gate drive signal of described clock control circuit so that the described power loss of described switched capacitor power inverter minimized controller substantially;
Wherein said controller is configured to carry out gate drive signal described in ACTIVE CONTROL by controlling the voltage of described gate drive signal; And
Wherein when controlling the voltage of described gate drive signal, described controller is configured to: the power loss of measuring described switched capacitor power inverter, by measured power loss with opposing for controlling the input of control system of the voltage of described gate drive signal, so that the power loss of described switched capacitor power inverter minimizes substantially.
Applications Claiming Priority (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/535,974 | 2009-08-05 | ||
| US12/535,974 US8320141B2 (en) | 2009-08-05 | 2009-08-05 | High-efficiency, switched-capacitor power conversion using a resonant clocking circuit to produce gate drive signals for switching capacitors |
| US12/540,578 | 2009-08-13 | ||
| US12/540,578 US7982548B2 (en) | 2009-08-05 | 2009-08-13 | Resonant oscillator with oscillation-startup circuitry |
| US12/629,370 | 2009-12-02 | ||
| US12/629,370 US8085103B2 (en) | 2009-08-05 | 2009-12-02 | Resonant oscillator circuit with reduced startup transients |
| US12/783,728 | 2010-05-20 | ||
| US12/783,728 US8541999B2 (en) | 2009-08-05 | 2010-05-20 | Controlling power loss in a switched-capacitor power converter |
| PCT/US2010/042339 WO2011016974A2 (en) | 2009-08-05 | 2010-07-16 | Controlling power loss in a switched-capacitor power converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102577060A CN102577060A (en) | 2012-07-11 |
| CN102577060B true CN102577060B (en) | 2014-11-19 |
Family
ID=43534337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201080034630.0A Expired - Fee Related CN102577060B (en) | 2009-08-05 | 2010-07-16 | Controlling power loss in a switched-capacitor power converter |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8541999B2 (en) |
| EP (1) | EP2462683B1 (en) |
| CN (1) | CN102577060B (en) |
| WO (1) | WO2011016974A2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10128749B2 (en) | 2014-05-12 | 2018-11-13 | Texas Instruments Incorporated | Method and circuitry for sensing and controlling a current |
| JP6403999B2 (en) * | 2014-06-05 | 2018-10-10 | 株式会社細川洋行 | Retort packaging laminate and container |
| WO2016011380A1 (en) * | 2014-07-17 | 2016-01-21 | The Trustees Of Dartmouth College | System and method for two-phase interleaved dc-dc converters |
| GB2547449A (en) * | 2016-02-18 | 2017-08-23 | General Electric Technology Gmbh | Converter apparatus |
| GB2547448A (en) * | 2016-02-18 | 2017-08-23 | General Electric Technology Gmbh | Converter apparatus |
| CN108075622B (en) * | 2017-12-26 | 2020-05-15 | 北京金风科创风电设备有限公司 | Power converter gate drive control method, device, controller and converter |
| US10790740B2 (en) | 2018-05-02 | 2020-09-29 | Analog Devices Global Unlimited Company | Techniques for switch capacitor regulator power savings |
| CN110729888B (en) * | 2019-10-29 | 2020-11-06 | 上海南芯半导体科技有限公司 | Hybrid power converter with high voltage conversion ratio |
| CN111786583A (en) * | 2020-06-08 | 2020-10-16 | 湖南大学 | High frequency resonance inverter |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4807104A (en) * | 1988-04-15 | 1989-02-21 | Motorola, Inc. | Voltage multiplying and inverting charge pump |
| US5684682A (en) * | 1995-07-19 | 1997-11-04 | Motorola, Inc. | Method and apparatus for selectable DC to DC conversion |
| US5760637A (en) * | 1995-12-11 | 1998-06-02 | Sipex Corporation | Programmable charge pump |
| US6188590B1 (en) * | 1996-12-18 | 2001-02-13 | Macronix International Co., Ltd. | Regulator system for charge pump circuits |
| DE10149938A1 (en) * | 2001-10-10 | 2003-05-08 | Infineon Technologies Ag | Circuit arrangement for contactless chip card has charge pump circuit with amplifier stages with pump nodes, charge reservoir circuit with coupling nodes coupled pump nodes |
| US6650163B1 (en) * | 2002-08-08 | 2003-11-18 | International Business Machines Corporation | Clock generator for integrated circuit |
| CN101095276A (en) * | 2005-01-14 | 2007-12-26 | 半导体元件工业有限责任公司 | DC-to-dc converter and method therefor |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5051881A (en) | 1990-07-05 | 1991-09-24 | Motorola, Inc. | Voltage multiplier |
| US5396195A (en) | 1993-12-13 | 1995-03-07 | At&T Corp. | Low-power-dissipation CMOS oscillator circuits |
| US5559478A (en) | 1995-07-17 | 1996-09-24 | University Of Southern California | Highly efficient, complementary, resonant pulse generation |
| US5677077A (en) | 1996-02-22 | 1997-10-14 | Compaq Computer Corporation | Sensor circuit for providing maximum and minimum cell voltages of a battery |
| US6249192B1 (en) | 1998-01-26 | 2001-06-19 | Agere Systems Guardian Corp. | Clock injection system |
| US6064277A (en) | 1998-02-27 | 2000-05-16 | Analog Devices, Inc. | Automatic biasing scheme for reducing oscillator phase noise |
| US6169673B1 (en) | 1999-01-27 | 2001-01-02 | National Semiconductor Corporation | Switched capacitor circuit having voltage management and method |
| IL138844A0 (en) * | 2000-08-14 | 2001-10-31 | K S Waves Ltd | High efficiency power supply |
| US6385065B1 (en) | 2000-09-14 | 2002-05-07 | Fairchild Semiconductor Corporation | Low voltage charge pump employing distributed charge boosting |
| US6559689B1 (en) * | 2000-10-02 | 2003-05-06 | Allegro Microsystems, Inc. | Circuit providing a control voltage to a switch and including a capacitor |
| JP4040467B2 (en) | 2001-02-01 | 2008-01-30 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Programmable charge pump device |
| JP2002238243A (en) | 2001-02-07 | 2002-08-23 | Seiko Epson Corp | Dc/dc converter and power supply for liquid crystal |
| GB2374952A (en) | 2001-04-24 | 2002-10-30 | Ubinetics Ltd | Resonant clock distribution circuit |
| JP3691421B2 (en) | 2001-09-27 | 2005-09-07 | シャープ株式会社 | Switched capacitor type stabilized power supply circuit |
| US6559492B1 (en) * | 2001-11-07 | 2003-05-06 | Intel Corporation | On-die switching power converter with stepped switch drivers and method |
| JP2003218634A (en) | 2002-01-28 | 2003-07-31 | Hitachi Ltd | Oscillation circuit |
| JP2003235244A (en) * | 2002-02-06 | 2003-08-22 | Seiko Instruments Inc | Rash current limiting/noise reducing circuit for pfm control charge pump |
| JP2004064937A (en) | 2002-07-31 | 2004-02-26 | Nec Corp | Charge pump-type boosting circuit |
| JP4763606B2 (en) | 2003-09-08 | 2011-08-31 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | High frequency control of semiconductor switches |
| TWI277853B (en) | 2005-03-03 | 2007-04-01 | Novatek Microelectronics Corp | Method for efficiency enhancement in a charge pump circuit and a charge pump control selector |
| US7430133B1 (en) * | 2005-05-31 | 2008-09-30 | National Semiconductor Corporation | Apparatus and method for switch connected as a diode in a charge pump |
| US8040175B2 (en) | 2007-10-24 | 2011-10-18 | Cypress Semiconductor Corporation | Supply regulated charge pump system |
| JP5214221B2 (en) * | 2007-11-13 | 2013-06-19 | ローム株式会社 | Charge pump circuit and control circuit and control method thereof |
| WO2009136369A2 (en) | 2008-05-09 | 2009-11-12 | Nxp B.V. | Frequency controlled capacitive power converter |
| TWI358884B (en) * | 2008-06-13 | 2012-02-21 | Green Solution Tech Co Ltd | Dc/dc converter circuit and charge pump controller |
| US8085103B2 (en) | 2009-08-05 | 2011-12-27 | Apple Inc. | Resonant oscillator circuit with reduced startup transients |
-
2010
- 2010-05-20 US US12/783,728 patent/US8541999B2/en active Active
- 2010-07-16 EP EP10737175.9A patent/EP2462683B1/en active Active
- 2010-07-16 WO PCT/US2010/042339 patent/WO2011016974A2/en active Application Filing
- 2010-07-16 CN CN201080034630.0A patent/CN102577060B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4807104A (en) * | 1988-04-15 | 1989-02-21 | Motorola, Inc. | Voltage multiplying and inverting charge pump |
| US5684682A (en) * | 1995-07-19 | 1997-11-04 | Motorola, Inc. | Method and apparatus for selectable DC to DC conversion |
| US5760637A (en) * | 1995-12-11 | 1998-06-02 | Sipex Corporation | Programmable charge pump |
| US6188590B1 (en) * | 1996-12-18 | 2001-02-13 | Macronix International Co., Ltd. | Regulator system for charge pump circuits |
| DE10149938A1 (en) * | 2001-10-10 | 2003-05-08 | Infineon Technologies Ag | Circuit arrangement for contactless chip card has charge pump circuit with amplifier stages with pump nodes, charge reservoir circuit with coupling nodes coupled pump nodes |
| US6650163B1 (en) * | 2002-08-08 | 2003-11-18 | International Business Machines Corporation | Clock generator for integrated circuit |
| CN101095276A (en) * | 2005-01-14 | 2007-12-26 | 半导体元件工业有限责任公司 | DC-to-dc converter and method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2462683A2 (en) | 2012-06-13 |
| WO2011016974A3 (en) | 2011-06-16 |
| WO2011016974A2 (en) | 2011-02-10 |
| CN102577060A (en) | 2012-07-11 |
| EP2462683B1 (en) | 2019-10-23 |
| US8541999B2 (en) | 2013-09-24 |
| US20110031957A1 (en) | 2011-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102577060B (en) | Controlling power loss in a switched-capacitor power converter | |
| US11374496B2 (en) | Driver for a circuit with a capacitive load | |
| US11239404B2 (en) | Method for reducing losses and distortion in a driver with a capacitive load | |
| CN102739045B (en) | Systems and methods for integrated switch-mode dc-dc converters for power supplies | |
| EP1664966B1 (en) | Low noise charge pump method and apparatus | |
| JP2577179B2 (en) | Quasi-resonant diode drive current source | |
| CN102377337B (en) | Switching power source apparatus | |
| CN102882369B (en) | Novel charge pump circuit in chip for motor drivers | |
| CN102332824B (en) | Time sharing multiplex control method for single-inductance double-output switching power supply and circuit thereof | |
| KR101367607B1 (en) | Synchronous dc-dc converter | |
| WO2009016898A1 (en) | Switching regulator and method for controlling operation thereof | |
| JP2013070470A (en) | Dc/dc converter | |
| TWM414763U (en) | Switching regulator and control circuit thereof | |
| CN103929048A (en) | Zero-crossing detection circuit of switching power supply | |
| US20110001462A1 (en) | Electronic device and method for dc-dc conversion | |
| CN103490631A (en) | DC-DC converter | |
| US8344762B2 (en) | Gate driving circuit | |
| Hwang et al. | A fast transient response flying-capacitor buck-boost converter utilizing pseudocurrent dynamic acceleration techniques | |
| CN102916585B (en) | Sampling hold circuit in flyback converter | |
| KR20110030373A (en) | Dc-dc converter | |
| KR101253216B1 (en) | Charge pump circuit | |
| KR101162951B1 (en) | Slop compensation circuit for boost converter | |
| CN107017771A (en) | A kind of negative supply becomes a full member power-switching circuit and positive supply turns negative electricity power-switching circuit | |
| JP5246251B2 (en) | Buck-boost DC-DC converter | |
| Shi et al. | Practical considerations for a digital inductive-switching DC/DC converter with direct battery connect in deep sub-micron CMOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141119 |