CN202267965U

CN202267965U - Field programmable gate array (FPGA) capable of performing communication with processor at high speed

Info

Publication number: CN202267965U
Application number: CN2011203633582U
Authority: CN
Inventors: 陈津; 栾庆宏; 文刚; 刘海龙
Original assignee: ZIBO KRUN ELECTRICAL CO Ltd
Current assignee: ZIBO KRUN ELECTRICAL CO Ltd
Priority date: 2011-09-26
Filing date: 2011-09-26
Publication date: 2012-06-06
Anticipated expiration: 2021-09-26

Abstract

The utility model relates to a field programmable gate array (FPGA) capable of performing communication with a processor at a high speed. The FPGA capable of performing communication with the processor at the high speed comprises the FPGA and the processor, and is characterized in that: a top layer module of the FPGA is provided with a dual-port random access memory 1 (DPRAM1) and a DPRAM2, wherein the DPRAM1 and the DPRAM2 are connected with the processor through a three-state bus. The FPGA capable of performing communication with the processor at the high speed is simple and reliable, is low in cost, and has the advantages of higher flexibility and more easiness in use than a traditional scheme in bidirectional communication; the reading and writing speeds of the FPGA are equal to those of a static random access memory (SRAM); and the requirement of mass data throughput is completely met.

Description

The FPGA that can communicate by letter with processor high speed

Technical field

The utility model relates to a kind of FPGA that can communicate by letter with processor high speed.

Background technology

Along with the reduction of FPGA cost, as high-speed parallel processing apparatus of new generation, FPGA uses more and more widely in high speed, high reliability field, becomes the only selection in the high-speed applications.Data communication between FPGA and general processor has serial and parallel dual mode; The general parallel communications mode that adopts in high data throughput is used; Implementation generally adopts outer two-port RAM of sheet or FIFO to realize; These two kinds of communication modes all need be realized through sheet outer expensive DPRAM or FIFO, realize that cost is high, and PCB layout is complicated, it is big to account for the plate area; And, must consider during PCB layout that impedance matching is isometric with wiring along with broadband increase in demand, increasingly high to the frequency of operation requirement, bad wiring very easily causes antijamming capability to descend.

The utility model content

According to above deficiency of the prior art, the technical matters that the utility model will solve is: provide a kind of and can overcome above-mentioned defective, reduce cost, and can improve the FPGA that can communicate by letter with processor high speed of communication efficiency.

The utility model solves the technical scheme that its technical matters adopted: a kind of FPGA that can communicate by letter with processor high speed; Comprise FPGA and processor; It is characterized in that: the top-level module of FPGA makes up and is provided with DPRAM1 and DPRAM2, and DPRAM1 and DPRAM2 are through tristate bus line connection processing device.

Described DPRAM1 and DPRAM2 are made up by the HDL language.

The beneficial effect that the utility model had is: simple and reliable, with low cost, and in two-way communication, have the advantage more flexible, more easy-to-use than traditional scheme, its read or write speed and SRAM are suitable, satisfy the demand of big data throughout fully.

Description of drawings

Fig. 1 is the utility model frame principle figure;

Embodiment

Below in conjunction with accompanying drawing the embodiment of the utility model is done and to further describe:

As shown in Figure 1, a kind of FPGA that can communicate by letter with processor high speed comprises FPGA and processor, and the top-level module of FPGA makes up through the HDL language and is provided with DPRAM1 and DPRAM2, and DPRAM1 and DPRAM2 are through tristate bus line connection processing device.

Wherein DPRM1 as FPGA write, processor reads; DPRAM2 as FPGA read, processor writes; The FPGA internal data flow writes DPRAM2 through the data that write data bus and write address bus will be sent to processor; Through read data bus and the taking-up general processor of reading address bus send data, SRAM control bus nCS, nOE, nWE that bus is switched through standard realize steering logic.

The utility model will be configured in the standard memory that the inner register of FPGA is converted into processor, can be through the C language at this memory block statement variable, the read-write operation of this variable is promptly accomplished the purpose of two-way communication, and very easy to use.

Claims

1. the FPGA that can communicate by letter with processor high speed comprises FPGA and processor, it is characterized in that: the top-level module of FPGA makes up and is provided with DPRAM1 and DPRAM2, and DPRAM1 and DPRAM2 are through tristate bus line connection processing device.