CN202261824U

CN202261824U - Intelligent taxi-dispatching terminal device

Info

Publication number: CN202261824U
Application number: CN2011202721336U
Authority: CN
Inventors: 邹文涛; 李敬; 宁树兴; 张瑞英; 李辉; 梁邦永
Original assignee: QINGDAO LONGERTEK TECHNOLOGY Ltd
Current assignee: QINGDAO LONGERTEK TECHNOLOGY Ltd
Priority date: 2011-07-29
Filing date: 2011-07-29
Publication date: 2012-05-30
Anticipated expiration: 2021-07-29

Abstract

The utility model discloses an intelligent taxi-dispatching terminal device, which comprises a shell, a touch screen and an intelligent control circuit board. The intelligent taxi-dispatching terminal device is characterized in that: one sidewall of the shell is provided with a mini USB (universal serial bus) interface, and another sidewall of the shell is provided with an SD (Secure Digital) card interface; and the circuits on the intelligent control circuit board are a mini USB interface circuit, an SD card interface circuit, an I2C clock interface circuit, an SRAM (static random access memory) interface circuit, an SIM (subscriber identity module) card interface circuit, a liquid crystal backlight circuit, a master processor part circuit, an SPI Nor FLASH circuit, an LCD (liquid crystal display) display circuit, an LCD screen connector circuit, a touch screen input circuit, a communication module part circuit, a power circuit and an audio circuit. The intelligent taxi-dispatching terminal device greatly increases the operation efficiency, and shortens the waiting time of both parties, moreover, the structure is complex, the fabrication cost is low, the performance is reliable and stable, and the intelligent taxi-dispatching terminal device is easy to mount and carry, and can be widely used on taxis.

Description

The taxi dispatching intelligent terminal

Technical field

The utility model relates to the mobile communications device of taxi, and specifically a kind of can the raising car efficient, is convenient to the taxi dispatching intelligent terminal that the passenger in time calls a taxi.

Background technology

The electronics applications that has intelligent function is very extensive, not only uses in fields such as various electronic toys, household electrical appliance, broadcasting equipment, various electronic instrument, military radars, and the report of application is also arranged on the minority taxi.If any on taxi, disposed vehicle GPS monitoring and scheduling terminal system; Comprise that communication module, antenna, GPS module, GPRS module or CDMA communication module, CPU and holder, camera, alarm, display screen constitute, have remote alarms and real-time release, dispatch buses, issue the function of public and business information.This vehicle GPS monitoring and scheduling terminal system has improved the efficiency of operation of vehicle undoubtedly.But the existing deficiency of this vehicle GPS monitoring and scheduling terminal system is: complex structure, and manufacturing cost is high, and inconvenience is installed, and unfailing performance is lower.

Summary of the invention

The purpose of the utility model is to provide that a kind of structure is simplified, manufacturing cost is low, easy mounting is carried, dependable performance is stablized, be exclusively used in the taxi configuration realize the about car of passenger and Real-Time Scheduling, with stand-by period of minimizing passenger; Reduce the empty wagons rate simultaneously, the taxi dispatching intelligent terminal of energy-conserving and environment-protective.

For reaching above purpose; The technical scheme that the utility model adopted is: this taxi dispatching intelligent terminal; Comprise shell body, touch-screen and intelligence control circuit plate, the intelligence control circuit plate is fixed in the shell body, and touch-screen is located on the top panel of shell body; It is characterized in that: a sidewall of said shell body is provided with the miniUSB interface, and another sidewall is provided with the SD card; Circuit on the described intelligent circuit board; Comprise the circuit of miniUSB interface, circuit and I2C clock interface circuit, SRAM interface circuit, SIM interface circuit, LCD backlight circuit, primary processor partial circuit, SPI Nor FLASH circuit, LCD display circuit, LCD screen connector circuit, touch-screen input circuit, communication module partial circuit, power circuit and the voicefrequency circuit of SD card; The circuit of I2C clock interface circuit, SPI Nor FLASH circuit, communication module partial circuit, LCD screen connector circuit, LCD backlight circuit, touch-screen input circuit, miniUSB interface and SD card all with intelligent circuit board on the primary processor partial circuit interconnect; SRAM interface circuit and LCD display circuit all interconnect with LCD screen connector circuit, and SIM interface circuit and voicefrequency circuit all interconnect with the communication module partial circuit.

The utility model is also implemented through following measure: the circuit of described miniUSB interface; Comprise chip U4 and miniUSB connector J17; USB_D+ wherein, USB_D-connect D+, the D-of miniUSB connector J17 respectively through a resistance R 20, R19; Chip U4 is PRTR5V0U2X, is a kind of electrostatic protection device.

The circuit of described SD card; Comprise SD draw-in groove CZ1,2 pin (SSP-CS) of SD draw-in groove CZ1,3 pin (SSP-MOSI), 6 pin (SSP-SCK), 8 pin (SSP-MISO) link to each other with host processor chip U10, and 10 pin link to each other with host processor chip U10 through resistance R 43, R44 respectively with 12 pin; Simultaneously be connected to VDD3.3 through R36, R35 respectively again; Capacitor C 26, C27 are filter capacitor, and an end connects VDD3.3, other end earth connection.

Described I2C clock interface circuit comprises chip U9, and chip used U9 is PCF8563; Holding wire SCL1, SDA1 link to each other with host processor chip U10, and meet VDD3.3 through resistance R 46, a R47 respectively, external independent battery BT1 between 8 pin of chip U9 and 4 pin; Capacitor C 33, C34 are filter capacitor, and BT1 is parallelly connected with independent battery, and 1 pin and 2 pin of chip U9 meet crystal oscillator X1; Crystal oscillator X1 is 32.768KHz, the 4 pin earth connections of chip U9.

Described SRAM interface circuit comprises chip U16, and its chips U16 adopts IS61LV25616AL; SRA [0..17], SRD [0..15] link to each other with the master chip U13 of LCD display circuit; The master chip U13 of LCD display circuit is MT100G16,6 pin of chip U16,40 pin, the direct ground connection of 39 pin, and 17 pin of chip U16,41 pin meet VDD3.3 through resistance R 61, a R60 respectively; Capacitor C 70, C71 are the filter capacitor of connection VDD3.3 with ground, and place near chip U16.

Described SIM interface circuit; Comprise sim card slot U15 and SIM_DATA, SIM_CLK, SIM_RST, SIM_VDD holding wire, resistance R 57～R59, electrostatic defending diode D8～D11, capacitor C 68, C69, C113～C115; In SIM_DATA, SIM_CLK, SIM_RST holding wire, be connected in series a resistance R 59, R58, the last SIM_VCC of moving to of R57 respectively; Do impedance matching usefulness, and meet ceramic condenser C69, C68 simultaneously to ground; On SIM_DATA, SIM_CLK, the SIM_RST holding wire respectively and connect capacitor C 113～C115 to ground, connect 21 pin, 23 pin, 25 pin of resistance R a 71～R73 more respectively to communication module chip U1, communication module chip U1 is SIM900B.

Described LCD backlight circuit; Comprise chip U12, VBL+ wherein, VBL-are 2 pin, the 1 pin NET label of the connector J6 of LCD screen, and 1 pin of chip U12 is connected to VBL+ through a diode D1; 3 pin of chip U12 meet VBL-, and 4 pin (Backon) of chip U12 link to each other with primary processor U10.Backon is used to control backlight illumination, if need not control backlight illumination, then Backon can directly connect height.

Said primary processor partial circuit; Comprise host processor chip U10; Filter capacitor C52～C58, C61～C63, and the holding wire that is connected with other circuit, its chips U10 adopts single-chip microcomputer LPCI768; Capacitor C 52～C58 is the filtering capacitance of voltage regulation between VDD3.3 and the DGND; Capacitor C 61, C63 are the filtering capacitance of voltage regulation between VA3.3 and the AGND, and capacitor C 62 is the filtering capacitance of voltage regulation between VREF and the AGND, and LCD_DATA [15:0], LCD_ADDR [2:0], LCD_WR# connect the master chip U13 (MT100G16) of LCD display circuit.90 pin (LCD_SCK) of chip U10,89 pin (LCD_SSEL), 88 pin (LCD_MOSI), 87 pin (LCD_GPIO), 86 pin (LCD_MISO), 25 pin (LCD_EINT) are connected with touch screen circuitry; 58 pin (SCL1) of host processor chip U10,59 pin (SDA1) link to each other with I2C interface circuit chips U9; 63 pin (SPI_CS) of host processor chip U10,61 pin (SPI_MISO), 62 pin (SPI_CLK), 60 pin (SPI_MOS) link to each other with SPI Nor FLASH circuit; 35 pin (SSP_CS) of host processor chip U10,38 pin (SSP_MOSI), 34 pin (SSP_SCK), 37 pin (SSP_MISO), 26 pin (SDPOWER), 24 pin (SDINSERT), 27 pin (SDWP) link to each other with SD card circuit; USB_D+, USB_D-connect D+, the D-of miniUSB connector J17 respectively through a resistance R 20, R19; 17 pin (nRST) of host processor chip U10 connect reset circuit; 22 pin (XTAL1) of host processor chip U10,23 pin (XTAL2) connect crystal oscillating circuit; J_nTRST, TCK, TMS, TDI, TDO, RTCK connect jtag circuit.Reset circuit U11 adopts chip CAT811S, and the used crystal oscillator Y1 of crystal oscillating circuit is 12MHz, and jtag circuit is used for simulation analysis and connects.

Described SPI Nor FLASH circuit; Comprise chip U8, SPI_CS, SPI_MISO, SPI_CLK, SPI_MOSI are respectively 1 pin, 2 pin, 6 pin of chip U8, the NET label of 5 pin, and U10 links to each other with host processor chip; Capacitor C 32 is a filter capacitor, places near chip.

Described LCD display circuit comprises master chip U13, filter capacitor C40～C43, C46～C49, and the holding wire that is connected with other circuit, and master chip U13 is MT100G16; C40～C43 is the filtering capacitance of voltage regulation between VDD3.3 and the DGND; C46～C49 is the filtering capacitance of voltage regulation between VDD1.5 and the DGND; LCD_DATA in the line of master chip [15:0], LCD_ADDR [2:0], LCD_WR# link to each other with the LPC1768 of host processor chip U10, SRA [17:0], SRD [15:0] be and memory chip IS61LV25616AL between line, LCD_R [4:0], LCD_G [5:0], LCD_B [4:0] are connected with LCD screen interface circuit; CLK connects clock circuit; Clock circuit uses crystal oscillator to be 48MHz, and RST# connects reset circuit, and U14 adopts chip CAT809TTBI-T in the reset circuit.

Described LCD screen connector circuit; Comprise connector J6; 1 pin of LCD screen connector J6, VBL-, the VBL+ of the continuous backlight circuit of 2 pin; The rgb signal line meets holding wire LCD_R [4:0], LCD_G [5:0], LCD_B [4:0] to host processor chip U10 through 10K resistance R P4, RP5, RP6, and LCD_DCLK, LCD_DEN receive host processor chip U10 through 10K resistance, and XL, XR, YU, YD link to each other with the touch-screen input circuit.

Said touch-screen input circuit; Comprise chip U17; 16 pin (LCD_SCK) of chip U17,15 pin (LCD_SSEL), 14 pin (LCD_MOSI), 13 pin (LCD_GPIO), 12 pin (LCD_MISO), 11 pin (LCD_EINT) link to each other with host processor chip U10; 2 pin of chip U17,3 pin, 4 pin, 5 pin link to each other with 39 pin, 40 pin, 37 pin, 38 pin of LCD screen connector J6, the voltage that connects and be simulation.

Described communication module partial circuit comprises communication module U1, and communication module U1 connects voicefrequency circuit, SIM circuit; Communication module U1 uses SIM900B, and wherein 1～8 pin connects VDD, and the capacitor C 17～C18 in the miniUSB interface circuit is an electric capacity of voltage regulation; 9～14 pin ground connection of communication module U1 provide the power supply of a 2.8V on the 17 pin VDD_EXT, the power supply that can be used as external module uses, and C19 is a filtering capacitance of voltage regulation.34 pin of communication module U1 are POWER_ON, link to each other with 33 pin of primary processor U10.40,42 pin of communication module U1 are Serial Port Line, link to each other with 74,75 pin of host processor chip U10.19 pin of communication module U1,21 pin, 23 pin, 25 pin have connected the SIM circuit; 53 pin of communication module U1,55 pin have connected the MIC circuit in the voicefrequency circuit; 54 pin of communication module U1,56 pin have connected the horn circuit in the voicefrequency circuit; 57～60 pin of communication module U1 have connected the head circuit in the voicefrequency circuit, and 50 pin of communication module U1,51 pin connect simulation ground.

Described power circuit; Comprise capacitor C 1～C4, C28～C31, ESD device D2, K switch 1, battery interface J0, J2, charging U mouth J1, magnetic bead FB1, FB2, voltage transitions chip U3, U6; Capacitor C 1～C4 is a filtering capacitance of voltage regulation; D2 is the ESD device at power import place, and J1 is a battery charge U mouth, judges through NET POWER_OFF whether electric weight is full of; 1 pin of J0 connects the electric core voltage of battery, collects in the single-chip microcomputer through resistance, electric capacity, can be used to judge the current electric quantity of battery; VDD is used for communication module power supply, links to each other with VDD3.3 through a magnetic bead FB1, uses magnetic bead FB2 to link to each other between VA3.3 and VDD3.3, and voltage transitions chip U3 exports VREF voltage, and U6 exports VDD1.5 voltage.

Described voicefrequency circuit comprises that D3～D8 and C101～C111 form; D3～D6 is the antistatic device of 2 differential pairs; Be the difference input and output; The common mode radio noise that the difference inputoutput pair is caused by the transmission of TDMA RF-wise has the obvious suppression effect, in the Microphone difference input circuit, connects two capacitor C 109, C110 between the differential lines and respectively meets two capacitor C 107, C108, C111, C112 to ground; Be connected to 53 pin, 55 pin of SIM900B communication module connecting circuit U1; In the Speaker differential output circuit, the SIM900B communication module connects audio amplifier circuit, and audio power amplifies chip U2 and adopts chip MC34119; Audio power amplifies between the differential lines output of chip U2 and connects two capacitor C 104, C103 and respectively meet two capacitor C 102, C101, C106, C105 to ground, is connected to the interface of Speaker.Head circuit comprises Mic difference input circuit and Speaker output circuit, in the Mic difference input circuit, partly is being the difference wiring near communication module; Near the earphone interface place, holding wire MIC2_N meets AGND, and MIC2_P connects a capacitor C 84 to AGND; At 2 pin through a resistance R 63 to earphone interface J18; Also capacitor C 85, an antistatic device D7 arrive ground between resistance R 63 and earphone interface, the direct ground connection of SPK2_N in the Speaker output circuit, and SPK2_P is connected in series a capacitor C 123; A resistance R 76 is to earphone interface; Individual also capacitor C 124, a C125 arrive ground at resistance R 76 two ends, arrive ground near earphone interface place and two capacitor C 86, C87, and antistatic device D8 arrive ground as antistatic protection.

The power supply of a 2.8V is provided on 17 pin VDD_EXT on the communication module SIM900B.

The utility model is through powered battery, cell voltage at 3.5V between the 3.6V.

The beneficial effect of the utility model is: compare with the vehicle GPS monitoring and scheduling terminal system of present report; Not only improved efficiency of operation greatly; Reduced both sides' stand-by period, and complex structure, manufacturing cost is low, easy mounting is carried, dependable performance is stablized.Can extensively on taxi, use.

Description of drawings

Fig. 1 cuts open sketch map for the structure office of overlooking of the utility model;

Fig. 2 is the structural principle block diagram of the utility model;

Fig. 3 is the utility model I2C interface circuit schematic diagram;

Fig. 4 is the utility model SPI Nor FLASH circuit theory diagrams;

Fig. 5-1 is the utility model LCD screen connector circuit schematic diagram;

Fig. 5-2 is the utility model SRAM interface circuit schematic diagram;

Fig. 6-1 is the utility model miniUSB interface circuit schematic diagram;

Fig. 6-2 is the utility model SD card circuit theory diagrams;

Fig. 7-1 is the utility model communication module partial circuit, voicefrequency circuit schematic diagram;

Fig. 7-2 is the utility model SIM circuit theory diagrams;

Fig. 8 is the utility model LCD backlight circuit and touch-screen input circuit schematic diagram;

Fig. 9 is the utility model power circuit principle figure;

Figure 10 is the utility model primary processor partial circuit schematic diagram;

Figure 11 is the utility model LCD display circuit schematic diagram.

Embodiment

Make the utility model with reference to Fig. 1,2,3,4,5-1,5-2,6-1,6-2,7-1,7-2,8,9,10,11.This taxi dispatching intelligent terminal; Comprise shell body 1, touch-screen 2 and intelligence control circuit plate 3; Intelligence control circuit plate 3 is fixed in the shell body 1; Touch-screen 2 is located on the top panel of shell body 1, it is characterized in that: a sidewall of said shell body 1 is provided with miniUSB interface 4, and another sidewall is provided with SD card 5; Circuit on the described intelligent circuit board 3; Comprise the circuit of miniUSB interface 4, circuit and I2C clock interface circuit, SRAM interface circuit, SIM interface circuit, LCD backlight circuit, primary processor partial circuit, SPI Nor FLASH circuit, LCD display circuit, LCD screen connector circuit, touch-screen input circuit, communication module partial circuit, power circuit and the voicefrequency circuit of SD card 5; The circuit of I2C clock interface circuit, SPI Nor FLASH circuit, communication module partial circuit, LCD screen connector circuit, LCD backlight circuit, touch-screen input circuit, miniUSB interface 4 and SD card 5 all with intelligent circuit board 3 on the primary processor partial circuit interconnect; SRAM interface circuit and LCD display circuit all interconnect with LCD screen connector circuit, and SIM interface circuit and voicefrequency circuit all interconnect with the communication module partial circuit.

The utility model is also implemented through following measure: the circuit of described miniUSB interface 4; Shown in Fig. 6-1; Comprise chip U4 and miniUSB connector J17; USB_D+ wherein, USB_D-connect D+, the D-of miniUSB connector J17 respectively through a resistance R 20, R19, chip U4 is PRTR5V0U2X, is a kind of electrostatic protection device.

The circuit of described SD card 5 with shown in Figure 10, comprises SD draw-in groove CZ1 like Fig. 6-2; 2 pin (SSP-CS) of SD draw-in groove CZ1,3 pin (SSP-MOSI), 6 pin (SSP-SCK), 8 pin (SSP-MISO) link to each other with host processor chip U10; 10 pin link to each other with host processor chip U10 through resistance R 43, R44 respectively with 12 pin, are connected to VDD3.3 through R36, R35 respectively again simultaneously, and capacitor C 26, C27 are filter capacitor; One end connects VDD3.3, other end earth connection.

Described I2C clock interface circuit, as shown in Figure 3, comprise chip U9; Chip used U9 is PCF8563, and holding wire SCL1, SDA1 link to each other with host processor chip U10, and meet VDD3.3 through resistance R 46, a R47 respectively; External independent battery BT1 between 8 pin of chip U9 and 4 pin, capacitor C 33, C34 are filter capacitor, BT1 is parallelly connected with independent battery; 1 pin and 2 pin of chip U9 meet crystal oscillator X1, and crystal oscillator X1 is 32.768KHz, the 4 pin earth connections of chip U9.

Described SRAM interface circuit; Like Fig. 5-2, shown in Figure 11, comprise chip U16, its chips U16 adopts IS61LV25616AL; SRA [0..17], SRD [0..15] link to each other with the master chip U13 of LCD display circuit; The master chip U13 of LCD display circuit is MT100G16,6 pin of chip U16,40 pin, the direct ground connection of 39 pin, and 17 pin of chip U16,41 pin meet VDD3.3 through resistance R 61, a R60 respectively; Capacitor C 70, C71 are the filter capacitor of connection VDD3.3 with ground, and place near chip U16.

Described SIM interface circuit; Shown in Fig. 7-2,7-1; Comprise sim card slot U15 and SIM_DATA, SIM_CLK, SIM_RST, SIM_VDD holding wire, resistance R 57～R59, electrostatic defending diode D8～D11, capacitor C 68, C69, C113～C115; In SIM_DATA, SIM_CLK, SIM_RST holding wire, be connected in series a resistance R 59, R58, the last SIM_VCC of moving to of R57 respectively, do impedance matching usefulness, and meet ceramic condenser C69, C68 simultaneously to ground; On SIM_DATA, SIM_CLK, the SIM_RST holding wire respectively and connect capacitor C 113～C115 to ground, connect 21 pin, 23 pin, 25 pin of resistance R a 71～R73 more respectively to communication module chip U1, communication module chip U1 is SIM900B, shown in Fig. 7-1.

Described LCD backlight circuit; As shown in Figure 8; Comprise chip U12, VBL+ wherein, VBL-are 2 pin, the 1 pin NET label of the connector J6 of LCD screen, and 1 pin of chip U12 is connected to VBL+ through a diode D1; 3 pin of chip U12 meet VBL-, and 4 pin (Backon) of chip U12 link to each other with primary processor U10.Backon is used to control backlight illumination, if need not control backlight illumination, then Backon can directly connect height.

Said primary processor partial circuit; Shown in figure 10, comprise host processor chip U10, filter capacitor C52～C58, C61～C63; And the holding wire that is connected with other circuit; Its chips U10 adopts single-chip microcomputer LPC1768, and capacitor C 52～C58 is the filtering capacitance of voltage regulation between VDD3.3 and the DGND, and capacitor C 61, C63 are the filtering capacitance of voltage regulation between VA3.3 and the AGND; Capacitor C 62 is the filtering capacitance of voltage regulation between VREF and the AGND, and LCD_DATA [15:0], LCD_ADDR [2:0], LCD_WR# connect the master chip U13 (MT100G16) of LCD display circuit.90 pin (LCD_SCK) of chip U10,89 pin (LCD_SSEL), 88 pin (LCD_MOSI), 87 pin (LCD_GPIO), 86 pin (LCD_MISO), 25 pin (LCD_EINT) are connected with touch screen circuitry; 58 pin (SCL1) of host processor chip U10,59 pin (SDA1) link to each other with I2C interface circuit chips U9; 63 pin (SPI_CS) of host processor chip U10,61 pin (SPI_MISO), 62 pin (SPI_CLK), 60 pin (SPI_MOS) link to each other with SPI Nor FLASH circuit; 35 pin (SSP_CS) of host processor chip U10,38 pin (SSP_MOSI), 34 pin (SSP_SCK), 37 pin (SSP_MISO), 26 pin (SDPOWER), 24 pin (SDINSERT), 27 pin (SDWP) link to each other with SD card circuit; USB_D+, USB_D-connect D+, the D-of miniUSB connector J17 respectively through a resistance R 20, R19; 17 pin (nRST) of host processor chip U10 connect reset circuit; 22 pin (XTAL1) of host processor chip U10,23 pin (XTAL2) connect crystal oscillating circuit; J_nTRST, TCK, TMS, TDI, TDO, RTCK connect jtag circuit.Reset circuit U11 adopts chip CAT811S, and the used crystal oscillator Y1 of crystal oscillating circuit is 12MHz, and jtag circuit is used for simulation analysis and connects.

Described SPI Nor FLASH circuit, as shown in Figure 4, comprise chip U8; SPI_CS, SPI_MISO, SPI_CLK, SPI_MOSI are respectively 1 pin, 2 pin, 6 pin of chip U8, the NET label of 5 pin; U10 links to each other with host processor chip, and capacitor C 32 is a filter capacitor, places near chip.

Described LCD display circuit, shown in figure 11, comprise master chip U13, filter capacitor C40～C43, C46～C49, and the holding wire that is connected with other circuit, master chip U13 is MT100G16; C40～C43 is the filtering capacitance of voltage regulation between VDD3.3 and the DGND; C46～C49 is the filtering capacitance of voltage regulation between VDD1.5 and the DGND; LCD_DATA in the line of master chip [15:0], LCD_ADDR [2:0], LCD_WR# link to each other with the LPC1768 of host processor chip U10, SRA [17:0], SRD [15:0] be and memory chip IS61LV25616AL between line, LCD_R [4:0], LCD_G [5:0], LCD_B [4:0] are connected with LCD screen interface circuit; CLK connects clock circuit; Clock circuit uses crystal oscillator to be 48MHz, and RST# connects reset circuit, and U14 adopts chip CAT809TTBI-T in the reset circuit.

Described LCD screen connector circuit; Shown in Fig. 5-1; Comprise connector J6,1 pin of LCD screen connector J6, VBL-, the VBL+ of the continuous backlight circuit of 2 pin, the rgb signal line meets holding wire LCD_R [4:0], LCD_G [5:0], LCD_B [4:0] to host processor chip U10 through 10K resistance R P4, RP5, RP6; LCD_DCLK, LCD_DEN receive host processor chip U10 through 10K resistance, and XL, XR, YU, YD link to each other with the touch-screen input circuit.

Said touch-screen input circuit; Shown in Fig. 8, Fig. 5-1; Comprise chip U17; 16 pin (LCD_SCK) of chip U17,15 pin (LCD_SSEL), 14 pin (LCD_MOSI), 13 pin (LCD_GPIO), 12 pin (LCD_MISO), 11 pin (LCD_EINT) link to each other with host processor chip U10,2 pin of chip U17,3 pin, 4 pin, 5 pin link to each other with 39 pin, 40 pin, 37 pin, 38 pin of LCD screen connector J6, the voltage that connects and be simulation.

Described communication module partial circuit shown in Fig. 7-1 and Fig. 6-1, comprises communication module U1, and communication module U1 connects voicefrequency circuit, SIM circuit; Communication module U1 uses SIM900B, and wherein 1～8 pin connects VDD, and the capacitor C 17～C18 in the miniUSB interface circuit is an electric capacity of voltage regulation; 9～14 pin ground connection of communication module U1 provide the power supply of a 2.8V on the 17 pin VDD_EXT, the power supply that can be used as external module uses, and C19 is a filtering capacitance of voltage regulation.34 pin of communication module U1 are POWER_ON, link to each other with 33 pin of primary processor U10.40,42 pin of communication module U1 are Serial Port Line, link to each other with 74,75 pin of host processor chip U10.19 pin of communication module U1,21 pin, 23 pin, 25 pin have connected the SIM circuit; 53 pin of communication module U1,55 pin have connected the MIC circuit in the voicefrequency circuit; 54 pin of communication module U1,56 pin have connected the horn circuit in the voicefrequency circuit; 57～60 pin of communication module U1 have connected the head circuit in the voicefrequency circuit, and 50 pin of communication module U1,51 pin connect simulation ground.

Described power circuit; As shown in Figure 9; Comprise capacitor C 1～C4, C28～C31, ESD device D2, K switch 1, battery interface J0, J2, charging U mouth J1, magnetic bead FB1, FB2, voltage transitions chip U3, U6, capacitor C 1～C4 is a filtering capacitance of voltage regulation, and D2 is the ESD device at power import place; J1 is a battery charge U mouth, judges through NET POWER_OFF whether electric weight is full of; 1 pin of J0 connects the electric core voltage of battery, collects in the single-chip microcomputer through resistance, electric capacity, can be used to judge the current electric quantity of battery; VDD is used for communication module power supply, links to each other with VDD3.3 through a magnetic bead FB1, uses magnetic bead FB2 to link to each other between VA3.3 and VDD3.3, and voltage transitions chip U3 exports VREF voltage, and U6 exports VDD1.5 voltage.

The power supply of a 2.8V is provided on 17 pin VDD_EXT on the communication module SIM900B, and the power supply that can be used as external module uses.

The utility model is through powered battery, cell voltage at 3.5V between the 3.6V.Installation procedure is brief, and cost is few, and circuit is simple, and circuit is reliable.

Claims

1. taxi dispatching intelligent terminal; Comprise shell body (1), touch-screen (2) and intelligence control circuit plate (3); Intelligence control circuit plate (3) is fixed in the shell body (1); Touch-screen (2) is located on the top panel of shell body (1), it is characterized in that: a sidewall of said shell body (1) is provided with miniUSB interface (4), and another sidewall is provided with SD card (5); Circuit on the described intelligent circuit board (3) comprises the circuit of miniUSB interface (4), circuit and I2C clock interface circuit, SRAM interface circuit, SIM interface circuit, LCD backlight circuit, primary processor partial circuit, SPI Nor FLASH circuit, LCD display circuit, LCD screen connector circuit, touch-screen input circuit, communication module partial circuit, power circuit and the voicefrequency circuit of SD card (5); The circuit of I2C clock interface circuit, SPI Nor FLASH circuit, communication module partial circuit, LCD screen connector circuit, LCD backlight circuit, touch-screen input circuit, miniUSB interface (4) and the circuit of SD card (5) all with intelligent circuit board (3) on the primary processor partial circuit interconnect; SRAM interface circuit and LCD display circuit all interconnect with LCD screen connector circuit, and SIM interface circuit and voicefrequency circuit all interconnect with the communication module partial circuit.

2. taxi dispatching intelligent terminal according to claim 1; The circuit that it is characterized in that described miniUSB interface (4); Comprise chip U4 and miniUSB connector J17; USB_D+ wherein, USB_D-connect D+, the D-of miniUSB connector J17 respectively through a resistance R 20, R19, chip U4 is PRTR5V0U2X, is a kind of electrostatic protection device.

3. taxi dispatching intelligent terminal according to claim 1 is characterized in that the circuit of described SD card (5) comprising SD draw-in groove CZ1; 2 pin of SD draw-in groove CZ1,3 pin, 6 pin, 8 pin link to each other with host processor chip U10; 10 pin are connected with host processor chip U10 through resistance R 43, R44 respectively with 12 pin, are connected to VDD3.3 through resistance R 36, R35 respectively again simultaneously, and capacitor C 26, C27 are filter capacitor; One end connects VDD3.3, other end earth connection.

4. taxi dispatching intelligent terminal according to claim 1 is characterized in that described I2C clock interface circuit, comprises chip U9; Chip used U9 is PCF8563; Holding wire SCL1, SDA1 link to each other with host processor chip U10, and meet VDD3.3 through resistance R 46, a R47 respectively, external independent battery BT1 between 8 pin of chip U9 and 4 pin; Capacitor C 33, C34 are filter capacitor; BT1 is parallelly connected with independent battery, and 1 pin and 2 pin of chip U9 meet crystal oscillator X1, the 4 pin earth connections of chip U9.

5. taxi dispatching intelligent terminal according to claim 1; It is characterized in that described SRAM interface circuit; Comprise chip U16, its chips U16 adopts IS61LV25616AL, and SRA, SRD link to each other with the master chip U13 of LCD display circuit; The master chip U13 of LCD display circuit is MT100G16; 6 pin of chip U16,40 pin, the direct ground connection of 39 pin, 17 pin of chip U16,41 pin meet VDD3.3 through resistance R 61, a R60 respectively, and capacitor C 70, C71 are for connecting the filter capacitor on VDD3.3 and ground.

6. taxi dispatching intelligent terminal according to claim 1; It is characterized in that described SIM interface circuit; Comprise sim card slot U15 and SIM_DATA, SIM_CLK, SIM_RST, SIM_VDD holding wire, resistance R 57～R59, electrostatic defending diode D8～D11, capacitor C 68～C69, C113～C115; In SIM_DATA, SIM_CLK, SIM_RST holding wire, be connected in series a resistance R 59, R58, the last SIM_VCC of moving to of R57 respectively, and meet ceramic condenser C69, C68 simultaneously to ground; On SIM_DATA, SIM_CLK, the SIM_RST holding wire respectively and connect capacitor C 113～C115 to ground, connect 21 pin, 23 pin, 25 pin of resistance R a 71～R73 more respectively to communication module chip U1.

7. taxi dispatching intelligent terminal according to claim 1; It is characterized in that described LCD backlight circuit, comprise chip U12,1 pin of chip U12 is connected to VBL+ through a diode D1; 3 pin of chip U12 meet VBL-, and 4 pin of chip U12 link to each other with host processor chip U10.

8. taxi dispatching intelligent terminal according to claim 1; It is characterized in that described primary processor partial circuit; Comprise host processor chip U10, filter capacitor C52～C58, C61～C63, its chips U10 adopts single-chip microcomputer LPC1768; Capacitor C 52～C58 is the filtering capacitance of voltage regulation between VDD3.3 and the DGND; Capacitor C 61, C63 are the filtering capacitance of voltage regulation between VA3.3 and the AGND, and capacitor C 62 is the filtering capacitance of voltage regulation between VREF and the AGND, and LCD_DATA [15:0], LCD_ADDR [2:0], LCD_WR# connect the master chip U13 of LCD display circuit; 90 pin of chip U10,89 pin, 88 pin, 87 pin, 86 pin, 25 pin are connected with touch screen circuitry; 58 pin of host processor chip U10,59 pin link to each other with I2C interface circuit chips U9; 63 pin of chip U10,61 pin, 62 pin, 60 pin link to each other with SPI Nor FLASH circuit; 35 pin of chip U10,38 pin, 34 pin, 37 pin, 26 pin, 24 pin, 27 pin link to each other with SD card circuit; USB_D+, USB_D-connect D+, the D-of miniUSB connector J17 respectively through a resistance R 20, R19; 17 pin of chip U10 connect reset circuit; 22 pin of chip U10,23 pin connect crystal oscillating circuit.

9. taxi dispatching intelligent terminal according to claim 1 is characterized in that described SPINor FLASH circuit, comprises chip U8, and U10 links to each other with host processor chip, and capacitor C 32 is a filter capacitor.