CN202189783U - 灯驱合一的柱状rgb全彩led混合封装结构 - Google Patents

灯驱合一的柱状rgb全彩led混合封装结构 Download PDF

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CN202189783U
CN202189783U CN201120080400XU CN201120080400U CN202189783U CN 202189783 U CN202189783 U CN 202189783U CN 201120080400X U CN201120080400X U CN 201120080400XU CN 201120080400 U CN201120080400 U CN 201120080400U CN 202189783 U CN202189783 U CN 202189783U
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pin
led
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乔红瑗
姜亮亮
丁佳卿
杨晓鹏
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SHANGHAI DOUBLE MICROELECTRONICS CO Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

本实用新型公开了一种灯驱合一的柱状RGB全彩LED混合封装结构;包括:LED驱动芯片和LED灯芯片;所述LED驱动芯片和LED灯芯片被封装在柱状LED灯柱内部;从柱状LED灯柱内部向下引出LED驱动芯片和/或LED灯芯片的引脚。本实用新型可以提高***集成度,相对于现有产品有更高的封装可靠性,更高的亮度,更好的防水性能。

Description

灯驱合一的柱状RGB全彩LED混合封装结构
技术领域
本实用新型涉及一种LED芯片与驱动IC的多芯片混合封装结构。 
背景技术
目前,随着LED越来越被广泛的应用,除白光LED广泛的被用于照明、背光等领域,由RGB混合而成的白光也将在更高要求领域被人们认可。就RGB本身来讲,应用于装饰以及由其作为像素点实现大屏幕显示也越来越被广泛应用。 
目前,无论是用于显示还是装饰,LED都不可避免的需要专用的驱动IC,而且现有的驱动模式是驱动IC和LED分别独立封装后在外部再进行连接,因此驱动IC占了整机成本的很大比重,而且采用大量的驱动IC使LED整机的重量大大增加,对整机的安装带来极大不便,并且不可避免的影响其可靠性,给检修也带来复杂性。 
实用新型内容
本实用新型所要解决的技术问题是提供一种灯驱合一的柱状RGB全彩LED混合封装结构,它可以提高***集成度,相对于现有产品有更高的封装可靠性,更高的亮度,更好的防水性能。 
为了解决以上技术问题,本实用新型提供了一种灯驱合一的柱状RGB全彩LED混合封装结构;包括:LED驱动芯片和LED灯芯片;所述LED驱动芯片和LED灯芯片被封装在柱状LED灯柱内部。 
本实用新型的有益效果在于:可以提高***集成度,相对于现有产品有更高的封装可靠性,更高的亮度,更好的防水性能。 
优选的,从柱状LED灯柱内部向下引出LED驱动芯片和/或LED灯芯片的引 脚。 
优选的,所述LED灯芯片包括红色LED灯芯片、绿色LED灯芯片和蓝色LED灯芯片;所述柱状体形状可以为圆形、椭圆或矩形。 
优选的,对于双线传输芯片,其有6根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的负极相连,三颗LED芯片的正极与驱动芯片的VDD端都连接在VDD管脚;时钟输入端和数据输入端分别连接在CIN和DIN管脚;时钟输出端和数据输出端分别连接在Cout和Dout管脚。 
优选的,对于单线传输芯片,其有4根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的负极相连,三颗LED芯片的正极与驱动芯片的VDD端都连接在VDD管脚;数据输入端连接在DIN管脚;数据输出端连接在Dout管脚。 
优选的,对于双线传输芯片,其有6根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的正极相连,三颗LED芯片的负极与驱动芯片的地端都连接在地管脚;时钟输入端和数据输入端分别连接在CIN和DIN管脚;时钟输出端和数据输出端分别连接在Cout和Dout管脚。 
优选的,对于单线传输芯片,其有4根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的正极相连,三颗LED芯片的负极与驱动芯片的地端都连接在地管脚;数据输入端连接在DIN管脚;数据输出端连接在Dout管脚。 
优选的,内置的驱动IC芯片的供电模式为恒流供电,内置驱动IC带有温度传感器和控制模块,可以控制LED芯片温度。 
优选的,内置驱动IC有数据级联功能,将驱动芯片的数据线串联后可以实现对整条串联LED灯进行控制,所述级联采用单线或双线级联通信方式。 
优选的,用于LED显示屏。 
附图说明
下面结合附图和具体实施方式对本实用新型作进一步详细说明。 
图1是本实用新型实施例所述双线LED混合封装结构正视图; 
图2是本实用新型实施例所述双线LED混合封装结构45度斜视图; 
图3是本实用新型实施例所述单线LED混合封装结构正视图; 
图4是本实用新型实施例所述单线LED混合封装结构45度斜视图; 
图5是本实用新型实施例所述双线信号控制模式原理图; 
图6是本实用新型实施例所述单线信号控制模式原理图; 
图7是本实用新型实施例所述双线LED混合封装连接图; 
图8是本实用新型实施例所述单线LED混合封装连接图; 
图9是本实用新型实施例所述控制电路级联示意图。 
具体实施方式
本实用新型提供了一种将RGB三种颜色LED芯片与驱动芯片同时封装在柱状的LED灯珠内部的结构。其提高***集成度,相对于贴片混合封装的灯驱合一LED产品有更高的封装可靠性,更高的亮度,更好的防水性能。 
如图1、图2、图7所示,所述LED灯芯片包括红色LED灯芯片5、绿色LED灯芯片3和蓝色LED灯芯片4。其可以采用的结构是在绿色LED灯芯片3和蓝色LED灯芯片4周围涂有绝缘胶,在红色LED灯芯片5和驱动芯片6周围涂有导电 胶。本实用新型将RGB三色LED芯片与驱动芯片6封装在柱状LED灯柱1内部,采用6立式排布管脚的框架2,其中两个管脚顶端有两个较大的基岛用于装载驱动IC芯片6和RGB三色芯片,所述芯片6垂直于引出的管脚10。驱动芯片6的三个输出端分别与RGB三颗LED芯片的负极相连,三颗LED芯片的正极与驱动芯片的VDD端都连接在VDD管脚。对于双线传输芯片,时钟输入端和数据输入端分别连接在CIN和DIN管脚。时钟输出端和数据输出端分别连接在Cout和Dout管脚。加上VDD管脚,芯片的GND管脚共有CIN、DIN、VDD、GND、COUT、DOUT,6个管脚。图7中,7为导电胶、8为绝缘胶、9为导电胶。 
如图3、图4、图8所示,对于单线传输芯片,没有时钟信号线,只有数据输入端和数据输出端分别连接在Din和Dout管脚。共有VDD、GND、DIN、DOUT四个管脚。 
作为另外一种变形,可以将驱动芯片6的三个输出端分别与RGB三颗LED芯片的正极相连,三颗LED芯片的负极与驱动芯片的地端都连接在地管脚。 
如图5、图6所示,内置的驱动IC使得DBLED或DBRGB的供电模式由恒压变为恒流供电,对工作电压的要求降低,具有更宽的工作电压范围。内置驱动IC带有温度控制,可以控制LED芯片温度,有效地降低LED的色衰,延长LED芯片使用寿命。 
如图9所示,内置驱动IC设计有数据级联功能,将DBLED或DBRGB的数据线串联后可以实现对整条串联的DBLED或DBRGB进行控制。每颗DBLED或DBRGB都可以作为一个象素点,实现图像显示不再需要单独的驱动IC,级联采用单线或双线级联通信方式。 
本实用新型并不限于上文讨论的实施方式。以上对具体实施方式的描述旨在于为了描述和说明本实用新型涉及的技术方案。基于本实用新型启示的显而 易见的变换或替代也应当被认为落入本实用新型的保护范围。以上的具体实施方式用来揭示本实用新型的最佳实施方法,以使得本领域的普通技术人员能够应用本实用新型的多种实施方式以及多种替代方式来达到本实用新型的目的。 

Claims (10)

1.一种灯驱合一的柱状RGB全彩LED混合封装结构;其特征在于,包括:LED驱动芯片和LED灯芯片;
所述LED驱动芯片和LED灯芯片被封装在柱状LED灯柱内部。
2.如权利要求1所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,从柱状LED灯柱内部向下引出LED驱动芯片和/或LED灯芯片的引脚。
3.如权利要求1所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,所述LED灯芯片包括红色LED灯芯片、绿色LED灯芯片和蓝色LED灯芯片;所述柱状体形状可以为圆形、椭圆或矩形。
4.如权利要求3所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,对于双线传输芯片,其有6根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的负极相连,三颗LED芯片的正极与驱动芯片的VDD端都连接在VDD管脚;时钟输入端和数据输入端分别连接在CIN和DIN管脚;时钟输出端和数据输出端分别连接在Cout和Dout管脚。
5.如权利要求3所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,对于单线传输芯片,其有4根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的负极相连,三颗LED芯片的正极与驱动芯片的VDD端都连接在VDD管脚;数据输入端连接在DIN管脚;数据输出端连接在Dout管脚。
6.如权利要求3所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,对于双线传输芯片,其有6根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输 出端分别与RGB三颗LED芯片的正极相连,三颗LED芯片的负极与驱动芯片的地端都连接在地管脚;时钟输入端和数据输入端分别连接在CIN和DIN管脚;时钟输出端和数据输出端分别连接在Cout和Dout管脚。
7.如权利要求3所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,对于单线传输芯片,其有4根立式排布管脚,其中管脚顶端用于装载驱动IC芯片和RGB三色芯片,所述芯片垂直于引出的管脚;驱动芯片的三个输出端分别与RGB三颗LED芯片的正极相连,三颗LED芯片的负极与驱动芯片的地端都连接在地管脚;数据输入端连接在DIN管脚;数据输出端连接在Dout管脚。
8.如权利要求4或5或6或7所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,内置的驱动IC芯片的供电模式为恒流供电,内置驱动IC带有温度传感器和控制模块,可以控制LED芯片温度。
9.如权利要求4或5或6或7所述的灯驱合一的柱状RGB全彩LED混合封装结构,其特征在于,内置驱动IC有数据级联功能,将驱动芯片的数据线串联后可以实现对整条串联LED灯进行控制,所述级联采用单线或双线级联通信方式。
10.一种灯驱合一的柱状RGB全彩LED混合封装结构;其特征在于,用于LED显示屏。 
CN201120080400XU 2011-03-24 2011-03-24 灯驱合一的柱状rgb全彩led混合封装结构 Expired - Lifetime CN202189783U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2497183A (en) * 2011-11-29 2013-06-05 Ibm Light emitting diode (LED) with three active regions and intensity control unit
CN110415641A (zh) * 2019-08-26 2019-11-05 深圳市好的照明有限公司 一种双线级联led驱动电路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2497183A (en) * 2011-11-29 2013-06-05 Ibm Light emitting diode (LED) with three active regions and intensity control unit
CN110415641A (zh) * 2019-08-26 2019-11-05 深圳市好的照明有限公司 一种双线级联led驱动电路

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