CN202120882U - 四面无引脚半导体封装模具结构 - Google Patents

四面无引脚半导体封装模具结构 Download PDF

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CN202120882U
CN202120882U CN 201120201239 CN201120201239U CN202120882U CN 202120882 U CN202120882 U CN 202120882U CN 201120201239 CN201120201239 CN 201120201239 CN 201120201239 U CN201120201239 U CN 201120201239U CN 202120882 U CN202120882 U CN 202120882U
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lead frame
mold
electromagnet
utility
pins
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王新潮
谢洁人
吴昊
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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Abstract

本实用新型涉及一种四面无引脚半导体封装模具结构，所述模具结构包括引线框，引线框采用磁性材料制作，引线框包括基岛（1）和引脚（2），引线框上设置有芯片（5）和金属线（6），所述设置有芯片（5）和金属线（6）的引线框放置于一上模（8）与一下模（9）之间，下模（9）连有电磁铁（10）。在封装时，通过连接在包封模具上的电磁铁开关，使磁性引线框吸合在封装模具上，可以省去传统的背面贴膜，降低了引线框制造成本。而且背面不贴附柔软的胶膜，打线时更容易控制产品质量，提高产品良率。

Description

四面无引脚半导体封装模具结构
技术领域
本实用新型涉及一种半导体封装模具结构。属于半导体封装技术领域。
背景技术
传统四面无引脚引线框的结构，是采用先在金属基板的正面进行化学蚀刻及表面电镀后，再在金属基板的背面贴上一层耐高温的胶膜形成可以进行封装过程的引线框载体（如图1所示），再将引线框载体进行装片打线，最后再进行塑封料的封装。但是由于此种封装方式引线框背面必须要贴上一层昂贵可抗高温的胶膜，所以直接增加了封装成本。又由于胶膜质地柔软，在装片打线过程中，容易造成打线松动和焊点不牢等问题，如图2。而且在封装过程中经常会出现胶膜粘贴不良，从而导致封装过程中塑封料溢料到引线框正面的基岛或引脚形成不良品。
发明内容
本实用新型的目的在于克服上述不足，提供一种封装成本低、不会引起打线不良等问题以及可以有效的避免溢料的四面无引脚半导体封装模具结构。
本实用新型的目的是这样实现的：一种四面无引脚半导体封装模具结构，所述模具结构包括引线框，引线框采用磁性材料制作，引线框包括基岛和引脚，引线框上设置有芯片和金属线，所述设置有芯片和金属线的引线框放置于一上模与一下模之间，下模连有电磁铁。
本实用新型四面无引脚半导体封装模具结构，还可以在所述上模上施加有与所述下模上的电磁铁极性相反的另一电磁铁。
本实用新型四面无引脚半导体封装模具结构，所述磁性材料为铁或铁合金。
本实用新型四面无引脚半导体封装模具结构，所述磁性材料为铁与铜的复合材料；或为铁合金与铜的复合材料。
由于引线框与下模紧密吸附，塑封料不会钻入引线框上基岛及引脚的底部，省去了贴膜。待塑封料固化后，即完成了传统的包封工序。
本实用新型的有益效果是： 
本实用新型模具结构采用磁性金属制作的四面无引脚引线框结构，省去了背面的胶膜，不仅降低了封装成本，而且在装片打线工艺中，不会出现打线不良，焊点松动等问题。在后续封装时，并且在封装时采用带磁性的包封模具来包封塑封料，通过选择电磁铁的开或关，来控制是否吸附住磁性引线框。当包封模具吸附住引线框时，可以有效的避免溢料。
附图说明
图1为以往在四面无引脚引线框背面贴上耐高温胶膜的示意图。
图2为以往贴胶膜的四面无引脚引线框打线示意图。
图3为本实用新型采用的四面无引脚引线框结构的示意图。
图4为本实用新型的四面无引脚引线框打线示意图。
图5为本实用新型四面无引脚半导体封装模具结构示意图。
图中附图标记：
基岛1
引脚2
胶膜  3
半蚀刻连筋4
芯片5
金属线6
劈刀7
上模8
下模9
电磁铁10。
具体实施方式
参见图5，图5为本实用新型四面无引脚半导体封装模具结构示意图。由图5可以看出，本实用新型涉及的四面无引脚半导体封装模具结构，所述模具结构包括引线框，引线框采用磁性材料制作，引线框包括基岛1和引脚2，引线框上设置有芯片5和金属线6，所述设置有芯片5和金属线6的引线框放置于一上模8与一下模9之间，下模9上连有电磁铁10。
所述模具结构的制作包括以下工艺过程：
步骤一、取一磁性材料基板并在其表面进行化学蚀刻及表面电镀，在磁性材料基板形成基岛1、引脚2和半蚀刻连筋4，完成引线框的生产，如图3。所述磁性材料基板用铁、铁合金等磁性金属材料制作，或为铁合金与铜的复合材料制作。
步骤二、将步骤一制作完成的引线框进行装片打线，如图4；
步骤三、将完成装片打线后的引线框放置于一上模8与一下模9之间，下模9连有电磁铁10，当引线框放置到指定位置后，打开电磁铁10的开关，下模9即紧密吸附住引线框，如图5，此时再进行合模注塑。待塑封料固化后，即完成了传统的包封工序。
本实用新型还可以在所述上模8上施加有与所述下模9上的电磁铁10极性相反的另一电磁铁（图中未示出），以避免上模上带有与下模9上极性相反的极性。
本实用新型所述磁性材料为铁或铁合金；或为所述磁性材料为铁与铜的复合材料；或为铁合金与铜的复合材料。

Claims (3)

1.一种四面无引脚半导体封装模具结构，其特征在于：所述模具结构包括引线框，引线框采用磁性材料制作，引线框包括基岛（1）和引脚（2），引线框上设置有芯片（5）和金属线（6），所述设置有芯片（5）和金属线（6）的引线框放置于一上模（8）与一下模（9）之间，下模（9）连有电磁铁（10）。
2.根据权利要求1所述的一种四面无引脚半导体封装模具结构，其特征在于：在所述上模（8）上施加有与所述下模（9）上的电磁铁（10）极性相反的另一电磁铁。
3.根据权利要求1或2所述的一种四面无引脚半导体封装模具结构，其特征在于：所述磁性材料为铁或铁合金。
CN 201120201239 2011-06-15 2011-06-15 四面无引脚半导体封装模具结构 Expired - Lifetime CN202120882U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231366A (zh) * 2011-06-15 2011-11-02 江苏长电科技股份有限公司 四面无引脚半导体封装方法及其封装模具结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102231366A (zh) * 2011-06-15 2011-11-02 江苏长电科技股份有限公司 四面无引脚半导体封装方法及其封装模具结构

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