CN201917897U - Circuit for realizing access of central processor to external memory device - Google Patents
Circuit for realizing access of central processor to external memory device Download PDFInfo
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- CN201917897U CN201917897U CN2010206372274U CN201020637227U CN201917897U CN 201917897 U CN201917897 U CN 201917897U CN 2010206372274 U CN2010206372274 U CN 2010206372274U CN 201020637227 U CN201020637227 U CN 201020637227U CN 201917897 U CN201917897 U CN 201917897U
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Abstract
The utility model relates to a circuit for realizing access of a central processor to an external memory device. The circuit comprises a central processor, a data flip latch and an external memory device, wherein the central processor comprises a M-bit data port and an N-bit latch control port; the data flip latch comprises an N*M-bit data input port, an N*M-bit data output port, an N-bit latch enabling port and an N-bit output enabling port, the N*M-bit data input port are equally divided into N groups of data input ports, each group of data input ports corresponds to the M-bit data port of the central processor one by one, the N-bit latch enabling port corresponds to the N-bit latch control port of the central processor one by one, and the N-bit output enabling port is set to be an eternally-valid state; and the external memory device comprises an N*M-bit address bus and an M-bit data bus, the N*M-bit address bus corresponds to the N*M-bit data output port of the data flip latch one by one, and the M-bit data bus corresponds to the M-bit data port of the central processor one by one. Due to adoption of the circuit, the addressing space of the central processor can be effectively expanded.
Description
Technical field
The utility model relates to electronic circuit field, relates in particular to a kind of realization circuit of central processing unit visit External memory equipment.
Background technology
In a lot of flush type circuit designs, all relate to central processing unit External memory equipment is conducted interviews.Under many circumstances, central processing unit does not have independently address bus and data bus, only have limited several FPDP, and the figure place of the address bus of the External memory equipment of using always now is higher than the figure place of the FPDP of central processing unit, for example: the quantity of the FPDP of central processing unit is less than 16, and External memory equipment has 16 bit address buses.
In this case, during central processing unit visit External memory equipment, the addressing space of central processing unit is restricted, and has reduced the memory capacity and the utilization factor of External memory equipment to a great extent.
The utility model content
The utility model provides a kind of realization circuit of central processing unit visit External memory equipment, in order to realize expanding effectively the addressing space of central processing unit, improves the memory capacity and the utilization factor of External memory equipment.
The utility model provides a kind of realization circuit of central processing unit visit External memory equipment, comprising:
Central processing unit comprises that M bit data port and N position latch control port, and wherein, M is the natural number more than or equal to 1, and N is the natural number more than or equal to 2;
Data latches, comprise N*M bit data input port, N*M bit data output port, N position latch enable port and N position output enable port, described N*M bit data input port is divided into N group data-in port, the M bit data interface of every group of data-in port and described central processing unit connects one to one, the N position of described N position latch enable port and described central processing unit is latched control port and is connected one to one, and described N position output enable port is set to permanent effectively state;
External memory equipment, comprise N*M bit address bus and M bit data bus, the N*M bit data output port of described N*M bit address bus and described data latches connects one to one, and the M bit data port of described M bit data bus and described central processing unit connects one to one.
In this real utility model, central processing unit is address bus and data bus with M bit data port time-sharing multiplex, the address space of the addressable External memory equipment of M bit data port of central processing unit is the N*M position, solved of the restriction of the less central processing unit chip of FPDP in the prior art to outside storage device access space, expand the addressing space of central processing unit, improved the memory capacity and the utilization factor of External memory equipment.
Description of drawings
Fig. 1 is the electrical block diagram of realization circuit first embodiment of the utility model central processing unit visit External memory equipment;
Fig. 2 is the electrical block diagram of realization circuit second embodiment of the utility model central processing unit visit External memory equipment.
Embodiment
The utility model will be further described below in conjunction with specification drawings and specific embodiments.
Realization circuit first embodiment of central processing unit visit External memory equipment
As shown in Figure 1, the electrical block diagram for the utility model central processing unit is visited realization circuit first embodiment of External memory equipment can comprise central processing unit 11, data latches 12 and External memory equipment 13.
The principle of work of data latches 12 is: N*M bit data output port also is divided into N group data-out port, 1 group of data-out port is corresponding with 1 group of data-in port, 1 latch enable port and 1 group of data-in port of 1 output enable port controlling and with 1 group of data-out port, when 1 latch enable port and 1 output enable port all effectively the time, 1 group of controlled data-out port will be organized the data that data-in port the received output of data-out port correspondence and go, and when this latch enable signal lost efficacy, this group data-out port can also keep the data exported.
In the present embodiment, supposing that central processing unit 11 is divided into the address of addressing from a high position to the low level is divided into N section: addr[N], addr[N-1] ..., addr[1], every section comprises the M position.The control port that latchs of central processing unit 11 is LC[N], LC[N-1] ..., LC[1].The latch enable port of data latches 12 is LE[N], LE[N-1] ..., LE[1].The output enable port of data latches 12 is OE[N], OE[N-1] ..., OE[1].The N of data latches 12 group data-in port is Ip[N], Ip[N-1] ..., Ip[1].The N of data latches 12 group data-out port is Op[N], Op[N-1] ..., Op[1].Latch enable port LE[N] and output enable port OE[N] control Ip[N] and Op[N], latch enable port LE[N-1] and output enable port OE[N-1] control Ip[N-1] and Op[N-1], by that analogy, latch enable port LE[1] and output enable port OE[1] control Ip[1] and Op[1].In the present embodiment, the output enable port OE[N of data latches 12], OE[N-1] ..., OE[1] be set to permanent effectively, for example: output enable port OE[N], OE[N-1] ..., OE[1] be effective during ground connection.
The course of work of circuit shown in Figure 1 is as follows:
Step a: central processing unit 11 will latch control port LC[N] be set to effectively, the latch enable port of data latches 12 is LE[N] be set to effectively;
Step b: central processing unit 11 M bit data ports are set to output port, and with addr[N] send on this M bit data port.At this moment, the Ip[N of data latches] and Op[N] addr[N will occur];
Step c: central processing unit 11 will latch control port LC[N] be set to invalid.Since the data latching effect of data latches 12, the Op[N of data latches] will export addr[N];
Steps d: central processing unit 11 will latch control port LC[N-1] be set to effectively, the latch enable port of data latches 12 is LE[N-1] be set to effectively;
Step e: central processing unit 11 is with addr[N-1] send on the M bit data port.At this moment, the Ip[N-1 of data latches] and Op[N-1] addr[N-1 will occur];
Step f: central processing unit will latch control port LC[N-1] be set to invalid.Since the data latching effect of data latches 12, the Op[N-1 of data latches] will export addr[N-1];
By that analogy, carry out following steps:
Step g: central processing unit 11 will latch control port LC[1] be set to effectively, the latch enable port of data latches 12 is LE[1] be set to effectively;
Step h: central processing unit 11 is with addr[1] send on the M bit data port.At this moment, the Ip[1 of data latches] and Op[1] addr[1 will occur];
Step I: central processing unit 11 will latch control port LC[1] be set to invalid.Since the data latching effect of data latches 12, the Op[1 of data latches 12] will export addr[1];
Step j: central processing unit 11 is if the External memory equipment operation is read in execution, and then M bit data port is set to input port, and the M bit data port of central processing unit 11 can be read the data of External memory equipment 13 appropriate address; Central processing unit 11 is if the External memory equipment operation is write in execution, and then the data that will write earlier are sent on the M bit data port, and the M bit data port of central processing unit 11 promptly can write data the appropriate address of External memory equipment 13.
Above step has been finished the read or write of M bit data, if continue the read-write of next M bit data, then re-executes step a-j.
In the present embodiment, central processing unit is address bus and data bus with M bit data port time-sharing multiplex, the address space of the addressable External memory equipment of M bit data port of central processing unit is the N*M position, solved of the restriction of the less central processing unit chip of FPDP in the prior art to outside storage device access space, expand the addressing space of central processing unit, improved the memory capacity and the utilization factor of External memory equipment.
Realization circuit second embodiment of central processing unit visit External memory equipment
As shown in Figure 2, be the electrical block diagram of realization circuit second embodiment of the utility model central processing unit visit External memory equipment, be with the difference of a last embodiment, in the present embodiment, N=2, M=8, P=2.
In addition, in the present embodiment, External memory equipment 13 can be read-write memory, central processing unit 11 can also comprise read port R and write port W, External memory equipment 13 can also comprise read port R and write port W, the read port of central processing unit is connected with the read port of External memory equipment, and the write port of central processing unit is connected with the write port of External memory equipment.Alternatively, External memory equipment 13 can also be ROM (read-only memory), and central processing unit 11 can also include only read port R, and External memory equipment 13 can also include only read port R; External memory equipment 13 can also be write only memory, and central processing unit 11 can also include only write port W, and External memory equipment 13 can also include only write port W.
In addition, when central processing unit need carry out data interaction with a plurality of External memory equipments 13, central processing unit 11 comprises that also sheet selects port CS, and External memory equipment 13 comprises that also sheet selects port CS, and the sheet of central processing unit 11 selects port CS to select port to be connected CS with the sheet of External memory equipment 13.
The principle of work of circuit shown in Figure 2 is as follows:
Step a: central processing unit 11 is with latch control signal LC[2] be set to useful signal;
Step b: central processing unit 11 8 bit data ports are set to output port, and the most-significant byte address that will visit is sent on this 8 bit data port.At this moment, the most-significant byte address will appear in the most-significant byte output port of data latches 12;
Step c: central processing unit 11 is with latch control signal LC[2] be set to invalid signals.Because the data latching effect of data latches, the most-significant byte address will appear in the most-significant byte output port of data latches 12;
Steps d: central processing unit 11 is with latch control signal LC[1] be set to useful signal;
Step e: central processing unit 11 sends to the least-significant byte address that will visit on the 8 bit data ports.At this moment, the least-significant byte address signal will appear in the least-significant byte output port of data latches 12;
Step f: central processing unit 11 is with latch control signal LC[1] be set to invalid signals.Because the data latching effect of data latches, the least-significant byte address will appear in the least-significant byte output port of data latches 12;
Step g: the chip selection signal CS of central processing unit 11 External memory equipments 13 is set to effectively;
Step h: central processing unit 11 is read the External memory equipment operation if carry out, then 8 bit data ports are set to input port, and read port R is set to effectively, and at this moment, 8 bit data ports of central processing unit 11 can be read the data of External memory equipment 13 appropriate address; Central processing unit 11 is if the External memory equipment operation is write in execution, and then the data that will write earlier are sent on the 8 bit data ports, and write port W is set to effectively subsequently.
Step I: it is invalid that central processing unit read port R or write port W are set to;
Step j; It is invalid that the central processing unit sheet selects port CS to be set to;
Above step has been finished the read or write of a byte (promptly 8) data, if continue the read-write of next byte, then re-executes step a-j.
In the present embodiment, central processing unit is address bus and data bus with 8 bit data port time-sharing multiplexs, the address space of the addressable External memory equipment of 8 bit data ports of central processing unit is 16, solved of the restriction of the less central processing unit chip of FPDP in the prior art to outside storage device access space, expand the addressing space of central processing unit, improved the memory capacity and the utilization factor of External memory equipment.
It should be noted that at last: above embodiment is only unrestricted in order to the explanation the technical solution of the utility model, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement the technical solution of the utility model, and not break away from the spirit and scope of technical solutions of the utility model.
Claims (4)
1. the realization circuit of a central processing unit visit External memory equipment is characterized in that, comprising:
Central processing unit comprises that M bit data port and N position latch control port, and wherein, M is the natural number more than or equal to 1, and N is the natural number more than or equal to 2;
Data latches, comprise N*M bit data input port, N*M bit data output port, N position latch enable port and N position output enable port, described N*M bit data input port is divided into N group data-in port, the M bit data interface of every group of data-in port and described central processing unit connects one to one, the N position of described N position latch enable port and described central processing unit is latched control port and is connected one to one, and described N position output enable port is set to permanent effectively state;
External memory equipment, comprise N*M bit address bus and M bit data bus, the N*M bit data output port of described N*M bit address bus and described data latches connects one to one, and the M bit data port of described M bit data bus and described central processing unit connects one to one.
2. circuit according to claim 1 is characterized in that, N=2, M=8.
3. circuit according to claim 1 and 2, it is characterized in that, described central processing unit also comprises read port and/or write port, described External memory equipment also comprises read port and/or write port, the read port of described central processing unit is connected with the read port of described External memory equipment, and the write port of described central processing unit is connected with the write port of described External memory equipment.
4. circuit according to claim 1 and 2 is characterized in that, described central processing unit comprises that also sheet selects port, and described External memory equipment comprises that also sheet selects port, and the sheet of described central processing unit selects port to select port to be connected with the sheet of described External memory equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206372274U CN201917897U (en) | 2010-11-26 | 2010-11-26 | Circuit for realizing access of central processor to external memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206372274U CN201917897U (en) | 2010-11-26 | 2010-11-26 | Circuit for realizing access of central processor to external memory device |
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| Publication Number | Publication Date |
|---|---|
| CN201917897U true CN201917897U (en) | 2011-08-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206372274U Expired - Lifetime CN201917897U (en) | 2010-11-26 | 2010-11-26 | Circuit for realizing access of central processor to external memory device |
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| Country | Link |
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| CN (1) | CN201917897U (en) |
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2010
- 2010-11-26 CN CN2010206372274U patent/CN201917897U/en not_active Expired - Lifetime
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Granted publication date: 20110803 |