CN201797518U - Device for realizing cascade of third-generation mobile communication access network digital optical transceivers - Google Patents
Device for realizing cascade of third-generation mobile communication access network digital optical transceivers Download PDFInfo
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- CN201797518U CN201797518U CN2009202302547U CN200920230254U CN201797518U CN 201797518 U CN201797518 U CN 201797518U CN 2009202302547 U CN2009202302547 U CN 2009202302547U CN 200920230254 U CN200920230254 U CN 200920230254U CN 201797518 U CN201797518 U CN 201797518U
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Abstract
The utility model relates to a device for realizing cascade of third-generation mobile communication access network digital optical transceivers. A front interface and a rear interface of the device are both lasers, a data storage and common public radio interface (CPRI) protocol resolution processing unit adopts a field programmable gate array (FPGA) module controlled by an ARM module, and the FPGA module includes a first serial/parallel conversion module, a CPRI protocol resolution module, a first parallel/serial conversion module, a CPRI protocol framing module, a double-port random memory (DPRAM) data cache module, a synchronous detection module and a data synthesis module. The FPGA module realizes merging upstream data of two channels, an upstream 10ms data frame header of a next-level remote end is adopted as reference, current-level upstream data is cached by an internal DPRAM of one FPGA, alignment of two levels of upstream 10ms data frame headers is realized by adjusting output time of the DPRAM, and merging of the upstream data of two channels is realized by aid of logic addition, thereby a normal upstream data channel is provided for the next-level remote end in cascade, and the multiple remote-end cascading function is realized.
Description
Technical field
The utility model relates to the device that a kind of 3G mobile communication Access Network Digital Optical Terminal cascade realizes, belongs to optical-fiber network digital communication technology field, particularly optical-fiber network digital communication cascade unit.
Background technology
Along with increase at full speed and the skyscraper of mobile subscriber in the city are more and more, traffic density and covering require also constantly to rise, and these architectural scale are big, quality good, and mobile telephone signal is had very strong shielding action.Under environment such as the bottom of building, market place builet below the ground, underground parking, a little less than the mobile communication signal, mobile phone can't normally use, and has formed the blind area and the shadow region of mobile communication; At intermediate floor, because overlapping from different base station signal on every side produces ping-pong, mobile phone frequently switches, even call drop, has had a strong impact on the normal use of mobile phone; At the high level of building, owing to be subjected to the limitation in height of antenna for base station, can't normally cover, also be the blind area of mobile communication.If adopt the solution of traditional cable+trunk amplifier, need to lay a large amount of cables, with high costs, need to increase the power loss that the trunk amplifier compensating cable brings simultaneously, when further increasing cost, also increase the interference of base station upward signal, influenced the base station coverage effect, reduced the base station covering radius.
And since optical transceiver to have loss little, with low cost, can not introduce new advantages such as interference, be particularly suitable for indoor covering system, one end (near-end) cooperates radio-frequency module to finish obtaining and sending base station signal, the other end (far-end) cooperates radio-frequency module to finish obtaining and sending mobile phone signal, data between near-end and the far-end transmit and adopt CPRI (The Common Public Radio Interface, common public radio interface) standard light interface, two ends cooperate realizes that base station signal zooms out covering to indoor hot spot region, solve the difficult problem of the indoor covering of 3-G (Generation Three mobile communication system), have good social benefit and economic benefit.
Star-like, chain, multiple connected mode such as ring-like can be arranged, to satisfy the demand of network agile networking, scalable application scenario between near-end and the far-end.For long narrow bottom lines such as railway, highway, coastlines, can pass through the cascade between far-end, and adopt directional antenna to cover, far-end cascade schematic diagram is as shown in Figure 1.The difficult point that the far-end cascade realizes is in up link, far-ends at different levels send to upper level or near-end after the upstream data of at the corresponding levels and next stage need being merged again, traditional method is to use AXC (Antenna Carrier, antenna carrier) and the C﹠amp in 4 high depth memory cell difference buffer memory corresponding levels and the next stage up link; M (Control and Management, control and management) data, according to the data in 4 memory cell of CPRI agreement timesharing transmission, the resource that this method needs is many then, and the sequencing control complexity is unfavorable for system's miniaturization, and then increases product cost pressure.
Summary of the invention
The utility model purpose is in order to overcome the defective that conventional method exists, the device that a kind of resource is few, realization is simple, stable 3G mobile communication Access Network Digital Optical Terminal cascade high, that help system's miniaturization realizes to be provided.
The technical solution of the utility model: the device that 3G mobile communication Access Network Digital Optical Terminal cascade of the present utility model realizes comprises front end interface, storage and CPRI protocol analysis processing unit, back end interface successively, its front end interface and back end interface are lasers, storage and CPRI protocol analysis processing unit adopt the FPGA module, by the ARM module to the FPGA module controls; First laser is responsible for the reception of down link data and the transmission of uplink data, to finish communicating by letter of far-end at the corresponding levels and near-end or upper level far-end; Comprise in the FPGA module: CPRI protocol analysis processing unit, synchronous detection module, data synthesis module, DPRAM data cache module, CPRI protocol groups frame module; Be specially:
(1) first laser that is connected with near-end or upper level far-end communicates to connect by the first serial/parallel modular converter and CPRI protocol analysis processing unit;
(2) output of CPRI protocol analysis processing unit is connected with second laser by the first parallel/serial modular converter, and second laser and next stage far-end communicate to connect;
The output of (3) second lasers is connected with synchronous detection module by the second serial/parallel modular converter;
(4) output of synchronous detection module is connected with the DPRAM data cache module with the data synthesis module respectively;
(5) output of data synthesis module is connected with first laser by the second parallel/serial modular converter;
(6) ARM module and CPRI protocol groups frame module communicate to connect; The output of CPRI protocol groups frame module is connected with the DPRAM data cache module; The DPRAM data cache module is connected with the data synthesis module;
(7) input of CPRI protocol groups frame module also is connected with far-end AXC data wires at different levels.
Advantage of the present utility model: the resource that kernel processor chip FPGA uses is few, low in energy consumption, and stability is high, and is beneficial to realization and debugging.
Description of drawings
Fig. 1 is the device block diagram that the cascade of 3G mobile communication Access Network Digital Optical Terminal realizes.
Fig. 2 is the key step flow chart that the utility model adopted.
Embodiment
The utility model is with DSP (Digital Signal Processing, Digital Signal Processing) technology is a core, this device utilizes FPGA (Field Programmable Gate Array, field programmable gate array) merging of realization two-way upstream data, be benchmark wherein with the up 10ms data of next stage far-end frame head, use inner DPRAM (the Dual Port RAM of 1 FPGA, dual-port random access memory) buffer memory upstream data at the corresponding levels, output time by regulating DPRAM is to realize the alignment of the up 10ms data of two-stage frame head, utilize the merging of the operation method realization two-way upstream data of union at last, thereby, realize the multi-stage far-end cascade function for the next stage far-end in the cascade provides normal upstream data passage.
The invention will be further described below in conjunction with accompanying drawing.
In device shown in Figure 1, front end interface and back end interface are lasers, and storage and CPRI protocol analysis processing unit adopt the FPGA module, by the ARM module to the FPGA module controls; First laser is responsible for the reception of down link data and the transmission of uplink data, to finish communicating by letter of far-end at the corresponding levels and near-end or upper level far-end; Comprise in the FPGA module:
1) first, second serial/parallel modular converter is responsible for finishing converting the high-speed-differential serial signal to parallel data, and finishes the 8B/10B decoding;
2) CPRI protocol analysis module is responsible for receiving the data from near-end or upper level far-end, extracts at the corresponding levels required AXC and C﹠amp; The M data are transmitted to the next stage far-end with descending complete CPRI Frame simultaneously;
3) first, second parallel/serial modular converter is responsible for finishing converting parallel data to the high-speed-differential serial signal, and finishes the 8B/10B coding;
4) CPRI protocol groups frame module is responsible for AXC at the corresponding levels and C﹠amp; The M data become up 10ms frame 1 at the corresponding levels according to the CPRI protocol groups, send to the DPRAM data cache module;
5) DPRAM data cache module, be responsible for buffer memory up 10ms frame 1 at the corresponding levels, to adjust upstream data time delay at the corresponding levels according to the next stage upstream data, when arriving, the up 10ms data of next stage frame head reads up 10ms data at the corresponding levels from DPRAM, by the alignment of register fine setting with realization two-stage upstream data, the data of this module output send to the data synthesis module then;
6) synchronous detection module be responsible for to detect the up 10ms data of next stage frame head, export to the DPRAM data cache module trigger DPRAM read enable, simultaneously the up 10ms Frame 1 of next stage is sent to the data synthesis module;
7) data synthesis module is responsible for up 10ms Frame 2 of the corresponding levels and the up 10ms Frame 2 of next stage are carried out the data merging, and concrete grammar is with other far-end AXC at different levels and C﹠amp in the up 10ms Frame 2 of the corresponding levels; The whole zero clearings of M data only keep timing controlled information and AXC at the corresponding levels and C﹠amp in the CPRI agreement; The M data correspondingly, will be used to send AXC at the corresponding levels and C﹠amp in the up 10ms Frame 2 of next stage; The whole zero clearings of the data of M, it is synthetic then two paths of data serial addition in time can be finished data, obtains a up 10ms Frame and sends to near-end or upper level far-end;
ARM field programmable gate array module is responsible for from C﹠amp; The M passage receives near-end and disposes the control information of getting off, and gives the FPGA module by register configuration;
Second laser is responsible for the transmission of down link data and the reception of uplink data, to finish communicating by letter of far-end at the corresponding levels and next stage far-end.
In device shown in Figure 1, far-end C﹠amp at different levels; The M data are in the HDLC passage timesharing transmission of CPRI 10ms Frame, for line link, because the 10ms Frame adopts broadcast mode to transmit, so do not need descending C﹠amp; The M data dispatch.But for up link, to the up C﹠amp of two-way; When the M data are synthesized, need the C﹠amp that adopts scheduling mechanism to avoid two-way to upload simultaneously; The M data produce conflict.Concrete method is to detect the corresponding levels in real time whether to need to send up C﹠amp; The M data are if having then the preferential up C﹠amp at the corresponding levels of transmission; M data, and the up C﹠amp of buffer memory next stage; The M data are up to the up C﹠amp of the corresponding levels; The M data send the HDLC passage that finishes and are in idle condition, resend the up C﹠amp of next stage again; The M data.
The data synthesis module of FPGA is responsible for up 10ms Frame 2 of the corresponding levels and the up 10ms Frame 2 of next stage are carried out the data merging, and concrete grammar is with other far-end AXC at different levels and C﹠amp in the up 10ms Frame 2 of the corresponding levels; The whole zero clearings of M data only keep timing controlled information and AXC at the corresponding levels and C﹠amp in the CPRI agreement; The M data correspondingly, will be used to send AXC at the corresponding levels and C﹠amp in the up 10ms Frame 2 of next stage; The whole zero clearings of the data of M, it is synthetic then two paths of data serial addition in time can be finished data, obtains a up 10ms Frame and sends to near-end or upper level far-end.
Before data are synthetic, need the distance of two up 10ms data frame heads is judged, need to use FPGA built-in system work clock 122.88MHz signal to measure as benchmark.FPGA receives from the next stage upstream data, the counter that is provided with in the rising edge startup FPGA with next stage 10ms data frame head begins counting, FPGA also receives upstream data at the corresponding levels simultaneously, stop rolling counters forward with the rising edge of 10ms data frame head at the corresponding levels, the quantity of the 122.88MHz clock of being added up in this hour counter be exactly between two frame heads apart from d.
Determine two frame heads apart from behind the d, FPGA is according to the threshold value of determining of memory depth at the corresponding levels and the subordinate's data cache module, as d during less than threshold value, show that the distance between two frame heads is less, the DPRAM data cache module is had the ability the corresponding levels complete reception of up 10ms Frame and is adjusted to and the up 10ms data frame alignment of next stage.As d during greater than threshold value, show that the distance between two frame heads is far away, the DPRAM data cache module can't and be adjusted to and the up 10ms data frame alignment of next stage the corresponding levels complete reception of up 10ms Frame, abandons the up 10ms Frame of next stage the most at last and only sends up 10ms Frame at the corresponding levels.
In the cascade of reality, if the next stage far-end can normally start, and the fiber lengths that links to each other with the corresponding levels is in reasonable range, inevitable very little between the two up 10ms Frames then apart from d, when the value of d has surpassed threshold value more greatly, illustrating that next stage also is not activated finishes, this moment its up AXC and C﹠amp; The M data are nonsensical, therefore can not transmit the next stage upstream data.
The utility model utilizes FPGA to realize the merging of two-way upstream data, be benchmark wherein with the up 10ms data of next stage far-end frame head, use inner DPRAM (the Dual Port RAM of 1 FPGA, dual-port random access memory) buffer memory upstream data at the corresponding levels, output time by regulating DPRAM is to realize the alignment of the up 10ms data of two-stage frame head, utilize the merging of the operation method realization two-way upstream data of union at last, thereby, realize the multi-stage far-end cascade function for the next stage far-end in the cascade provides normal upstream data passage.
Fig. 2 is the key step flow chart that the utility model adopted: the realization of the utility model 3G mobile communication Access Network Digital Optical Terminal cascade unit may further comprise the steps:
(1) first laser is responsible for the reception of down link data and the transmission of uplink data, to finish communicating by letter of far-end at the corresponding levels and near-end or upper level far-end.
(2) first of the FPGA serial/parallel modular converter is responsible for finishing and is converted the high-speed-differential serial signal to parallel data, and finishes the 8B/10B decoding.
(3) the CPRI protocol analysis module of FPGA is responsible for receiving the data from near-end or upper level far-end, extracts at the corresponding levels required AXC and C﹠amp; The M data are transmitted to the next stage far-end with descending complete CPRI Frame simultaneously.
(4) second of the FPGA parallel/serial modular converter is responsible for finishing and is converted parallel data to the high-speed-differential serial signal, and finishes the 8B/10B coding.
(5) second lasers are responsible for the forward downlink data, to finish communicating by letter of near-end or upper level far-end and next stage far-end.
(6) second lasers are responsible for the reception of uplink data simultaneously, to finish communicating by letter of next stage far-end and near-end or upper level far-end.
(7) second of the FPGA serial/parallel modular converter is responsible for finishing and is converted the high-speed-differential serial signal to parallel data, and finishes the 8B/10B decoding.
(8) the 2nd CPRI protocol analysis module of FPGA is responsible for receiving the data from the next stage far-end, extract up 10ms frame head and export to the DPRAM cache module of FPGA, with this module dateout of setting out, simultaneously the 10ms frame 2 of uplink complete is exported to the data synthesis module of FPGA.
(9) the ARM module is responsible for from C﹠amp; The M passage receives near-end and disposes the control information of getting off, and gives the FPGA module by register configuration.
(10) the CPRI protocol groups frame module of FPGA is responsible for AXC at the corresponding levels and C﹠amp; The M data become up 10ms frame 1 at the corresponding levels according to the CPRI protocol groups, send to the DPRAM data cache module.
(11) the DPRAM data cache module of FPGA is responsible for buffer memory up 10ms frame 1 at the corresponding levels, to adjust upstream data time delay at the corresponding levels according to the next stage upstream data, when arriving, the up 10ms data of next stage frame head reads up 10ms data at the corresponding levels from DPRAM, by the alignment of register fine setting with realization two-stage upstream data, the data of this module output send to the data synthesis module then.
(12) the data synthesis module of FPGA is responsible for up 10ms Frame 2 of the corresponding levels and the up 10ms Frame 2 of next stage are carried out the data merging, and concrete grammar is with other far-end AXC at different levels and C﹠amp in the up 10ms Frame 2 of the corresponding levels; The whole zero clearings of M data only keep timing controlled information and AXC at the corresponding levels and C﹠amp in the CPRI agreement; The M data correspondingly, will be used to send AXC at the corresponding levels and C﹠amp in the up 10ms Frame 2 of next stage; The whole zero clearings of the data of M, it is synthetic then two paths of data serial addition in time can be finished data, obtains a up 10ms Frame and sends to near-end or upper level far-end.
(13) first of the FPGA parallel/serial modular converter is responsible for finishing and is converted parallel data to the high-speed-differential serial signal, and finishes the 8B/10B coding.
(14) first lasers are responsible for sending uplink data, to finish communicating by letter of far-end at the corresponding levels and near-end or upper level far-end.
Above-mentioned steps (1) repeats to step (14), just can realize the multi-stage cascade of 3G mobile communication Access Network Digital Optical Terminal.
Core of the present utility model is to utilize FPGA (Field Programmable Gate Array, field programmable gate array) as chip, combines with laser, ARM module to realize the multi-stage far-end cascade function.Therefore, every FPGA that utilizes is as chip, combines with laser, ARM module to realize the multi-stage far-end cascade function all belonging to protection range of the present utility model.
Claims (1)
1. the device realized of a 3G mobile communication Access Network Digital Optical Terminal cascade, comprise front end interface, storage and CPRI protocol analysis processing unit, back end interface successively, it is characterized in that: front end interface and back end interface are lasers, storage and CPRI protocol analysis processing unit adopt FPGA field programmable gate array module, by the ARM module to FPGA field programmable gate array module controls; Laser is responsible for the reception of down link data and the transmission of uplink data, to finish communicating by letter of far-end at the corresponding levels and near-end or upper level far-end; Comprise in the FPGA field programmable gate array module: CPRI protocol analysis processing unit, synchronous detection module, data synthesis module, DPRAM data cache module, CPRI protocol groups frame module; Be specially:
(1) first laser that is connected with near-end or upper level far-end communicates to connect by the first serial/parallel modular converter and CPRI protocol analysis processing unit;
(2) output of CPRI protocol analysis processing unit is connected with second laser by the first parallel/serial modular converter, and second laser and next stage far-end communicate to connect;
The output of (3) second lasers is connected with synchronous detection module by the second serial/parallel modular converter;
(4) output of synchronous detection module is connected with the DPRAM data cache module with the data synthesis module respectively;
(5) output of data synthesis module is connected with first laser by the second parallel/serial modular converter;
(6) ARM module and CPRI protocol groups frame module communicate to connect; The output of CPRI protocol groups frame module is connected with the DPRAM data cache module; The DPRAM data cache module is connected with the data synthesis module;
(7) input of CPRI protocol groups frame module also is connected with far-end AXC data wires at different levels.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104243941A (en) * | 2014-10-16 | 2014-12-24 | 成都思迈科技发展有限责任公司 | Video optical terminal system |
| CN109787740A (en) * | 2018-12-24 | 2019-05-21 | 北京诺亦腾科技有限公司 | Synchronous method, device, terminal device and the storage medium of sensing data |
| CN113517894A (en) * | 2021-07-14 | 2021-10-19 | 上海安路信息科技股份有限公司 | Serial-parallel conversion circuit |
-
2009
- 2009-11-24 CN CN2009202302547U patent/CN201797518U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104243941A (en) * | 2014-10-16 | 2014-12-24 | 成都思迈科技发展有限责任公司 | Video optical terminal system |
| CN109787740A (en) * | 2018-12-24 | 2019-05-21 | 北京诺亦腾科技有限公司 | Synchronous method, device, terminal device and the storage medium of sensing data |
| CN109787740B (en) * | 2018-12-24 | 2020-10-27 | 北京诺亦腾科技有限公司 | Sensor data synchronization method and device, terminal equipment and storage medium |
| CN113517894A (en) * | 2021-07-14 | 2021-10-19 | 上海安路信息科技股份有限公司 | Serial-parallel conversion circuit |
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