CN201540373U - 24 bit dual-channel synchronous data collector - Google Patents
24 bit dual-channel synchronous data collector Download PDFInfo
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- CN201540373U CN201540373U CN 200920244814 CN200920244814U CN201540373U CN 201540373 U CN201540373 U CN 201540373U CN 200920244814 CN200920244814 CN 200920244814 CN 200920244814 U CN200920244814 U CN 200920244814U CN 201540373 U CN201540373 U CN 201540373U
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- resistable filter
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Abstract
The utility model relates to a 24 bit dual-channel synchronous data collector, comprising two antialiasing filters. The two antialiasing filters are respectively connected with corresponding 24-bit A/D converter, the two 24-bit A/D converter are connected and both connected to a voltage reference module (5), and connected with the DSP controller (6) through the other output ends, the DSP controller (6) is connected with the USB-UART bridge (7), two signals are delivered to the 24-bit A/D converter through the antialiasing filter. The two A/D converter transmits the data editted by the DSP controller (6) by a USB interface through a USB-UART bridge (7) to an external machine. And the collector has features of simple structure and convenient use.
Description
Technical field
The utility model relates to a kind of data acquisition unit, particularly a kind of 24 binary channels synchronous data collection devices.
Background technology
Data acquisition unit is one of measurement links of most critical in the modern digital testing apparatus, can be divided into single-ended input and difference input according to the input pattern signal difference, can be divided into 8,12,16,24 etc. according to the resolution difference, be divided into isa bus, pci bus, usb bus etc. according to the interface mode difference, be divided into poll formula or synchronous mode sampling work mode according to the number difference of sampling holder or A/D.Different test requests is very different to the requirement of data collector, the many employings of electrical log instrument at present 12 or 16 AD, and it has been difficult to satisfy the requirement of modern high-resolution logging instrumentation to the resolution characteristic of feeble signal.
Summary of the invention
In order to overcome the defective of above-mentioned prior art, the purpose of this utility model is to provide a kind of 24 binary channels synchronous data collection devices, has characteristics simple in structure, easy to use.
In order to achieve the above object, the technical solution of the utility model is achieved in that a kind of 24 binary channels synchronous data collection devices, comprise first frequency overlapped-resistable filter 1 and second frequency overlapped-resistable filter 2, the signal output part of first frequency overlapped-resistable filter 1 and second frequency overlapped-resistable filter 2 links to each other with the input end of the one 24 A/D converter 3 and the 2 24 A/D converter 4 respectively, the serial ports mode of operation selecting side ground connection of the one 24 A/D converter 3 and the 2 24 A/D converter 4, the reference voltage input terminal of the one 24 A/D converter 3 and the 2 24 A/D converter 4 all links to each other with the reference voltage output terminal mouth of voltage reference module 5, the digital output end of the 2 24 A/D converter 4 is connected with the digital input end of the one 24 A/D converter 3, the digital output end of the one 24 A/D converter 3 and the 2 24 A/D converter 4 links to each other with the input end of dsp controller 6, and the output terminal of dsp controller 6 links to each other with the input end of USB-UART bridge 7.
The utility model can accurately be measured faint sinusoidal signal amplitude of the two-way in 1Hz in the electrical log instrument～50kHz frequency range and phase differential, adopts USB interface can export the result easily.
Description of drawings
Accompanying drawing is a structure principle chart of the present utility model.
Embodiment
Below in conjunction with accompanying drawing structural principle of the present utility model and principle of work are described in detail.
With reference to accompanying drawing, a kind of 24 binary channels synchronous data collection devices, comprise first frequency overlapped-resistable filter 1 and second frequency overlapped-resistable filter 2, the signal output part of first frequency overlapped-resistable filter 1 and second frequency overlapped-resistable filter 2 links to each other with the input end of the one 24 A/D converter 3 and the 2 24 A/D converter 4 respectively, the serial ports mode of operation selecting side FORMAT ground connection of the one 24 A/D converter 3 and the 2 24 A/D converter 4, the reference voltage input terminal of the one 24 A/D converter 3 and the 2 24 A/D converter 4 all links to each other with the reference voltage output terminal mouth of voltage reference module 5, the digital output end DOUT of the 2 24 A/D converter 4 is connected with the digital input end DIN of the one 24 A/D converter 3, the numeral output DOUT end of the one 24 A/D converter 3 is connected to the DR0 end of dsp controller 6, / DRDY end is connected to the RFS0 end of dsp controller 6, the SCLK end is connected to the SCLK0 end of dsp controller 6, the SCLK end of the 2 24 A/D converter 4 also is connected to the SCLK0 end of dsp controller 6, and the output terminal of dsp controller 6 links to each other with the input end of USB-UART bridge 7.
Principle of work of the present utility model is: two-way simulating signal input AIN1 and AIN2 are connected to first frequency overlapped-resistable filter 1 and second frequency overlapped-resistable filter 2, two 2 rank Butterworth low-pass filters that frequency overlapped-resistable filter is made up of accurate difference output amplifier OPA1632, cutoff frequency 50kHz, its differential output signal is connected respectively to the one 24 A/D converter 3 and the 2 24 A/D converter 4, two A/D converters are 24 delta-sigma A/D converter ADS1271, adopt the 27MHz crystal oscillator to provide work clock and serial port clock for two A/D converters, the highest sampling rate 105kSPS of A/D, serial communication speed 27Mbps, the mode of operation of A/D can be set to fast mode by jumper wire device, high resolution mode and low-power consumption mode, two-way A/D adopts daisy chain to connect, synchronous working under the control of dsp controller 6, the serial ports mode of operation selecting side FORMAT ground connection of two A/D converters, be that mode of operation is set to 0, the serial line interface working method is SPI.The SPORT0 of dsp controller 6 is configured to the SPI hyperchannel and cushions mode of operation automatically, port number is set to 24, every passage 8 bit data, the last output 48 bit serial data of the daisy chain of the one 24 A/D converter 3 are transferred to dsp controller 6 by SPORT0, be assigned to 6 passages, 24 sampled result of two converters are transferred to dsp controller 6 backs and are divided into 3 16 words preservations respectively at send buffer, and the DSP program is reorganized into two 16 words with 3 16 words and preserves with complement form.Voltage reference 5 provides reference voltage base for two A/D converters, and two A/D converter sampled datas carry out after the formatting through USB-UART bridge 7 sampled data being transferred to external mechanical by USB interface through dsp controllers 6.
Claims (1)
1. one kind 24 binary channels synchronous data collection devices, it is characterized in that, comprise first frequency overlapped-resistable filter (1) and second frequency overlapped-resistable filter (2), the signal output part of first frequency overlapped-resistable filter (1) and second frequency overlapped-resistable filter (2) links to each other with the input end of the one 24 A/D converter (3) and the 2 24 A/D converter (4) respectively, the serial ports mode of operation selecting side ground connection of the one 24 A/D converter (3) and the 2 24 A/D converter (4), the reference voltage input terminal of the one 24 A/D converter (3) and the 2 24 A/D converter (4) all links to each other with the reference voltage output terminal mouth of voltage reference module (5), the digital output end of the 2 24 A/D converter (4) is connected with the digital input end of the one 24 A/D converter (3), the digital output end of the one 24 A/D converter (3) and the 2 24 A/D converter (4) links to each other with the input end of dsp controller (6), and the output terminal of dsp controller (6) links to each other with the input end of USB-UART bridge (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920244814 CN201540373U (en) | 2009-10-22 | 2009-10-22 | 24 bit dual-channel synchronous data collector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920244814 CN201540373U (en) | 2009-10-22 | 2009-10-22 | 24 bit dual-channel synchronous data collector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201540373U true CN201540373U (en) | 2010-08-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200920244814 Expired - Fee Related CN201540373U (en) | 2009-10-22 | 2009-10-22 | 24 bit dual-channel synchronous data collector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201540373U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102736549A (en) * | 2012-05-25 | 2012-10-17 | 青岛华特自动化设备有限公司 | 24-Bit acquisition module |
| CN103778760A (en) * | 2012-10-17 | 2014-05-07 | 成都龙冠科技实业有限公司 | Wireless data collector based on DSP and FPGA |
| CN114448456A (en) * | 2022-02-16 | 2022-05-06 | 山东胜业智控科技有限公司 | Double-channel data acquisition unit |
-
2009
- 2009-10-22 CN CN 200920244814 patent/CN201540373U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102736549A (en) * | 2012-05-25 | 2012-10-17 | 青岛华特自动化设备有限公司 | 24-Bit acquisition module |
| CN103778760A (en) * | 2012-10-17 | 2014-05-07 | 成都龙冠科技实业有限公司 | Wireless data collector based on DSP and FPGA |
| CN114448456A (en) * | 2022-02-16 | 2022-05-06 | 山东胜业智控科技有限公司 | Double-channel data acquisition unit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100804 Termination date: 20121022 |