CN201365192Y - High voltage and low voltage converting circuit - Google Patents

Abstract

The utility model discloses a high voltage and low voltage converting circuit, which belongs to the technical field of integrated circuit. The converting circuit comprises a reference current generating circuit, a low voltage generating circuit and an output voltage stabilizing circuit, wherein the reference current generating circuit generates reference current for the low voltage generating circuit, the low voltage generating circuit includes a parasitic PNP, a compensating resistance and low voltage MOS tubes, the parasitic PNP, the compensating resistance and the low voltage MOS tubes provide stable drive voltage for the output voltage stabilizing circuit, the drive voltage passes through a first current mirror, and outputs stable low voltage through a voltage stabilizing capacitor in the output voltage stabilizing circuit. The high voltage and low voltage converting circuit does not need to use Zener diodes, but utilizes standard elements of MOS tubes, triodes, resistances, capacitors and the like, does not require additional customizing, and reduces chip cost and debugging cost.

Description

A kind of level shifter circuit

Technical field

The utility model belongs to technical field of integrated circuits, relates in particular to a kind of level shifter circuit.

Background technology

Make the field at integrated circuit, up-to-date technology at first is applied to the production and the design of digit chip, adds resistance, the electric capacity that some analog chips need then in technology, and parasitic triode etc.But, the simulation process that the electronics foundries provides can not provide some devices that special analog circuit needs, wherein a kind of device is exactly a zener, and zener is widely used in the voltage-stabilizing system, especially is applied in the Switching Power Supply integrated circuit (IC) design that relates to from the high voltage to the low voltage transition.

If production technology provides zener, can realize the high-low pressure conversion at chip internal by mode shown in Figure 1.Wherein, I1 provides reference current by current source, input voltage is VDD, after the zener Z120 voltage stabilizing, through the current mirror output of forming by metal-oxide-semiconductor M101 and metal-oxide-semiconductor M102, output voltage V CC is approximately equal to the pressure drop of zener Z120, uses through can be used as the low-voltage module power supply after capacitor C 110 voltage stabilizings.But because zener is not a normal component, customizing this device needs the long period, and debugging cost is higher, so there is certain drawback.

The utility model content

The purpose of this utility model is to solve because the problem of using zener to bring in the level shifter circuit provides a kind of in standard foundries technology, does not need to use the voltage stabilizing zener and realizes circuit from high pressure to the low pressure translation function.

For achieving the above object, the utility model adopts following technical scheme: a kind of level shifter circuit comprises that reference current generating circuit, low pressure produce circuit and output voltage stabilizing circuit; Wherein, reference current generating circuit provides reference current for low pressure produces circuit; Described low pressure produces circuit and comprises parasitic PNP, compensating resistance and low pressure metal-oxide-semiconductor, and parasitic PNP, compensating resistance and low pressure metal-oxide-semiconductor provide stable driving voltage for output voltage stabilizing circuit; Described driving voltage passes through first current mirror, exports stable low pressure by electric capacity of voltage regulation in output voltage stabilizing circuit.

Preferably, described first current mirror comprises that low pressure produces the tenth NMOS pipe on the circuit and the 11 NMOS on the output voltage stabilizing circuit manages; Wherein, the grid and the drain electrode of the tenth NMOS pipe link together, and described reference current is imported its drain electrode; The drain electrode of the 11 NMOS pipe inserts input voltage, inserts described electric capacity of voltage regulation between source electrode and the ground; Low pressure produces circuit and comprises two low pressure metal-oxide-semiconductors, be respectively the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor, the two grid and drain electrode separately links together, and the source electrode of the 8th metal-oxide-semiconductor and the tenth NMOS pipe and the annexation of the 9th metal-oxide-semiconductor guarantee that the gate source voltage of the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is in the conducting state of the two; Be connected described compensating resistance, the collector electrode of parasitic PNP and base earth between the emitter of the 9th metal-oxide-semiconductor and parasitic PNP.

Preferably, described reference current generating circuit comprises second and third and four current mirrors, wherein, second current mirror comprises two measure-alike PMOS pipes (M201) and the 2nd PMOS pipe (M202), the source electrode of the two all inserts input voltage, grid is connected to each other, and the grid and the drain electrode of PMOS pipe (M201) link together; The 3rd current mirror comprises the 3rd NMOS pipe (M203) and the 4th NMOS pipe (M204), and the drain electrode of the two is electrically connected with the drain electrode of PMOS pipe (M201) and the drain electrode of the 2nd PMOS pipe (M202) respectively, and the grid of the two is connected to each other together; The drain electrode and the grid of the 4th NMOS pipe (M204) link together; The 4th current mirror comprises the 5th NMOS pipe (M205) and the 6th NMOS pipe (M206), the drain electrode of the two is electrically connected with the source electrode of the 3rd NMOS pipe (M203) and the source electrode of the 4th NMOS pipe (M204) respectively, the grid of the two is connected to each other together, the drain electrode and the grid of the 6th NMOS pipe (M206) link together, series resistor (R220) between the source electrode of the 6th NMOS pipe (M206) and the ground; Reference current generating circuit provides reference current by the 5th current mirror for low pressure produces circuit, the 5th current mirror comprises that described PMOS pipe (M201) and low pressure produce the 7th PMOS pipe (M207) on the circuit, the grid of the two links together, the source electrode of the 7th PMOS pipe (M207) inserts input voltage, and drain electrode is electrically connected with the drain electrode of described the tenth NMOS pipe (M210).

Preferably, produce increase load compensation circuit between the circuit at described output voltage stabilizing circuit and low pressure.

Preferably, described load compensation circuit comprises the 6th current mirror, and described the 6th current mirror comprises the 13 PMOS pipe and the 14 PMOS pipe, and the source electrode of the two all inserts input voltage, the grid of the two is connected to each other together, and the grid and the drain electrode of the 14 PMOS pipe link together; The drain electrode of the 13 PMOS pipe is electrically connected with the grid of the tenth NMOS pipe, the drain electrode of the 14 PMOS pipe is electrically connected with the drain electrode of 1 the 12 NMOS pipe, the grid of described the 12 NMOS pipe is electrically connected with the grid of the tenth NMOS pipe, and source electrode is electrically connected with the source electrode of the 11 NMOS pipe.

Preferably, described resistance is negative temperature coefficient type resistance; The material of described compensating resistance is identical with the material of resistance; Described the tenth NMOS pipe and the 11 NMOS pipe measure-alike.

Preferably, described PMOS pipe (M201), the 2nd PMOS pipe (M202), the 3rd NMOS pipe (M203) and the 4th NMOS pipe (M204), the 7th PMOS manage (M207), and the tenth NMOS manages (M210) and the 11 NMOS pipe (M211) passes through high-voltage MOS pipe; The 5th NMOS pipe (M205) and the 6th NMOS pipe (M206) are the low pressure metal-oxide-semiconductor.

The usefulness of controller described in the utility model is: on the one hand, level shifter circuit described in the utility model does not need to use Zener diode, all use normal component such as metal-oxide-semiconductor, triode, resistance and electric capacity, do not need additional customized, reduced chip cost and debugging cost; On the other hand, the part metal-oxide-semiconductor in the level shifter circuit is realized by low pressure process, has reduced the realization area significantly.

Description of drawings

Fig. 1 is the schematic diagram of existing level shifter circuit;

Fig. 2 is the schematic diagram of first embodiment of level shifter circuit described in the utility model;

Fig. 3 is the schematic diagram of second embodiment of level shifter circuit described in the utility model;

Fig. 4 is the schematic diagram of the 3rd embodiment of level shifter circuit described in the utility model.

Embodiment

A kind of level shifter circuit as shown in Figure 2 comprises that reference current generating circuit 21, low pressure produce circuit 22 and output voltage stabilizing circuit 23.Wherein, reference current generating circuit 21 provides reference current for low pressure produces circuit 22; Described low pressure produces circuit and comprises parasitic PNP, compensating resistance and low pressure metal-oxide-semiconductor, and parasitic PNP, compensating resistance and low pressure metal-oxide-semiconductor provide stable driving voltage for output voltage stabilizing circuit; Described driving voltage passes through by first current mirror, exports stable low pressure VCC by electric capacity of voltage regulation in output voltage stabilizing circuit.

First current mirror comprises that the tenth NMOS on the low pressure generation circuit 22 manages the 11 NMOS pipe M211 on M210 and the output voltage stabilizing circuit 23.Wherein, grid and the drain electrode of the tenth NMOS pipe M210 link together, and described reference current is imported its drain electrode; The drain electrode of the 11 NMOS pipe M211 inserts input voltage VDD, inserts electric capacity of voltage regulation C230 between source electrode and the ground, by electric capacity of voltage regulation C230 output low pressure VCC.

Reference current generating circuit 21 can adopt following structure:

Reference current generating circuit 21 comprises second and third and four current mirrors.Wherein, second current mirror comprises two measure-alike PMOS pipe M201 and the 2nd PMOS pipe M202, and the source electrode of the two all inserts input voltage VDD, and grid is connected to each other, and grid and the drain electrode of PMOS pipe M201 link together; The 3rd current mirror comprises the 3rd NMOS pipe M203 and the 4th NMOS pipe M204, the drain electrode of the two is electrically connected with the drain electrode of PMOS pipe M201 and the drain electrode M202 of the 2nd PMOS pipe respectively, the grid of the two is connected to each other, and drain electrode and the grid of the 4th NMOS pipe M204 link together; The 4th current mirror comprises the 5th NMOS pipe M205 and the 6th NMOS pipe M206, the drain electrode of the two is electrically connected with the source electrode of the 3rd NMOS pipe M203 and the source electrode of the 4th NMOS pipe M204 respectively, the grid of the two is connected to each other, drain electrode and the grid of the 6th NMOS pipe M206 link together, series resistor R220 between the source electrode of the 6th NMOS pipe M206 and the ground; Reference current generating circuit 21 provides reference current by the 5th current mirror for low pressure produces circuit 22, the 5th current mirror comprises that described PMOS pipe M201 and low pressure produce the 7th PMOS pipe M207 on the circuit 22, the grid of the two links together, and the source electrode of the 7th PMOS pipe M207 inserts input voltage.

If the 5th NMOS pipe M205 and the 6th NMOS pipe M206 size ratio are 1: n, then the 5th NMOS pipe M205 gate source voltage V _Gs205, the 6th NMOS pipe M206 gate source voltage V _Gs206, (resistance is R to flow through resistance R 220 ₂₂₀) electric current I between the pass be:

V _gs205＝V _gs206+I*R ₂₂₀ (1)

The computing formula of this electric current is as follows:

$I=\frac{2}{{\mathrm{\μ}}_n{C}_{\text{ox}}{(W/L)}_{206}}*\frac{1}{{R_{220}}^2}{(1-\frac{1}{\sqrt{n}})}^2---\left(2\right)$

Wherein, μ _nBe electron mobility, C _OxBe the gate oxide electric capacity of unit are, (W/L) ₂₀₆Be the channel width of the 6th NMOS pipe M206 and the ratio of channel length.From formula (2) as can be seen, electric current I is relevant with the temperature coefficient of resistance R 220, if select the resistance of negative temperature coefficient type to form resistance R 220, then electric current I is an electric current that rises along with the rising of temperature, and the variation of reference current and temperature are quadratic relation.Because reference current generating circuit 21 is a tertiary current mirror structure, therefore, electric current I will become the reference current I that flows into low pressure generation circuit 22.

Low pressure produces circuit 22 can comprise two low pressure metal-oxide-semiconductors, be respectively the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor, the two grid and drain electrode separately links together, the annexation of the source electrode of the 8th metal-oxide-semiconductor and the tenth NMOS pipe and the 9th metal-oxide-semiconductor guarantees that the gate source voltage of the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is in the conducting state of the two, be connected compensating resistance R221, the collector electrode of parasitic PNP and base earth between the emitter of the 9th metal-oxide-semiconductor and parasitic PNP.As shown in Figure 2, if adopt two low pressure NMOS pipes, then the drain electrode of the 8th metal-oxide-semiconductor M208 is connected with the source electrode of the tenth NMOS pipe M210, source electrode is connected with the drain electrode of the 9th metal-oxide-semiconductor M209, the source electrode of the 9th metal-oxide-semiconductor M209 is connected with the emitter of parasitic PNP240, can adopt two or a plurality of parasitic PNP herein, as shown in Figure 3, adopt two parasitic PNP, the base stage of parasitic PNP240 is connected with the emitter of parasitic PNP241, and the collector electrode of parasitic PNP241 and base earth, the voltage at promptly parasitic PNP two ends is the base stage of integral multiple and the voltage between the emitter.As shown in Figure 3, if the 8th metal-oxide-semiconductor M208 adopts the PMOS pipe, then the source electrode of the 8th metal-oxide-semiconductor M208 is connected with the source electrode of the tenth NMOS pipe M210, and drain electrode is connected with the drain electrode of the 9th metal-oxide-semiconductor M209.Equally, the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209 all can adopt the PMOS pipe.

As shown in Figure 2, the computing formula of the low pressure VCC of output voltage stabilizing circuit 23 outputs is as follows:

VCC＝V _be240+I*R ₂₂₁+V _gs208+V _gs209+V _gs210-V _gs211 (3)

Wherein, V _Be240, R ₂₂₁, V _Gs208, V _Gs209, V _Gs210, V _Gs211Be respectively the base stage of parasitic PNP240 and the voltage between the emitter, the resistance of compensating resistance R221, and, the gate source voltage of the 8th metal-oxide-semiconductor M208 to the 11 NMOS pipe M211.

Preceding two with formula (2) substitution formula (3) equal sign right side draw:

$V_{\mathrm{be}240}+I*R221=V_{\mathrm{be}240}+R221*\frac{2}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{(W/L)}_{206}}*\frac{1}{{R_{220}}^2}{(1-\frac{1}{\sqrt{n}})}^2---\left(4\right)$

According to formula (4) as can be known, if the material of compensating resistance R221 is identical with the material of resistance R 220, be the resistance of negative temperature coefficient type, then in the formula (4) back one be the positive temperature coefficient relation of first power with temperature, again because the base stage of parasitic PNP240 and the voltage V between the emitter _Be240Be negative temperature coefficient, as can be known, if select suitable compensating resistance R221 can offset parasitic PNP240 with variation of temperature, and keep formula (3) equal sign right side preceding two constant.

Two of the centres on formula (3) equal sign right side are expressed as follows again:

$V_{\mathrm{gs}208}+V_{\mathrm{gs}209}=(V_{\mathrm{ov}208}+V_{\mathrm{th}208})+(V_{\mathrm{ov}209}+V_{\mathrm{th}209})$

$=(\sqrt{2*{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{(W/L)}_{208}*I_{208}}+\sqrt{2*{\mathrm{\μ}}_n{C}_{\mathrm{ox}}{(W/L)}_{209}*I_{209}})+(V_{\mathrm{th}208}+V_{\mathrm{th}209})---\left(5\right)$

Wherein, (W/L) ₂₀₈(W/L) ₂₀₉Be respectively the channel width of the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209 and the ratio of channel length, I ₂₀₈And I ₂₀₉Be respectively the electric current that flows through the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209, V _Th208And V _Th209Be respectively the threshold voltage of the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209, V _Ov209And V _Th209Be respectively the driving voltage of the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209.Owing to the effect of the 5th current mirror, flow through the electric current I of the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209 ₂₀₈And I ₂₀₉Equal reference current I.

Therefore, will draw in formula (2) the substitution formula (5):

$V_{\mathrm{gs}208}+V_{\mathrm{gs}209}=\frac{2}{R_{220}}*(1-\frac{1}{\sqrt{n}})*(\sqrt{\frac{{(W/L)}_{208}}{{(W/L)}_{206}}}+\sqrt{\frac{{(W/L)}_{209}}{{(W/L)}_{206}}})+(V_{\mathrm{th}208}+V_{\mathrm{th}209})---\left(6\right)$

Because resistance R 220 is a negative temperature coefficient, then first of formula (6) equal sign right side is positive temperature coefficient, and the threshold voltage V of the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209 _Th208And V _Th209Be negative temperature coefficient, therefore, by being that the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209 select suitable dimensions, first of formula (6) equal sign right side and second variations in temperature can be offset, so two of the centres on formula (3) equal sign right side are temperature independent voltage drop.

For last two of formula (3) equal sign right side, by the tenth NMOS pipe M210 and the 11 NMOS pipe M211 that selects size match, identical as the size of the two, then can cancel out each other, therefore, last two of formula (3) equal sign right side also can be designed to and the irrelevant amount of variations in temperature.

In sum, the low pressure VCC of output voltage stabilizing circuit 23 outputs is reference voltages of a single order zero-temperature coefficient.In addition, when selecting the size of the 8th metal-oxide-semiconductor M208 and the 9th metal-oxide-semiconductor M209, can select bigger channel width W and channel length L, to reduce the influence that technology is brought low pressure VCC as far as possible.

In the level shifter circuit shown in Fig. 2, have only a PMOS pipe M201, the 2nd PMOS pipe M202, the 3rd NMOS pipe M203 and the 4th NMOS pipe M204, the 7th PMOS to manage M207, and the tenth NMOS pipe M210 and the 11 NMOS pipe M211 need realize by high-pressure process, and the 5th NMOS pipe M205 and the 6th NMOS pipe M206 can adopt low pressure process to realize owing to the shielding of the 3rd NMOS pipe M203 and the 4th NMOS pipe M204, thereby can greatly reduce to realize area.

In addition, as shown in Figure 4, between described output voltage stabilizing circuit 23 and low pressure generation circuit 22, can increase load compensation circuit 24.Described load compensation circuit 24 comprises the 6th current mirror, described the 6th current mirror comprises the 13 PMOS pipe M213 and the 14 PMOS pipe M214, the source electrode of the two all inserts input voltage VDD, and the grid of the two is connected to each other together, and grid and the drain electrode of the 14 PMOS pipe M214 link together.The drain electrode of the 13 PMOS pipe M213 is electrically connected with the grid of the tenth NMOS pipe M210, the drain electrode of the 14 PMOS pipe M214 is electrically connected with the drain electrode of 1 the 12 NMOS pipe M212, the grid of described the 12 NMOS pipe M212 is electrically connected with the grid of the tenth NMOS pipe M210, and source electrode is electrically connected with the source electrode of the 11 NMOS pipe M211.The compensation process of load compensation circuit 24 is as follows:

If it is heavy that load becomes suddenly, output low pressure VCC will descend, because the grid of the 12 NMOS pipe M212 and the 11 NMOS pipe M211 links together, thereby the gate source voltage difference of the 12 NMOS pipe M212 improves, and the electric current of the 12 NMOS pipe M212 will increase, and the electric current of the 6th current mirror increases simultaneously, and then the tenth NMOS pipe M210 and the electric current that is concatenated into the branch road on ground thereof increase, therefore, the grid voltage of the tenth NMOS pipe M210 improves, and then exports low pressure VCC and will improve.

The substrate of employed PMOS pipe can be connected on source electrode in level shifter circuit described in the utility model, also can be connected on more high potential place.

Being the utility model preferred embodiment only in sum, is not to be used for limiting practical range of the present utility model.Be that all equivalences of doing according to the content of the utility model claim change and modification, all should belong to technology category of the present utility model.

Claims (7)

1. a level shifter circuit is characterized in that: comprise that reference current generating circuit, low pressure produce circuit and output voltage stabilizing circuit; Wherein, reference current generating circuit provides reference current for low pressure produces circuit; Described low pressure produces circuit and comprises parasitic PNP, compensating resistance and low pressure metal-oxide-semiconductor, and parasitic PNP, compensating resistance and low pressure metal-oxide-semiconductor provide stable driving voltage for output voltage stabilizing circuit; Described driving voltage passes through first current mirror, exports stable low pressure by electric capacity of voltage regulation in output voltage stabilizing circuit.

2. level shifter circuit according to claim 1 is characterized in that: described first current mirror comprises that the tenth NMOS on the low pressure generation circuit manages the 11 NMOS pipe (M211) on (M210) and the output voltage stabilizing circuit; Wherein, the grid and the drain electrode of the tenth NMOS pipe link together, and described reference current is imported its drain electrode; The drain electrode of the 11 NMOS pipe (M211) inserts input voltage, inserts described electric capacity of voltage regulation between source electrode and the ground; Low pressure produces circuit and comprises two low pressure metal-oxide-semiconductors, be respectively the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor, the two grid and drain electrode separately links together, and the 8th metal-oxide-semiconductor and the source electrode of the tenth NMOS pipe (M210) and the annexation of the 9th metal-oxide-semiconductor guarantee that the gate source voltage of the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is in the conducting state of the two; Be connected described compensating resistance, the collector electrode of parasitic PNP and base earth between the emitter of the 9th metal-oxide-semiconductor and parasitic PNP.

3. level shifter circuit according to claim 2, it is characterized in that: described reference current generating circuit comprises second and third and four current mirrors, wherein, second current mirror comprises two measure-alike PMOS pipes (M201) and the 2nd PMOS pipe (M202), the source electrode of the two all inserts input voltage, grid is connected to each other, and the grid and the drain electrode of PMOS pipe (M201) link together; The 3rd current mirror comprises the 3rd NMOS pipe (M203) and the 4th NMOS pipe (M204), and the drain electrode of the two is electrically connected with the drain electrode of PMOS pipe (M201) and the drain electrode of the 2nd PMOS pipe (M202) respectively, and the grid of the two is connected to each other together; The drain electrode and the grid of the 4th NMOS pipe (M204) link together; The 4th current mirror comprises the 5th NMOS pipe (M205) and the 6th NMOS pipe (M206), the drain electrode of the two is electrically connected with the source electrode of the 3rd NMOS pipe (M203) and the source electrode of the 4th NMOS pipe (M204) respectively, the grid of the two is connected to each other together, the drain electrode and the grid of the 6th NMOS pipe (M206) link together, series resistor (R220) between the source electrode of the 6th NMOS pipe (M206) and the ground; Reference current generating circuit provides reference current by the 5th current mirror for low pressure produces circuit, the 5th current mirror comprises that described PMOS pipe (M201) and low pressure produce the 7th PMOS pipe (M207) on the circuit, the grid of the two links together, the source electrode of the 7th PMOS pipe (M207) inserts input voltage, and drain electrode is electrically connected with the drain electrode of described the tenth NMOS pipe (M210).

4. level shifter circuit according to claim 3 is characterized in that: produce increase load compensation circuit between the circuit at described output voltage stabilizing circuit and low pressure.

5. level shifter circuit according to claim 4, it is characterized in that: described load compensation circuit comprises the 6th current mirror, described the 6th current mirror comprises the 13 PMOS pipe (M213) and the 14 PMOS pipe (M214), the source electrode of the two all inserts input voltage, the grid of the two is connected to each other together, and the grid and the drain electrode of the 14 PMOS pipe (M214) link together; The drain electrode of the 13 PMOS pipe (M213) is electrically connected with the grid that the tenth NMOS manages (M210), the drain electrode of the 14 PMOS pipe (M214) is electrically connected with the drain electrode of 1 the 12 NMOS pipe (M212), the grid of described the 12 NMOS pipe (M212) is electrically connected with the grid that the tenth NMOS manages (M210), and source electrode is electrically connected with the source electrode of the 11 NMOS pipe (M211).

6. according to claim 3,4 or 5 described level shifter circuits, it is characterized in that: described resistance (R220) is negative temperature coefficient type resistance; The material of described compensating resistance is identical with the material of resistance (R220); Described the tenth NMOS pipe (M210) and the 11 NMOS manage the measure-alike of (M211).

7. level shifter circuit according to claim 6, it is characterized in that: described PMOS pipe (M201), the 2nd PMOS pipe (M202), the 3rd NMOS pipe (M203) and the 4th NMOS pipe (M204), the 7th PMOS manage (M207), and the tenth NMOS manages (M210) and the 11 NMOS pipe (M211) is a high-voltage MOS pipe; The 5th NMOS pipe (M205) and the 6th NMOS pipe (M206) are the low pressure metal-oxide-semiconductor.

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