CN104656732A - Voltage reference circuit - Google Patents
Voltage reference circuit Download PDFInfo
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- CN104656732A CN104656732A CN201410855579.XA CN201410855579A CN104656732A CN 104656732 A CN104656732 A CN 104656732A CN 201410855579 A CN201410855579 A CN 201410855579A CN 104656732 A CN104656732 A CN 104656732A
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Abstract
The invention discloses a voltage reference circuit which comprises a starting unit, a reference voltage generation unit, a regulating unit and an output buffering unit, wherein the starting unit is used for assisting the reference voltage generation unit in normal starting; the reference voltage generation unit is used for generating two or more paths of reference voltage and comprises two or more groups of resistor strings respectively coupled to the regulating unit; the groups of resistor strings are suitable for providing a selectable reference voltage range for the regulating unit; the regulating unit is used for selecting one reference voltage from the two or more paths of reference voltage; the output buffering unit is used for generating a reference signal array according to the reference voltage selected by the regulating unit. According to the voltage reference circuit, the reference voltage meeting the design requirement can be obtained under a process variation.
Description
Technical field
The invention belongs to electronic circuit technology field, particularly relate to a kind of voltage reference circuit.
Background technology
In current numeral, simulation and power-supply management system, in order to can correctly work, system needs temperature, supply voltage, load, the insensitive reference source of technological fluctuation.In actual applications for the consideration of cost, also often require the area reducing reference source, reduce its power consumption.In order on chip, the module of diverse location difference in functionality provides benchmark, need reference source will have certain driving force, and when keeping precision, there is multiple output valve.
Traditional electrical potential source is bandgap voltage reference, and its principle is the Δ V by adopting positive temperature coefficient (PTC)
bEwith the V of negative temperature coefficient
bEweighted sum obtains the reference voltage of temperature compensation, the benchmark finally obtained is exported and is substantially constant at about 1.25V.But in traditional peak point current source circuit, when there is process deviation, the adjustable range of reference voltage is less, is difficult to the reference voltage obtaining meeting designing requirement.For revising technological fluctuation to the impact of reference voltage, also require that redesign trims circuit.
Summary of the invention
The problem that the embodiment of the present invention solves is the reference voltage how obtaining meeting designing requirement when process deviation.
For solving the problem, the embodiment of the present invention provides a kind of voltage reference circuit, comprising: start unit, reference voltage generation unit, trim unit and export buffer cell;
Start unit, normally starts for helping described reference voltage generation unit;
Reference voltage generation unit, for generation of at least two-way reference voltage; Described reference voltage generation unit comprise be respectively coupled to described in trim at least two group resistance strings of unit; Trim unit described in described at least two group resistance strings are suitable for and optional reference voltage range is provided;
Trim unit, for selecting a reference voltage from described at least two-way reference voltage;
Export buffer cell, produce reference signal array for the reference voltage trimming Unit selection described in basis.
Optionally, described reference voltage generation unit comprises:
Current mirror module, for producing image current in the branch circuit of described reference voltage generation unit;
Peaking current mirror module, for producing peak point current in the branch circuit of described reference voltage generation unit;
First division module, for carrying out dividing potential drop to described reference voltage generation unit branch circuit, produces at least two-way reference voltage.
Optionally, described first division module comprises: the first resistance string, the second resistance string and the 3rd resistance string; Described peaking current mirror module comprises: the first transistor, transistor seconds and described second resistance string; Described current mirror module comprises: third transistor and the 4th transistor;
Described first resistance string, described second resistance string and described 3rd resistance string couple in turn, and one end of described first resistance string is coupled to the drain terminal of described transistor seconds, and one end of described 3rd resistance string is coupled to the drain terminal of described 4th transistor;
Unit is trimmed described in the tap of described first resistance string, described second resistance string and described 3rd resistance string is respectively coupled to;
The grid end of described the first transistor is coupled between described second resistance string and described 3rd resistance string, and drain terminal is coupled to the output terminal of described reference voltage generation unit to described start unit, source ground connection;
The grid end of described transistor seconds is coupled between described first resistance string and described second resistance string, source ground connection;
The grid end of described third transistor and drain terminal are all coupled to the output terminal of described reference voltage generation unit to described start unit, and source is coupled to supply voltage;
The grid end of described 4th transistor is coupled to the output terminal of described reference voltage generation unit to described start unit, and source is coupled to supply voltage.
Optionally, described start unit comprises:
Detection module, for detecting voltage or the electric current of described reference voltage generation unit;
Judge module, for according to the voltage of described reference voltage generation unit or electric current, judges whether described reference voltage generation unit starts;
Voltage pulls module, for when described reference voltage generation unit is not activated, pulls described reference voltage generation unit to depart from zero condition.
Optionally, described detection module comprises: the 5th transistor; Described judge module comprises: the 6th transistor, the 7th transistor and the 8th transistor; Described voltage pulls module to comprise: the 9th transistor;
The grid end of described 5th transistor is coupled to the input end of described start unit to described reference voltage generation unit, and source is coupled to supply voltage, and drain terminal is coupled to grid end and the drain terminal of described 6th transistor;
The source ground connection of described 6th transistor;
The grid end of described 7th transistor is coupled to the grid end of described 6th transistor, and drain terminal is coupled to drain terminal and the grid end of described 8th transistor, source ground connection;
The source of described 8th transistor is coupled to supply voltage;
The grid end of described 9th transistor is coupled to the grid end of described 8th transistor, and source couples with ground, and drain terminal is coupled to the input end of described start unit extremely described reference voltage generation unit.
Optionally, described detection module comprises: the tenth transistor; Described judge module comprises: the 11 transistor; Described voltage pulls module to comprise: the tenth two-transistor;
The grid end of described tenth transistor is coupled to the input end of described start unit to described reference voltage generation unit, and source is coupled to supply voltage, and drain terminal is coupled to the drain terminal of described 11 transistor and the grid end of described tenth two-transistor;
The grid end of described 11 transistor is coupled to the input end of described start unit to described reference voltage generation unit, source ground connection;
The source of described tenth two-transistor is coupled to described supply voltage, and drain terminal is coupled to the output terminal of described start unit to described reference voltage generation unit.
Optionally, trim unit described in comprise:
At least two-way gate-controlled switch of at least two-way reference voltage described in correspondence;
Code translator, for receiving gate control signal, and according to described gate control signal, gating one road reference voltage from described at least two-way reference voltage.
Optionally, described output buffer cell comprises: amplifier, Correctional tube, compensating module and division module;
Amplifier, for amplifying by the described reference voltage trimming unit and export;
Correctional tube, for stablizing described reference voltage;
Compensating module, for carrying out feedback compensation to the output voltage of described Correctional tube;
Second division module, for carrying out dividing potential drop to the output voltage of described Correctional tube, produces reference signal array.
Optionally, described amplifier comprises: the first operational transconductance amplifier; Described Correctional tube comprises: the 13 transistor; Described second division module comprises: the first divider resistance string; Described compensating module comprises: the first compensating module;
The output terminal of unit is trimmed described in the negative input end of described first operational transconductance amplifier is coupled to, positive input terminal is coupled to the place tap in described first divider resistance string, 3rd input end is coupled to offset side, four-input terminal is coupled to one end of described first compensating module, and output terminal is coupled to the grid end of described 13 transistor;
The other end of described first compensating module is coupled to the output terminal of described 13 transistor;
The source of described 13 transistor is coupled to supply voltage, and drain terminal is coupled to one end of described first divider resistance string;
The other end ground connection of described first divider resistance string, and the tap of described first divider resistance string exports described reference signal array.
Optionally, described amplifier comprises: the second operational transconductance amplifier; Described Correctional tube comprises: the 14 transistor; Described division module comprises: the second divider resistance string; Described compensating module comprises: the second compensating module;
The output terminal of unit is trimmed described in the positive input terminal of described second operational transconductance amplifier is coupled to, negative input end is coupled to the place tap in described second divider resistance string, 3rd input end is coupled to offset side, and output terminal is coupled to one end of described second compensating module and the grid end of described 14 transistor;
The other end ground connection of described second compensating module;
The drain terminal of described 14 transistor is coupled to supply voltage, and source is coupled to one end of described second divider resistance string;
The other end ground connection of described second divider resistance string, and the tap of described first divider resistance string exports described reference signal array.
Compared with prior art, the technical scheme of the embodiment of the present invention has the following advantages:
The reference voltage generation unit of the embodiment of the present invention, comprise at least two group resistance strings trimming unit described in being coupled to, increase the adjustable range of reference voltage, therefore when there is process deviation, can be adjusted by the tap of the resistance string of described at least two groups, obtain desirable output reference voltage, thus achieve with less cost and trim unit.
Further, owing to all adopting CMOS technology, therefore there is simple and that realization is convenient, compatible good, portability is good on other CMOS technology lines advantage of structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of voltage reference circuit of the embodiment of the present invention;
Fig. 2 is the structural representation of a kind of resistance string of the embodiment of the present invention;
Fig. 3 is reference voltage generation unit in a kind of voltage reference circuit of the embodiment of the present invention and the structural representation trimming unit;
Fig. 4 is the structural representation of a kind of start unit of the embodiment of the present invention;
Fig. 5 is the structural representation of the another kind of start unit of the embodiment of the present invention;
Fig. 6 is the structural representation of a kind of voltage reference circuit of the embodiment of the present invention;
Fig. 7 is a kind of structural representation exporting buffer cell of the embodiment of the present invention;
Fig. 8 is the structural representation of the another kind output buffer cell of the embodiment of the present invention.
Embodiment
Traditional voltage source is bandgap voltage reference, and its principle is the Δ V by adopting positive temperature coefficient (PTC)
bEwith the V of negative temperature coefficient
bEweighted sum obtains the reference voltage of temperature compensation, the benchmark finally obtained is exported and is substantially constant at about 1.25V.But in traditional peak point current source circuit, when there is process deviation, the adjustable range of reference voltage is very little, is difficult to the reference voltage obtaining meeting designing requirement.For revising technological fluctuation to the impact of reference voltage, also require that redesign trims circuit.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 1 shows the structural representation of a kind of voltage reference circuit in the embodiment of the present invention.As shown in Figure 1, described voltage reference circuit can comprise: start unit 101, reference voltage generation unit 102, trim unit 103 and export buffer cell 104.
Described start unit 101 normally starts for helping described reference voltage generation unit.
In concrete enforcement, described start unit 101 can comprise: detection module, judge module and voltage pull module.Wherein, described detection module is for detecting voltage or the electric current of described reference voltage generation unit 102.Described judge module.For according to the voltage of described reference voltage generation unit 102 or electric current, judge whether described reference voltage generation unit 102 starts.Described voltage pulls module, for when described reference voltage generation unit 102 is not activated, pulls described reference voltage generation unit 102 to depart from zero condition.
Described reference voltage generation unit 102 is for generation of at least two-way reference voltage.
In concrete enforcement, described reference voltage generation unit 102 can comprise be respectively coupled to described in trim at least two group resistance strings of unit 103.As shown in Figure 2, can pass through from described at least two group resistance string R
aand R
bthe corresponding tap V of middle extraction
1, V
2, V
3v
n-2, V
n-1, V
n, and trim unit 103 described in described tap being connected to, trim unit 103 described in namely can be and optional reference voltage range is provided, thus increase the adjustable range of reference voltage.
In concrete enforcement, described reference voltage generation unit 102 can comprise current mirror module, peaking current mirror module and division module.
Wherein, described current mirror module is used for producing image current in the branch circuit of described reference voltage generation unit 102.Described peaking current mirror module is used for producing peak point current in the branch circuit of described reference voltage generation unit 102.Described division module, for carrying out dividing potential drop to described reference voltage generation unit 102 branch circuit, produces at least two-way reference voltage.
In concrete enforcement, described current mirror module and described peaking current mirror model calling, and described current mirror module is linear current-mirror structure, described peaking current mirror module is nonlinear current-mirror structure, therefore, both intersection are the duty residing for described reference voltage generation unit 102 reality.
In concrete enforcement, described division module can comprise at least two above-mentioned group resistance strings, for carrying out dividing potential drop, and produces at least two-way reference voltage.
The described unit 103 that trims for selecting a reference voltage from described at least two-way reference voltage, when occurring that the process deviation of device causes the output voltage skew of described reference voltage generation unit 102, just carry out selection correction by the described unit 103 that trims.
The reference voltage generation reference signal array that described output buffer cell 104 is selected for trimming unit 103 described in basis.
The reference voltage generation unit 102 of the embodiment of the present invention, by increasing resistance string R1 and resistance string R3, increase the adjustable range of reference voltage, therefore when there is process deviation, can be adjusted by the tap of the resistance string of described at least two groups, obtain desirable output reference voltage, thus achieve with less cost and trim unit 103.
Fig. 3 shows the reference voltage generation unit 102 in a kind of voltage reference circuit of the embodiment of the present invention and trims the structural representation of unit 103.Shown in composition graphs 1 and Fig. 3, described first division module in described reference voltage generation unit 102 can comprise: the first resistance string R1, the second resistance string R2 and the 3rd resistance string R3.Peaking current mirror module in described reference voltage generation unit 102 can comprise: the first transistor M1, transistor seconds M2 and described second resistance string R2.Current mirror module in described reference voltage generation unit 102 can comprise: third transistor M3 and the 4th transistor M4.
Second resistance string R2 has two kinds of functions herein, and one is the Voltage to current transducer resistance in conventional peak current source, and two is that the resistance that trims of benchmark provides voltage tap.Because resistance is multiplexing, because this reducing the quantity of resistance, reduce cost.
Described first resistance string R1, described second resistance string R2 and described 3rd resistance string R3 couple in turn, and one end of described first resistance string R1 is coupled to the drain terminal of described transistor seconds M2, one end of described 3rd resistance string R3 is coupled to the drain terminal of described 4th transistor M4.Trim unit 103 described in the tap of described first resistance string R1, described second resistance string R2 and described 3rd resistance string R3 is respectively coupled to, form reference voltage V 1 ~ VN output terminal as shown in Figure 2.
The grid end of described the first transistor M1 is coupled between described second resistance string R2 and described 3rd resistance string R3, and drain terminal is coupled to the output terminal of described reference voltage generation unit to described start unit, source ground connection.
The grid end of described transistor seconds M2 is coupled between described first resistance string R1 and described second resistance string R2, source ground connection.
The grid end of described third transistor M3 and drain terminal are all coupled to the output terminal of described reference voltage generation unit 102 to described start unit 101, and source is coupled to supply voltage Vdd.
The grid end of described 4th transistor M4 is coupled to the output terminal of described reference voltage generation unit to described start unit, and source is coupled to supply voltage Vdd.
In concrete enforcement, described the first transistor M1 and described transistor seconds M2 is nmos pass transistor; Described third transistor M3 and described 4th transistor M4 is PMOS transistor.Described third transistor M3's and described 4th transistor M4 is measure-alike, and both form the current mirror module of described reference voltage generation unit 102.Therefore the electric current flowing through two branch roads in described reference voltage generation unit 102 is equal, if be I
d.
The grid appearance etc. of described the first transistor M1 and described transistor seconds M2, and the grid width of described transistor seconds M2 is K times of the first transistor M1.As shown in Figure 3, because the grid end of described the first transistor M1 and the grid end of described transistor seconds M2 are respectively coupled to the two ends of described resistance string R2, therefore the difference of both gate source voltages is the voltage Δ V on resistance string R2
gS=V
gS2-V
gS1, and then described electric current I can be obtained
d=Δ V
gS/ R
2.
In concrete enforcement, described third transistor M3 and described 4th transistor M4 is nmos pass transistor.The expression formula of the first-order linear of the threshold voltage temperature characterisitic of nmos pass transistor is:
V
THN(T)＝V
THN(T
0)-α
VTHN(T-T
0)； (1)
Wherein, T
0for reference temperature, V
tHN(T
0) be NMOS threshold value under reference temperature, α
vTHNfor the temperature factor of NMOS tube threshold voltage.
NMOS mobility [mu]
nthe expression formula of temperature characterisitic is:
Wherein, μ
n(T
0) be the value of the NMOS mobility under reference temperature, α
μ nfor the temperature factor of NMOS mobility.
In actual applications, described third transistor M3 and the 4th transistor M4 works in sub-threshold region or saturation region.The situation only working in saturation region for third transistor M3 and the 4th transistor M4 is herein described.Now, the electric current I of two branch roads is flow through
dequal.
Can obtain according to circuit node voltage relationship: V
gS2=V
gS1+ I
dr
2;
Ignore higher-order effect, be then operated in the metal-oxide-semiconductor drain-source current I of pipe saturation region
dSwith grid source V
gSvoltage relationship is:
By the working current I of described the first transistor M1 and described transistor seconds M2
d, and size value W/L, technological parameter μ
n, C
oxbring described formula (3) respectively into can obtain:
Formula of reduction (4) can obtain:
Wherein
Be described Δ V
gS.
Abbreviation above formula obtains described I
dexpression formula be:
The temperature coefficient supposing described second resistance string R2 is zero, can obtain according to formula (2):
Wherein,
To sum up, according to expression formula (7), (8) formula, because formula (8) is greater than 0, therefore I
dthere is positive temperature coefficient.
Suppose that p tap in the large resistance string be made up of described first resistance string R1, described second resistance string R2 and described 3rd resistance string R3 is connected to the grid end of described the first transistor M1, i.e. V
p=V
gS1, then reference voltage V
i, the value of i ∈ (1, N) is:
V
i(T)＝V
GS1+V
i2p＝V
THN1+V
OD1+V
i-V
p
Wherein, in formula (9), V
gS1for the gate source voltage of described the first transistor M1, V
i2pin resistance string 5 i-th tap and p tap voltage poor, R
ufor the resistance of resistance in resistance string as shown in Figure 2.
From formula (9), the threshold voltage V of described the first transistor M1
tHN1=V
tHN1(T
0)-α
vTHN1(T-T
0), therefore it has negative temperature coefficient;
therefore V
oD1there is positive temperature coefficient;
therefore V
i2ptemperature coefficient depend on V
itap position and V
pthe relation of tap position.If i>p, being then positive temperature coefficient (PTC), if i<p, is then negative temperature coefficient.
As fully visible, the embodiment of the present invention produces nucleus module based on conventional peak current source structure as reference voltage, utilize the positive temperature coefficient (PTC) of two branch currents of the positive temperature coefficient (PTC) of the negative temperature characteristic of metal-oxide-semiconductor threshold voltage in peak current source, overdrive voltage, mobility negative temperature coefficient temperature characterisitic, peak current source, obtain the reference voltage through temperature compensation, thus can avoid using more branch road and operational amplifier.Be compared to traditional CMOS benchmark, described reference voltage generation unit 102, owing to reducing branch road quantity, thus greatly reduces number of devices and circuit power consumption, also reduces the impact that device mismatch may cause output valve simultaneously.
Fig. 4 is the structural representation of a kind of start unit 101 of the embodiment of the present invention.Shown in composition graphs 1 and Fig. 4, the described detection module in described start unit 101 can comprise: the 5th transistor M5.Described judge module in described start unit 101 can comprise: the 6th transistor M6, the 7th transistor M7 and the 8th transistor M8; Described voltage in described start unit 101 pulls module to comprise: the 9th transistor M9.
The grid end of described 5th transistor M5 is coupled to the input end that described start unit 101 couples described reference voltage generation unit 102, and source is coupled to supply voltage Vdd, and drain terminal is coupled to grid end and the drain terminal of described 6th transistor M6.
The source ground connection of described 6th transistor M6.
The grid end of described 7th transistor M7 is coupled to the grid end of described 6th transistor M6, and drain terminal is coupled to drain terminal and the grid end of described 8th transistor M8, source ground connection.
The source of described 8th transistor M8 is coupled to supply voltage Vdd.
The grid end of described 9th transistor M9 is coupled to the grid end of described 8th transistor M8, source with couple, drain terminal is coupled to the input end of described start unit 101 to described reference voltage generation unit 102.
In the present embodiment, described 5th transistor M5 and described 8th transistor M8 is PMOS; Described 6th transistor M6, the 7th transistor M7 and described 9th transistor M9 are NMOS tube, and the output terminal of the input end of described start unit 101 and described start unit 101 is all coupled to the gate terminal of third transistor M3 in reference voltage generation unit 102 as shown in Figure 3.Below sketch the principle of work of described start unit 101:
Shown in composition graphs 1 and Fig. 3, described 5th transistor M5 detects the grid by being connected to third transistor M3 in described reference voltage generation unit 102, carrys out the electric current that mirror image flows through described third transistor M3.If described reference voltage generation unit 102 does not normally start, then work in zero condition, the electric current namely in described third transistor M3 is zero.Therefore the electric current in the 5th transistor M5 is also zero, makes the electric current flowing through the 6th transistor M6 that diode connects also be zero.The grid potential of described 7th transistor M7 is zero, and described 7th transistor M7 is turned off.The grid of the 8th transistor M8 of now diode connection and the voltage of drain electrode are close to V
dD, described 9th transistor M9 is opened, produces the pull-down current I that is greater than zero
pull, make described third transistor M3 make reference voltage generation unit 102 depart from zero condition by electric current.
If described reference voltage generation unit 102 normally starts, then there is quiescent current in described 5th transistor M5 and described 6th transistor M6, makes described 7th transistor M7 conducting.Described 8th transistor M8 manages as falling than managing, due to the grid of now described 8th transistor M8 and drain voltage lower, therefore make described 9th transistor M9 turn off, make described pull-down current I
pullbe zero.
Described Fig. 5 is the another kind of start unit 101 of the embodiment of the present invention.Shown in composition graphs 1 and Fig. 5, described detection module can comprise: the tenth transistor M10; Described judge module can comprise: the 11 transistor M11; Described voltage pulls module to comprise: the tenth two-transistor M12.
The grid end of described tenth transistor M10 is coupled to the input end of described start unit 101 to described reference voltage generation unit 102, source is coupled to supply voltage Vdd, and drain terminal is coupled to the drain terminal of described 11 transistor M11 and the grid end of described tenth two-transistor M12.
The grid end of described 11 transistor M11 is coupled to the input end that described start unit 101 couples described reference voltage generation unit 102, source ground connection.
The source of described tenth two-transistor M12 is coupled to described supply voltage Vdd, and drain terminal is coupled to the output terminal of described start unit 101 to described reference voltage generation unit 102.
In the present embodiment, described tenth transistor M10 and described tenth two-transistor M12 is PMOS; Described 11 transistor M11 is NMOS tube, and the input end of described start unit 101 is coupled to the gate terminal of third transistor M3 in reference voltage generation unit 102 as illustrated in fig.x, the output terminal of described start unit 101 is coupled to the source terminal of transistor seconds M2 described in described reference voltage generation unit 102.Below sketch the principle of work of described start unit 101:
Described 11 transistor M11 detects the grid terminal voltage value of described third transistor M3, if now reference voltage generation unit 102 does not normally start, then the grid terminal voltage value of described third transistor M3 is supply voltage Vdd, simultaneously because the drain terminal voltage of described tenth transistor M10 and described 11 transistor M11 is GND, cause described tenth two-transistor M12 conducting, produce pull-up current I
pull, described pull-up current I
pullbe connected to the grid end of transistor seconds M2 described in described reference voltage generation unit 102, make described reference voltage generation unit 102 depart from zero current duty.
If described reference voltage generation unit 102 normally starts, then the grid terminal voltage value of described third transistor M3 is not supply voltage Vdd, now the drain terminal voltage of described tenth transistor M10 and described 11 transistor M11 is supply voltage Vdd, described tenth two-transistor M12 is turned off, described pull-up current I
pullvalue be zero.
In an embodiment of the present invention, the reference voltage exported to make circuit still can obtain design load when skew occurs technique, described in trim unit 103 and can comprise: at least two-way gate-controlled switch of at least two-way reference voltage described in correspondence; Code translator, for receiving gate control signal, and according to described gate control signal, gating one road reference voltage from described at least two-way reference voltage.
Fig. 6 is a kind of structural representation trimming unit 103 of the embodiment of the present invention.Shown in composition graphs 1 and Fig. 6, described in trim unit 103 and comprise N number of gate-controlled switch T1 ~ TN, and be connected respectively to Multi-path reference voltage V1 ~ VN that described reference voltage generation unit 102 exports.M position control signal is as gating signal, and obtained the value of the control signal C1 ~ CN of each switch according to the value of described M position gating signal by code translator, in the institute of M position gating signal likely under combined situation, C1 ~ CN only has a signal for high, namely T1 ~ TN only has a switch conduction, makes final reference voltage V
mUXonly be connected to a voltage in V1 ~ VN.
In embodiments of the present invention, described output buffer cell 104 can comprise: amplifier, Correctional tube, compensating module and division module.Wherein, described amplifier is for amplifying by the described reference voltage trimming unit 103 and export; Described Correctional tube is used for stablizing described reference voltage; Described compensating module is used for the compensation output voltage of described Correctional tube being carried out to stability; Described division module is used for carrying out dividing potential drop to the output voltage of described Correctional tube, produces reference signal array.
Fig. 7 is that the one of this aspect embodiment exports buffer cell 104.As shown in Figure 7, the amplifier exported in buffer cell 104 can comprise: the first operational transconductance amplifier A1; The described Correctional tube exported in buffer cell 104 can comprise: the 13 transistor M13; Described second division module exported in buffer cell 104 can comprise: the first divider resistance string; The compensating module exported in buffer cell 104 can comprise: the first compensating module.
In concrete enforcement, as shown in Figure 7, described 13 transistor M13 is PMOS.
The output terminal of unit 103 is trimmed described in the negative input end of described first operational transconductance amplifier A1 is coupled to, positive input terminal is coupled to the place tap in described first divider resistance string RFb1 ~ RFbm, 3rd input end is coupled to offset side, four-input terminal is coupled to one end of described first compensating module, and output terminal is coupled to the grid end of described 13 transistor M13.
The other end of described first compensating module is coupled to the output terminal of described 13 transistor M13.
The source of described 13 transistor M13 is coupled to supply voltage Vdd, and drain terminal is coupled to one end of described first divider resistance string.
The other end ground connection of described first divider resistance string, and the tap of described first divider resistance string exports described reference signal array VRef1 ~ VRefm.
Fig. 8 is that the another kind of this aspect embodiment exports buffer cell 104.As shown in Figure 8, the amplifier exported in buffer cell 104 can comprise: the second operational transconductance amplifier A2; Described Correctional tube can comprise: the 14 transistor M14; Described division module can comprise: the second divider resistance string; Described compensating module can comprise: the second compensating module.
In concrete enforcement, as shown in Figure 8, described 14 transistor M14 is NMOS tube.
Trim the output terminal of unit 103 described in the positive input terminal of described second operational transconductance amplifier A2 is coupled to, negative input end is coupled to described second divider resistance string R
fb1~ R
fbmin place tap, the 3rd input end is coupled to offset side, and output terminal is coupled to one end of described second compensating module and the grid end of described 14 transistor M14.
The other end ground connection of described second compensating module.
The drain terminal of described 14 transistor M14 is coupled to supply voltage Vdd, and source is coupled to one end of described second divider resistance string.
The other end ground connection of described second divider resistance string, and the tap of described first divider resistance string exports described reference signal array V
ref1~ V
refm.
Reference output voltage is positioned at the output terminal of described output buffer cell 104, therefore, it is possible to the circuit of effectively isolating below and reference voltage array produce circuit, reduces rear class noise to the impact of reference voltage generation unit 102, promotes circuit noise robustness.Simultaneously, again because described output buffer cell 104 has stronger driving force, the benchmark of the overall situation can be provided for larger integrated circuit, thus do not need to add other buffer circuits, and described output buffer cell 104 also have transient response faster.
As fully visible, a kind of voltage reference circuit of the embodiment of the present invention all adopts CMOS technology, owing to only comprising four kinds of devices such as NMOS, PMOS, polysilicon resistance, electric capacity in circuit, therefore has the simple advantage of structure.Further, standard or other special CMOS technology lines realize conveniently, effectively, compatible good, portability is good.
This utilizes the negative temperature coefficient of two branch currents of the positive temperature system of the negative temperature characteristic of metal-oxide-semiconductor threshold voltage in common peak current source, overdrive voltage, mobility negative temperature coefficient temperature characterisitic, peak current source, realize compensating, avoid using more branch road and operational amplifier, be compared to other traditional CMOS benchmark, reference voltage generation unit is by reducing branch road quantity, greatly reduce the quantity of device and the power consumption of circuit, the impact that the mismatch simultaneously also reducing device causes output valve.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a voltage reference circuit, is characterized in that, comprising: start unit, reference voltage generation unit, trim unit and export buffer cell;
Start unit, normally starts for helping described reference voltage generation unit;
Reference voltage generation unit, for generation of at least two-way reference voltage; Described reference voltage generation unit comprise be respectively coupled to described in trim at least two group resistance strings of unit; Trim unit described in described at least two group resistance strings are suitable for and optional reference voltage range is provided;
Trim unit, for selecting a reference voltage from described at least two-way reference voltage;
Export buffer cell, produce reference signal array for the reference voltage trimming Unit selection described in basis.
2. voltage reference circuit as claimed in claim 1, it is characterized in that, described reference voltage generation unit comprises:
Current mirror module, for producing image current in the branch circuit of described reference voltage generation unit;
Peaking current mirror module, for producing peak point current in the branch circuit of described reference voltage generation unit;
First division module, for carrying out dividing potential drop to described reference voltage generation unit branch circuit, produces at least two-way reference voltage.
3. voltage reference circuit as claimed in claim 2, is characterized in that,
Described first division module comprises: the first resistance string, the second resistance string and the 3rd resistance string; Described peaking current mirror module comprises: the first transistor, transistor seconds and described second resistance string; Described current mirror module comprises: third transistor and the 4th transistor;
Described first resistance string, described second resistance string and described 3rd resistance string couple in turn, and one end of described first resistance string is coupled to the drain terminal of described transistor seconds, and one end of described 3rd resistance string is coupled to the drain terminal of described 4th transistor;
Unit is trimmed described in the tap of described first resistance string, described second resistance string and described 3rd resistance string is respectively coupled to;
The grid end of described the first transistor is coupled between described second resistance string and described 3rd resistance string, and drain terminal is coupled to the output terminal of described reference voltage generation unit to described start unit, source ground connection;
The grid end of described transistor seconds is coupled between described first resistance string and described second resistance string, source ground connection;
The grid end of described third transistor and drain terminal are all coupled to the output terminal of described reference voltage generation unit to described start unit, and source is coupled to supply voltage;
The grid end of described 4th transistor is coupled to the output terminal of described reference voltage generation unit to described start unit, and source is coupled to supply voltage.
4. voltage reference circuit as claimed in claim 1, it is characterized in that, described start unit comprises:
Detection module, for detecting voltage or the electric current of described reference voltage generation unit;
Judge module, for according to the voltage of described reference voltage generation unit or electric current, judges whether described reference voltage generation unit starts;
Voltage pulls module, for when described reference voltage generation unit is not activated, pulls described reference voltage generation unit to depart from zero condition.
5. voltage reference circuit as claimed in claim 4, is characterized in that,
Described detection module comprises: the 5th transistor; Described judge module comprises: the 6th transistor, the 7th transistor and the 8th transistor; Described voltage pulls module to comprise: the 9th transistor;
The grid end of described 5th transistor is coupled to the input end of described start unit to described reference voltage generation unit, and source is coupled to supply voltage, and drain terminal is coupled to grid end and the drain terminal of described 6th transistor;
The source ground connection of described 6th transistor;
The grid end of described 7th transistor is coupled to the grid end of described 6th transistor, and drain terminal is coupled to drain terminal and the grid end of described 8th transistor, source ground connection;
The source of described 8th transistor is coupled to supply voltage;
The grid end of described 9th transistor is coupled to the grid end of described 8th transistor, and source couples with ground, and drain terminal is coupled to the input end of described start unit extremely described reference voltage generation unit.
6. voltage reference circuit as claimed in claim 4, is characterized in that,
Described detection module comprises: the tenth transistor; Described judge module comprises: the 11 transistor; Described voltage pulls module to comprise: the tenth two-transistor;
The grid end of described tenth transistor is coupled to the input end of described start unit to described reference voltage generation unit, and source is coupled to supply voltage, and drain terminal is coupled to the drain terminal of described 11 transistor and the grid end of described tenth two-transistor;
The grid end of described 11 transistor is coupled to the input end of described start unit to described reference voltage generation unit, source ground connection;
The source of described tenth two-transistor is coupled to described supply voltage, and drain terminal is coupled to the output terminal of described start unit to described reference voltage generation unit.
7. voltage reference circuit as claimed in claim 1, is characterized in that, described in trim unit and comprise:
At least two-way gate-controlled switch of at least two-way reference voltage described in correspondence;
Code translator, for receiving gate control signal, and according to described gate control signal, gating one road reference voltage from described at least two-way reference voltage.
8. voltage reference circuit as claimed in claim 1, it is characterized in that, described output buffer cell comprises:
Amplifier, Correctional tube, compensating module and division module;
Amplifier, for amplifying by the described reference voltage trimming unit and export;
Correctional tube, for stablizing described reference voltage;
Compensating module, for carrying out feedback compensation to the output voltage of described Correctional tube;
Second division module, for carrying out dividing potential drop to the output voltage of described Correctional tube, produces reference signal array.
9. voltage reference circuit as claimed in claim 8, is characterized in that,
Described amplifier comprises: the first operational transconductance amplifier; Described Correctional tube comprises: the 13 transistor; Described second division module comprises: the first divider resistance string; Described compensating module comprises: the first compensating module;
The output terminal of unit is trimmed described in the negative input end of described first operational transconductance amplifier is coupled to, positive input terminal is coupled to the place tap in described first divider resistance string, 3rd input end is coupled to offset side, four-input terminal is coupled to one end of described first compensating module, and output terminal is coupled to the grid end of described 13 transistor;
The other end of described first compensating module is coupled to the output terminal of described 13 transistor;
The source of described 13 transistor is coupled to supply voltage, and drain terminal is coupled to one end of described first divider resistance string;
The other end ground connection of described first divider resistance string, and the tap of described first divider resistance string exports described reference signal array.
10. voltage reference circuit as claimed in claim 8, is characterized in that,
Described amplifier comprises: the second operational transconductance amplifier; Described Correctional tube comprises: the 14 transistor;
Described division module comprises: the second divider resistance string; Described compensating module comprises: the second compensating module;
The output terminal of unit is trimmed described in the positive input terminal of described second operational transconductance amplifier is coupled to, negative input end is coupled to the place tap in described second divider resistance string, 3rd input end is coupled to offset side, and output terminal is coupled to one end of described second compensating module and the grid end of described 14 transistor;
The other end ground connection of described second compensating module;
The drain terminal of described 14 transistor is coupled to supply voltage, and source is coupled to one end of described second divider resistance string;
The other end ground connection of described second divider resistance string, and the tap of described first divider resistance string exports described reference signal array.
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Effective date of registration: 20171101 Address after: Jiaxing City, Zhejiang province 314100 Jiashan Huimin street 1 Building 2 Taisheng Road No. 111 building 201 room Patentee after: Galaxycore Microelectronics (Zhejiang) Co., Ltd. Address before: 201203 Shanghai, Pudong New Area, summer lane, Lane 2, building No. 560, 11F Patentee before: Galaxycore Microelectronics (Shanghai) Co., Ltd. |
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